Product How-to: Fully utilize TSMC s 28HPC process

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1 Product How-to: Fully utilize TSMC s 28HPC process Ken Brock - April 13, 2015 In September 2014, TSMC released its third major 28 nanometer (nm) process into volume production 28HPC. Millions of production wafers have come out of TSMC s first two 28-nm processes (the poly SiON 28LP and high-k Metal Gate 28HP/28HPL/28HPM). With 28HPC, TSMC has optimized the process for mobile and consumer devices need for balance between performance and cost. Using a combination of this process technology and high-quality standard cell logic libraries designed specifically for this process, designers can achieve their performance, power and area goals while mitigating schedule risk. This article describes five areas where designers can take advantage of this new process with the latest logic library technology to optimize the performance, power and area of their system on chips (SoCs). First, designers can improve SoC performance by using the global slow and fast (SSG, FFG) signoff corners enabled by TSMC s tighter process controls with 28HPC. The improved performance enables the use of lower drive (smaller) logic cells to close critical timing paths. Second, the 28HPC process reduces area, and therefore cost, as relaxed process rules enable library providers to deliver shorter cells with improved routability. Third, these same relaxed rules enable longer channel lengths to be drawn than could be drawn with the 28HPM process to reduce leakage power by up to 50% without use of expensive lithography-based gate biasing. Fourth, TSMC s tighter process controls for the 28HPC process cut power consumption by reducing leakage by 20% in its corner models. Fifth, new logic library features introduced for the 28HPC process, such as multi-delay, multi-setup and multi-bit flip-flops (MBFF), help designers optimize their processor cores for performance and power. The combination of innovative process technology and library design capabilities along with the latest EDA tool innovations and flows enable SoC designers to use their design skills to produce the highest performance, lowest cost designs consuming the lowest power. 1. Improved SoC Performance with global corner signoff Logic libraries have traditionally been developed with total corner process/voltage/temperature (PVT) simulation corners to reflect the typical P channel and N channel transistor performance, the statistical slowest performance (slow-slow or SS for 3 sigma), and fastest performance (fast-fast, or FF for 3 sigma). These corners are used to simulate typical expected performance, worst case performance (for flip-flop setup) and best case performance (for flip-flop hold) and include the expected die to die, wafer to wafer and lot to lot variability to assure yield. Because of reduced process variability, TSMC is able to deliver high yielding silicon at a new corner called SSG (for global) which provides a 10 to 15% performance boost over their previous 28HPM process, which required the more conservative SS signoff (Figure 1). The process variability improvement can enable processors to run 10 to 15% faster so a 28HPC logic library must be able to

2 support the additional dynamic power and electro-migration requirements for operating circuits at higher speeds. Figure 1. TSMC 28HPC SSG corner signoff provides a 10 to 15% performance boost over the 28HPM SS corner signoff 2. Reduced Gate Leakage with Reduced Process Variability The HPC process variability improvements reduce transistor leakage so the 28HPC process will show a reduction in leakage of approximately 20% compared to 28HPM based on different process options and conditions (Figure 2).

3 Figure 2. TSMC 28HPC FFG corner signoff shows a reduction in leakage of approximately 20% compared to 28HPM FFG corner signoff 3. Reduced Gate Leakage with Longer Channel Lengths Changes in the TSMC design rules driven by process improvements enable logic libraries to be drawn with multiple gate lengths for a greater range than was possible with the TSMC 28HPM process (Figure 3). At the same time, the new relaxed design rules remove some lithography steps to enable cells drawn with 30 nm, 35 nm, and 40 nm to expand the performance/leakage profile for each process implant variant with a slightly larger gate-to-gate pitch.

4 Figure 3. The top diagram shows more space for the contacts with the 140-nm pitch and 3 gate lengths of the TSMC 28HPC process compared to the 28HPM process on the bottom This wider range of gate lengths and associated lithography simplification enables designers to realize greater ranges of performance leakage tradeoffs for their designs using 28HPC-optimized logic libraries and the latest leakage recovery features in synthesis and place and route tools. 4. Relaxed Design Rules Enable Ultra High Density TSMC s relaxed design rules and higher performance in the 28HPC process enable designers to use shorter cell height in logic libraries to decrease chip area for some blocks if they can meet the timing requirements of the block with those reduced height cells. There is a trade-off between using shorter libraries and achieving higher speeds, as the shorter libraries require higher drive cells which are larger and can negate or even reverse any area savings with a larger block (Figure 4). Each library has a sweet spot between cell height and performance that can offer optimal results- -but a shorter cell height is not always the best idea.

5 Figure 4: At lower frequencies, a shorter library can be the optimal solution for some blocks That said, TSMC s relaxed design rules enable shorter cells to be more routable providing higher utilization through improved pin access, if the logic library provider crafts the standard cell layouts to take advantage of the latest features designed into the place and route tools. 5. Innovative Logic Library Design for Significant Block PPA Improvements Combining the benefits of this new TSMC 28HPC process with innovative logic library design and optimized layout provides design engineers creating blocks of digital logic from RTL through synthesis and place and route with several advantages. Using optimized logic library circuits, such as combinational cells, multi-setup/multi-delay flops and multi-bit flip-flops (MBFF), with the TSMC 28HPC process provide power, performance and area (PPA) benefits. Combinational Cells Optimizing register-to-register paths requires a rich standard cell library that includes the appropriate functions, drive strengths, and implementation variants. A rich set of optimized functions (NAND, NOR, AND, OR, Inverter, buffers, XOR, XNOR, MUX, adders, compressors, etc.) are necessary for synthesis to create optimal designs and optimized layout techniques are needed to get the most out of the latest routing algorithms to eliminate congestions. Advanced synthesis and place-and-route tools can take advantage of a rich set of drive strengths to optimally handle the different fanouts and loads created by the design topology and physical distances between cells. Sequential Cells The setup plus the delay time of flip-flops is sometimes referred to as the dead or black hole time. Like clock uncertainty, this time eats into every clock cycle that could otherwise be doing useful computational work. Multiple sets of high-performance flip-flops are required to optimally manage this dead time. Delay-optimized flops (multi-delay flops) rapidly launch signals into critical path logic clusters and setup-optimized flops (multi-setup flops) capture registers to extend the

6 available clock cycle in several increments (Figure 5). Synthesis and routing optimization tools can be effectively constrained to use these multi-setup/multi-delay flip-flop sets for maximum speed, resulting in a 15 to 20% performance improvement. Figure 5: Sequential cells are used to resolve high-performance core design challenges. Multiple flop variants enable targeted optimization. Figure 6: Combining two single-bit flops into a dual flop with shared clocking optimizes area and dynamic and leakage power Multi-bit flip-flops provide a set of additional flops that have been optimized for power and area with a minor tradeoff in performance and placement flexibility. The flops share a common clock pin, which decreases the overall clock loading of the N flops in the multi-bit flop cell, reduces area with a corresponding reduction in leakage, and reduces dynamic power on the clock tree significantly (up

7 to 50% for a dual flop, more for quad or octal) (Figure 6). Multi-bit flip-flops are typically used in blocks that are not in the critical path of the highest chip operating frequency. They range from small, bus-oriented registers of SoC configuration data that are only clocked at power up, to major datapaths that are clocked every cycle and with a number of variants in between. SoC designers use the replacement ratio, measured by how many of the standard flops in the design can be replaced by their multi-bit equivalents and the resulting PPA improvements, to determine their overall chip power and area savings. The single-bit flip-flops to be replaced with multi-bit flip-flops must have the same function (clock edge, set/reset and scan configuration). As an example, Figure 7 shows a 32-bit processor being synthesized with a logic library for TSMC 28HPM (blue line) and again with the same library characterized to the TSMC 28HPC process (orange line), where you can see greater performance in less area. Including innovative cells such as those in the Synopsys High Performance Core Design Kit enables SoC designers to achieve smaller area for a given frequency and a higher top end frequency as seen in the dotted orange and blue lines. Figure 7: Comparison of the 28HPM process with the 28HPC process using Synopsys logic libraries and adding the Synopsys HPC Design Kit libraries to harden a 32-bit processor by sweeping timing constraints for a synthesized block until the library can no longer close timing Integration with Latest Digital EDA Tool Features Logic libraries for the TSMC 28HPC process must be designed to be synthesized, placed, routed, validated and optimized by digital EDA tools for timing, power and design rule compliance through design flows integrated with synthesis, place and route, design rules constraints and other tools. Digital EDA tools and flows enable designers to take full advantage of the circuit innovations such as multi-bit flops and the compact layouts designed into the most efficient logic libraries.

8 Summary TSMC s new 28HPC High K Metal Gate process offers improvements in process rules and variability to enable smaller designs, at higher performances, using less power. Leading synthesis and place and route tools can best take advantage of these process improvements to meet demanding design specifications if they have the right set of logic libraries that take full advantage of these new process capabilities. The Synopsys DesignWare TSMC 28HPC logic libraries and leading EDA tools are designed to enable SoC designers to push the limits of performance, area and power and fully utilize the capabilities of the TSMC 28HPC process.

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