EE 110 Practice Problems for Final Exam: Solutions


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1 EE 1 Practice Problems for Final Exam: Solutions 1. Finite State Machines: Sequence Recognizer You want to build a finite state machine that will recognize the sequence x = and output the sequence z = as this sequence occurs. In other words, output z = 0 when first receiving x = 0. Then output z = 0 if the next bit of x = 1; output z = 0 again if the following bit of x = 1. Finally, if the last (fourth) bit of x = 0, output z = 1. More simply, output z = 0 until the sequence x = is received, at which time output z = 1. 1(a). First, draw and label the transitions in the state bubble diagram below. The states are already labeled (but state bit values have not been assigned). Allow overlap of sequences. Build as a Moore machine. Include the input bits of x and output bits of z. START z=0 GOT0 0 GOT 0 GOT 1 GOT1 0 Note: This sequence recognizer allows for overlap of sequences, and thus outputs z = 1 whenever the sequence x = is recognized with overlap of sequences. If we do not allow for overlap, then the transitions from state GOT will go to state START for both x = 0 and x = 1. Without overlap, whenever the sequence x = is input, the output will be z =. 1(b). Write the state table from the state bubble diagram. Fill in the table given below. Use the following state assignments: START=0, GOT0=1, GOT=0, GOT1=1 and GOT=1. All unused states should go to the START state and output z = 0. Assume you will build the circuit with JK flipflops. (next page) 1
2 EE 1 Practice Problems for Final Exam: Solutions, Fall 28 2 Present State Input Output Next State FlipFlop Inputs z Q 2 Q 1 Q 0 J 2 K 2 J 1 K 1 J 0 K X 0 X 1 X X 0 X 0 X X 0 X X X 1 X X X X 1 1 X X X 0 1 X X X 1 X X X 1 X X 1 0 X 1 X X 1 1 X 0 X X 1 0 X X X 1 0 X X X 1 X 1 0 X X 1 X 1 0 X X 1 X 1 X X 1 X 1 X 1 1(c). Find the minimized logic equations for output z and flipflop inputs J 2, K 2, J 1, K 1 and J 0, K 0 ; use Kmaps if needed. Output z: Output z can be determined directly from the truth table, as z = 1 only when Q 2 = 1, = 0 and Q 0 = 0. Therefore, z = Q 0. You may check with a Kmap if you prefer. z = Q 0 Kmap for J 2 :
3 EE 1 Practice Problems for Final Exam: Solutions, Fall 28 3 From the Kmap above, we obtain the following expression for J 2 : J 2 = K 2 : Note that K 2 is either X or 1 for every entry of the truth table. Therefore, we may set K 2 = 1. K 2 = 1 Kmap for J 1 : From the Kmap above with two groupings, we obtain the following expression for J 1 : J 1 = Q 2 + Q 2 This expression may be further simplified by recognizing that Q 2 Q 0 + Q 2 Q 0 = Q 2 Q 0 ; J 1 = x(q 2 ) Kmap for K 1 : From the Kmap above with three groupings, we obtain the following expression for K 1 : K 1 = Q 0 + Q 2 + x
4 EE 1 Practice Problems for Final Exam: Solutions, Fall 28 4 Kmap for J 0 : 1 0 X X 1 1 X X 0 0 X X 1 0 X X From the Kmap above with two groupings, we obtain the following expression for J 0 : J 0 = x + Kmap for K 0 : X X 1 0 X X 1 1 X X 1 1 X X 1 1 From the Kmap above with three groupings, we obtain the following expression for K 0 : K 0 = + Q 2 + x 1(d). outputs. Draw the corresponding circuit diagram with JK flipflops. Label all inputs and (next page) Note: The black dots in the figure indicate a connection between wires. If there is no black dot, there is no connection between wires that cross.
5 EE 1 Practice Problems for Final Exam: Solutions, Fall 28 5 x NOT X +5V CLK J 2 K 2 Q 2 Q 2 J 1 K 1 J 0 Q 0 K 0 Q 0 z 2. State Bubble Diagram of Mealy Machine Redraw the state bubble diagram using a Mealy machine design. Be sure to label the transitions and bubbles. You may name your states whatever you like. Again allow overlap of sequences. How many states and flipflops do you need for the Mealy design? x/z=0/0 START BIT1 1/0 0/0 x/z=1/0 0/1, 1/0 BIT3 0/0 1/0 BIT2 Only four states are required for the Mealy machine design. Two state bits are thus needed to determine all the states. This means that only two flipflops are required to implement the Mealy machine design of the sequence recognizer. 3. Analysis of FSM Circuit Design Below is a simplified block diagram of a heart pacemaker. The output p from the pacemaker pulses high if the heart does not contract within a certain time. The input s indicates whether the heart has contracted (s = 1) or not (s = 0). The input t comes from a timer,
6 EE 1 Practice Problems for Final Exam: Solutions, Fall 28 6 which counts for the expected time between contractions (approximately 1 second). When t = 1, the timer has counted up to 1 second, and the heart should have contracted. If the heart has not contracted within that time, the pacemaker sends a pulse p = 1. (There is also a timer reset control coming from the pacemaker, which we ignore for this problem.) The inputs to the pacemaker circuit are s (from the heart) and t (from a timer  not shown). The output of the pacemaker circuit is p, which goes to the heart. Arrows indicate the inputs and output. Heart p s NOT s Pacemaker D 1 D 0 Q 0 t CLK Q 0 Note: The black dots in the figure indicate a connection between wires. If there is no black dot, there is no connection between wires that cross. 3(a). Is this a Mealy or a Moore machine? Why? This is a Mealy machine. The output p depends on the input s, as well as the sequential logic output states and Q 0 and the input t from a timer clocked synchronously with FF1 and FF0. This means that the output p can change at times other than on a rising clock edge, if the input s changes. The input s is not clocked, and is not constrained to change only on a rising clock edge. 3(b). Write the equations for output p and the flipflop inputs D 1 and D 0 from the block diagram. Output p: p = Q 0 s t D input for Flipflop 1, D 1 : D 1 = p = Q 0 s t
7 EE 1 Practice Problems for Final Exam: Solutions, Fall 28 7 D input for Flipflop 0, D 0 : D 0 = Q 0 + s 3(c). Fill in the state table below, using the equations obtained in part 3(b). Present State Inputs Output Next State Q 0 s t p Q 1 Q
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