data D Q sc_in D Q data CLK sc_en CLK clk clk scan Flip Flop Nonscan Flip Flop - 1 -

Transcription

1 data data D Q sc_in D Q clk CLK sc_en CLK clk Nonscan Flip Flop scan Flip Flop - 1 -

2 순차회로부 주사플립플롭 - 2 -

3 Partition A Design level Scan out pin added Design level Scan in pin added Unobservable Output Uncntrollable Input - 3 -

4 A B A B C D E F G H W1 W2 O C D T E F G H W2 W1 O a) Test point 가적용되지않은회로 b) controllability 를높이기위한 Test point 가적용된회로 T T A B TO A B TO C D E F W1 W2 O C D E F W1 O G H G H W2 c) observability 를높이기위한 Test point 가적용된회로 d) Test point 가적용된회로 - 4 -

5 test point (for observability) Combinational A Combinational B D si s e CLK Q so Next scan cell test point (for controllability) Combinational A Combinational B D si s e CLK Q so Next scan cell - 5 -

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21 Add Black Box Add Black Box Add Cell Library Add Cell Models Add Clock Groups Add Clocks Add Display Instances Add Display Loop Add Display Path Add Display Scanpath Add Mapping Definition Add Nofaults Add Nonscan Instances Add Nonscan Models Add Notest Points Add Output Masks Add Pin Constraints Add Pin Equivalences Defines black boxes and sets the constrained value on output or bidirectional black box pins. Specifies for DFTAdvisor to place buffer cells between the primary input of the specified test pin and the gates that it drives. Specifies the EDIF library in which to place all or specified library models which are explicitly added by DFTAdvisor scan and test logic insertion process. Specifies the name of a DFT library cell that DFTAdvisor can use with user-defined test points, system-generated test points, and system-generated test logic. Specifies the grouping of scan cells controlled by different clocks onto one chain. Specifies the names and inactive states of the primary input pins that control the clocks in the design. Adds the specified instances to the netlist for display. Displays all the gates in a specified feedback path. Displays all the gates associated with the specified path. Displays all the associated gates between two positions in a scan chain. Overrides the nonscan to scan model mapping defined by DFTAdvisor. Places nofault settings either on a pin or on all pins of a specified instance or module. Specifies for DFTAdvisor to ignore the specified instances, all instances controlled by the specified control pin, or all instances within the specified module, when identifying and inserting the required scan elements and test logic. Instructs DFTAdvisor to ignore all instances of the specified sequential DFT library model when identifying and inserting the required scan elements and test logic into the design. Adds circuit points to list for exclusion from testability insertion. Instructs DFTAdvisor to mask, and optionally maintain a constant logic level on, the specified primary output pins during the scan identification analysis. Specifies that DFTAdvisor hold the input pin at a constant state during the rules checking and loop cutting processes. Specifies to hold the specified primary input pins at a state either equal to or inverted in relationship to the state of another primary input pin during rules checking

22 Add Primary Inputs Adds a primary input to the net. Add Primary Outputs Adds a primary output to the net. Adds an off-state value to specified RAM read control Add Read Controls lines. Specifies a name for a preexisting scan chain within the Add Scan Chains design. Add Scan Groups Adds one scan chain group to the system. Specifies that DFTAdvisor add the specified instance, all instances controlled by the specified control pin, or all Add Scan Instances instances within the specified module, to the scannable instance list. Specifies that DFTAdvisor is to flag every instance of the Add Scan Models named DFT library model for inclusion into the identified scan list. Declares the name of a scan chain at the top-level module and assigns the corresponding scan input pin, scan output Add Scan Pins pin, and optionally, the scan clock pin that you want to associate with that chain. Specifies the enable value of a clock enable that internally gates Add Seq_transparent Constraints the clock input of a non-scan cell for sequential transparent scan identification. Specifies the name of a preexisting scan chain that exists Add Sub Chains entirely within a module or instance within a hierarchical design. Specifies explicitly where DFTAdvisor is to place a Add Test Points user-defined test point to improve the design's testability either through better controllability or observability. Specifies for DFTAdvisor to hold the named floating Add Tied Signals objects (nets or pins) at the given state value. Specifies the off-state value of the write control lines for Add Write Controls RAMs. Identifies and optionally defines the primary inputs of Analyze Control Signals control signals. Generates a netlist of the portion of the design involved Analyze Drc Violation with the specified rule violation number. Specifies for DFTAdvisor to calculate and display the Analyze Input Control effects of constraining primary input pins to an unknown value on those pins' control capability. Specifies for DFTAdvisor to calculate and display the Analyze Output Observe effects on the observability of masked primary output pins. Reports general scannability and testability information, Analyze Testability along with calculating the controllability and observability values for gates. Terminates the optional schematic viewing application Close Schematic Viewer (DFTInsight)

23 Delete Black Box Delete Buffer Insertion Delete Cell Models Delete Clock Groups Delete Clocks Delete Display Instances Delete Mapping Definition Delete Nofaults Delete Nonscan Instances Delete Nonscan Models Delete Notest Points Delete Output Masks Delete Pin Constraints Delete Pin Equivalences Delete Primary Inputs Delete Primary Outputs Delete Read Controls Delete Scan Chains Delete Scan Groups Delete Scan Instances Delete Scan Models Delete Scan Pins Delete Seq_transparent Constraints Delete Sub Chains Delete Test Points Undoes the effect of the Add Black Box command. Specifies the type of scan test pins on which you want to remove the fanout limit. Specifies the name of the DFT library cell that DFTAdvisor is to remove from the active list of cells that the user can access when adding test points or that DFTAdvisor can access when inserting test logic. Specifies the name of the group that you want to remove from the clock groups list. Removes primary input pins from the clock list. Removes the specified objects from display in DFTInsight. Returns the nonscan to scan model mapping to the mapping defined by DFTAdvisor. Removes the no-fault settings from either the specified pin or instance pathnames. Removes the specified sequential instances from the non-scan instance list. Removes from the non-scan model list the specified sequential DFT library models. Removes the specified pins from the list of notest points which the tool cannot use for testability insertion. Removes the masking of the specified primary output pins. Removes the pin constraints from the specified primary input pins. Removes the pin equivalence specifications for the designated primary input pins. Removes the specified primary inputs from the current netlist. Removes the specified primary outputs from the current netlist. Removes the read control line off-state definitions from the specified primary input pins. Removes the specified scan chain definitions from the scan chain list. Removes the specified scan chain group definitions from the scan chain group list. Removes the specified, sequential instances from the user-identified scan instance list. Removes the specified sequential models from the scan model list. Removes any previously-assigned scan input, output, and clock names from the specified scan chains. Removes the pin constraints from the specified DFT library model input pins. Removes the definition of a preexisting scan sub-chain. Remove the test point definitions at the specified locations

24 Delete Tied Signals Delete Write Controls Dofile Exit Help H istory Insert Test Logic Load Core Access Load Core Description Mark Open Schematic Viewer Read Procfile Redo Display Report Black Box Report Buffer Insertion Report Cell Models Report Clock Groups Report Clocks Report Control Signals Report Dft Check Report Display Instances Report Drc Rules Report Environment Report Feedback Paths Report Flatten Rules Report Gates Report Loops Report Mapping Definition Report Nofaults Removes the assigned (tied) value from the specified floating nets or pins. Removes the RAM write control line off-state definitions from the specified primary input pins. Executes the commands contained within the specified file. Terminates the current DFTAdvisor session. Displays the usage syntax and system mode for the specified command. Displays a list of previously-executed commands. Inserts the test structures that you define into the netlist to increase the design's testability. Loads the specified core access file. Loads the specified core description file. Highlights the objects that you specify in the Schematic View window. Invokes the optional schematic viewing application, DFTInsight. Reads the specified enhanced procedure file. Nullifies the schematic view effects of an Undo command. Displays information on defined blackboxes. Displays a list of all the different scan test pins and the corresponding fanout limit. Displays a list of either all cell models or the DFT library models associated with the specified cell type. Displays a list of all clock group definitions. Displays a list of all clock definitions. Displays the rules checking results for the specified control signals. Generates the scannability check results for non-scan instances. Displays a textual report of the netlist information for either the gates or instances that you specify or for all the gates in the current schematic view display. Displays either a summary of all the Design Rule Check (DRC) violations or the data for a specific violation. Displays the current values of all the "set" commands and the default names of the scan type pins. Displays a textual report of the currently identified feedback paths. Displays either a summary of all the flattening rule violations or the data for a specific violation. Displays the netlist information for the specified gates. Displays a list of all the current loops. Reports the nonscan to scan model mapping defined in the design. Displays the no-fault settings for the specified pin or instance pathnames

25 Report Nonscan Instances Report Nonscan Models Report Notest Points Report Output Masks Report Pin Constraints Report Pin Equivalences Report Primary Inputs Report Primary Outputs Report Procedure Report Read Controls Report Scan Cells Report Scan Chains Report Scan Groups Report Scan Identification Report Scan Instances Report Scan Models Report Scan Pins Report Seq_transparent Constraints Report Statistics Report Sub Chains Report Test Logic Report Test Points Report Testability Analysis Report Tied Signals Report Timeplate Report Write Controls Reset State Ripup Scan Chains Displays the currently defined sequential non-scan instances. Displays the sequential non-scan model list. Displays all the circuit points for which you do not want DFTAdvisor to insert controllability and observability. Displays a list of the currently masked primary output pins. Displays the pin constraints of the primary inputs. Displays the pin equivalences of the primary inputs. Displays the specified primary inputs. Displays the specified primary outputs. Displays the specified procedure. Displays all of the currently defined read control lines. Displays a report or writes a file on the scan cells that reside in the specified scan chains. Displays a report on all the current scan chains. Displays a report on all the current scan chain groups. Displays a list of the scan instances which DFTAdvisor has identified or you have defined as scan cells. Displays the currently defined sequential scan instances. Displays the sequential scan models currently in the scan model list. Displays all previously assigned scan input, output, and clock names. Displays the seq_transparent constraints. Displays a detailed report of the design's statistics. Generates and displays a report on the scan sub-chains. Displays the test logic that DFTAdvisor added during the scan insertion process. Displays the test point specifications you created with Add Test Points command and any test points that you enabled DFTAdvisor to automatically identify. Displays the results of the Analyze Testability command. Displays a list of the tied floating signals and pins. Displays the specified timeplate. Displays the currently defined write control lines and their off-states. Removes all instances from both the scan identification and test point identification lists that DFTAdvisor identified during a run. Removes the specified scan chains from the design

26 Run Save History Save Schematic Select Object Set Capture Clock Set Command Editing Set Contention Check Set Control Threshold Set Dofile Abort Set Drc Handling Set Fault Sampling Set File Compression Set Flatten Handling Set Gate Level Set Gate Report Set Gzip Options Set Identification Model Set Instancename Visibility Set Internal Fault Set Io Insertion Set Latch Handling Set Lockup Latch Set Logfile Handling Set Loop Duplication Set Multiple Scan_enables Set Net Resolution Set Nonscan Handling Runs the scan or test point identification process. Saves the command line history file to the specified file. Saves the schematic currently displayed by DFTInsight. Selects the specified objects in the DFTInsight schematic view. Specifies the capture clock name for random pattern simulation. Sets the command line editing mode. Specifies whether DFTAdvisor checks the gate types that you determine for contention. Specifies the controllability value for simulation-based pseudorandom pattern test point identification. Lets you specify that the tool complete processing of all commands in a dofile regardless of an error detection. Specifies how DFTAdvisor globally handles design rule violations. Specifies the fault sampling percentage for scan identification. Controls whether the tools read and write files with.z or.gz extensions as compressed files (the default). Specifies how DFTAdvisor globally handles flattening violations. Specifies the hierarchical level of gate reporting and displaying. Specifies the additional display information for the Report Gates command. Specifies GNU gzip options to use with the GNU gzip command. Specifies the simulation model that DFTAdvisor uses to imitate the scan operation during the scan identification process. Specifies whether DFTInsight displays instance names immediately above each instance in the Schematic View area. Specifies whether the tool allows faults within or on the boundary of library models. Specifies whether to insert I/O buffers. Specifies whether the tool considers non-transparent latches for scan insertion while test logic is turned on. Specifies for DFTAdvisor to insert latches between different clock domains to synchronize the clocks within a scan chain. Specifies for DFTAdvisor to direct the transcript information to a file. Specifies whether to include duplicate gates in feedback paths which are generated during the circuit flattening process. Specifies to create multiple scan_enables. Specifies the behavior of multi-driver nets. Specifies whether to check the nonscan instances for scannability

27 Set Observe Threshold Set Scan Type Set Schematic Display Set Screen Display Set Sensitization Checking Set Shadow Check Set Stability Check Set System Mode Set Test Logic Set Trace Report Set Transient Detection Set Zoom Factor Setup Output Masks Setup Pin Constraints Setup Scan Identification Setup Scan Insertion Setup Scan Pins Setup Test_point Identification Setup Test_point Insertion Setup Tied Signals System Undo Display Unmark Unselect Object Specifies the observability value for simulation-based test point identification. Specifies the scan style design. Changes the default schematic display environment settings for DFTInsight. Specifies whether DFTAdvisor writes the transcript to the session window. Specifies whether DRC checking attempts to verify a suspected C3 rules violation. Specifies whether DFTAdvisor will identify sequential elements as "shadow" elements when tracing existing scan chains. Specifies how the tool checks the effect of applying the shift procedure on non-scan cells. Specifies the next system mode for the tool to enter. Specifies which types of control lines DFTAdvisor makes controllable during the DFT rules checking. Specifies whether the tool displays gates in the scan chain trace. Specifies whether the tool detects all zero width events on the clock lines of state elements. Specifies the scale factor that the zoom icons use in the DFTInsight Schematic View window. Sets the default mask for all output and bidirectional pins. Sets the default pin constraint value for all input and bidirectional pins. Specifies the scan identification methodology and amount of scan that DFTAdvisor is to consider during the identification run. Sets up the parameters for the Insert Test Logic command. Changes the scan-in or scan-out pin naming parameters to index or bus format. Specifies the number of control and observe test points that DFTAdvisor flags during the identification run. Specifies how DFTAdvisor configures the inputs for the control test points and the outputs for the observe test points. Changes the default value for floating pins and floating nets that do not have assigned values. Passes the specified command to the operating system for execution. Restores the previous schematic view. Removes the highlighting from the specified objects in the Schematic View window of objects. Removes the specified objects from the selection list in the DFTInsight schematic view

28 View View Area Write Atpg Setup Write Loops Write Netlist Write Primary Inputs Write Primary Outputs Write Procfile Write Scan Identification Write Subchain Setup Zoom In Zoom Out Displays the specified object in the DFTInsight Schematic View window. Displays the specified area in the DFTInsight Schematic View window. Writes the test procedure and the dofile for inserted scan chains to the specified files. Writes a list of all loops to the specified file. Writes the new netlist to the specified file. Writes primary inputs to the specified file. Writes primary outputs to the specified file. Writes existing procedure and timing data to the named enhanced procedure file. Writes a list of the scan instances which DFTAdvisor has identified or you have defined as scan cells. Writes the appropriate Add Sub Chains commands to a file so that DFTAdvisor can understand the preexisting scan sub-chains at the top-level of this module. Enlarges the objects in the DFTInsight Schematic View window by reducing the displayed area. Reduces the objects in the DFTInsight Schematic View window by increasing the displayed area