Timing Design in Digital Systems
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1 ECE 520 Cass Noes Timing Design in Digia Sysems Dr. Pau D. Franzon Ouine 1. Timing design in Synchronous (cocked) Logic Min/Max iming wih fip-fops Lach-based design 3. Timing Issues in CMOS circuis 4. Timing verificaion and SDF References 1. Smih and Franzon, Chapers 11 and Smih, Secions 2.4, 13.6, 13.7, H.B. Bakogu, Circuis, Inerconnecions and Packing for VLSI, Addison- Wesey, Ch Dr. Pau D. Franzon, 1 ECE 520 Cass Noes Genera Approach o Timing Design In genera, a signas sar and end in regisers every cock period D-Fip-fops Combinaiona Logic In genera, here is ony one cock (in any one sub-bock of he chip) and each fip-fop is cocked every cyce If a chip nee muipe cocks, hey shoud share a common roo cock (e.g. divide a maser cock) and be fed o differen sub-designs wihin he chip 2000 Dr. Pau D. Franzon, 2
2 ECE 520 Cass Noes Criica Pah Thus, he cock speed is deermined by he sowes feasibe pah beween regisers in he design Ofen referred o as he criica pah 2000 Dr. Pau D. Franzon, 3 ECE 520 Cass Noes Cock Disribuion The goa of cock ree is for he cock o arrive a every eaf node a he same ime: Usuay designed afer synhesis: Mached buffers; mached capaciance oa Some cock skew (difference in arriva imes) is unavoidabe Cock skew specificaion is an imporan parameer Cock ree carefuy designed o mee a skew requiremen 2000 Dr. Pau D. Franzon, 4
3 ECE 520 Cass Noes Ck daa ou seup daa Ck hod cock-q Regiser D ck Q Q Combinaiona Logic ogic Fip-Fop based design ou Regiser D1 Q1 D2 Q2 Edge riggered D-fip-fop Q becomes D afer cock edge Se-up ime: Daa can no change no aer han his poin before he cock edge. Hod ime: Daa can no change during his ime afer he cock edge. _cock-q Deay on oupu (Q) changing from posiive cock edge ck ck +/-skew 2000 Dr. Pau D. Franzon, 5 ECE 520 Cass Noes Prevening Se-Up Vioaions Se-up vioaion: Logic is oo sow for he correc ogic vaue o arrive a he inpus o he regiser on he righ before one se-up ime before he cock edge Consrain o preven his: cock > cock Q max + ogic max + se up + skew cock cock Q1 D2 The amoun of ime required o urn < ino = is referred o as iming sack 2000 Dr. Pau D. Franzon, 6
4 ECE 520 Cass Noes Prevening hod vioaions Hod vioaions occur when race-hrough is possibe Consrain o preven hod vioaions: hod + skew < cock Q min + ogic min cock cock Q1 D2 someimes have o inser addiiona ogic o preven hod vioaions 2000 Dr. Pau D. Franzon, 7 ECE 520 Cass Noes D-Lach: Ck daa D Q Enabe Q Lach Based Design ou D-ach Q foows D whie cock is high Vaue on D when cock goes ow is sored on Q Ck daa seup hod Se-up and hod imes: D can no change cose o he faing ( aching ) cock edge. ou cock-q Regiser Regiser _cock-q Deay from cock going high o Q changing Combinaiona Logic D1 Q1 D2 Q2 ogic ck ck +/-skew 2000 Dr. Pau D. Franzon, 8
5 ECE 520 Cass Noes To preven se-up vioaions: Lach iming consrains + cock + cock high max > cock Q max + ogic max + se up cock skew cock Q1 D2 Noes: The percenage of ime he cock is high is referred o as he duy-cyce If par of he foowing cock-high ime is used o aow his ogic o be sower, hen he ogic-bock conneced o Q2 mus be proporionay faser Using he cock-high ime ike his is caed cyce-seaing 2000 Dr. Pau D. Franzon, 9 ECE 520 Cass Noes To preven hod vioaions: cock Lach iming consrains cock high max + hod + skew < cock Q min + ogic min cock Q1 D2 Noe: Hod vioaions are harder o preven in ach-based designs 2000 Dr. Pau D. Franzon, 10
6 ECE 520 Cass Noes Laches Cyce Seaing 2000 Dr. Pau D. Franzon, 11 ECE 520 Cass Noes D-fip-fop Exampe: D-fip-fop 2000 Dr. Pau D. Franzon, 12
7 ECE 520 Cass Noes CMOS Drive Srengh Revision: CMOS ransisors operaing in he inear region: I I = β (( V V gs where β = ( µε/ / R on V ) V ox V 2 )( W / L) wherew is he ransisor widh, and L is he channe engh i.e. / 2 To a firs approximaion, Thus, deay in CMOS circuis depen argey on W/L of he drive ransisor and he capaciance of he oad i is driving. Tha capaciance consiss of: Inpu gaes of ces being driven, and Capaciance of wiring 2000 Dr. Pau D. Franzon, 13 ECE 520 Cass Noes Timing in Design The ASIC vendor wi deveop deay modes for each ce Bes/wors modes deveoped as ransisor β changes wih process, emperaure, ec. Modes aso deveoped for deay as a funcion of capaciive oad (fan-ou) Timing modes are sored as par of he ce ibrary Timing Verificaion is done wih a combinaion of he foowing: Logic simuaion using acua deays from he iming ibrary Saic iming anaysis: A saic iming anayzer races hrough he acua ogic and cacuaes sowes and fases deay for each rue pah hrough he ogic u Someimes, however, i can no e he difference beween rue and fase (no possibe) pahs Ð Ofen he designer has o idenify fase pahs I oupus a iming repor for criica (Sowes) and oher pahs 2000 Dr. Pau D. Franzon, 14
8 ECE 520 Cass Noes Timing in ASIC Design Fow Sandard Deay Forma (SDF) fies: Toos communicae iming informaion using SDF fies Specifies iming informaion as cacuaed from: u ASIC vendor iming modes (Synopsys oupus as SDF fie based on his informaion) u Wiring deay cacuaions afer pace and roue The SDF fie is hen used by he ogic simuaor or saic iming verifier o verify ha he design wi no have any seup or hod vioaions 2000 Dr. Pau D. Franzon, 15 ECE 520 Cass Noes Good and Bad Timing Design Pracices Good Genera Pracices: In each modue, use ony one cock and one edge. Pay aenion o he amoun of ogic specified in ong ogic pahs during design Ony use he gobay disribued cock(s) Bad Design Pracices: Feeding back combinaiona ogic on isef u Specifying a ach! Using muipe cocks, muipe edges Gaing he cock or generaing oca cocks 2000 Dr. Pau D. Franzon, 16
9 ECE 520 Cass Noes Summary Timing issues drive he deais of any design operaing above 10 MHz maximum ogic deph beween fip-fops deermines cock speed he sowes pah is ermed he criica pah In any one design, ry o use ony one cock and one ype of memory eemen Generay edge-riggered fip-fops work bes Any design wi have a non-zero cock skew due o impossibiiy of exacy baancing deays in a branches of he cock ree Loca cock skews are usuay smaer han goba cock skews (hough his informaion migh no be avaiabe o he designer) Timing anayzers are used o deermine if se-up and hod vioaions occur e.g. The Cadence Pear Saic Timing Anayzer used in his cass Veriog-XL can be used o perform dynamic iming anaysis 2000 Dr. Pau D. Franzon, 17
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