Memory. Memory Decoders
|
|
- Anne Bradley
- 7 years ago
- Views:
Transcription
1 Memory RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM Memory Decoders M bits M bits N Words S 0 S 1 S 2 S N-2 S N_1 Word 0 Word 1 Word 2 Word N-2 Word N-1 Storage Cell A 0 A 1 A K-1 Decoder S 0 Word 0 Word 1 Word 2 Word N-2 Word N-1 Storage Cell Input-Output (M bits) Input-Output (M bits) N words => N select signals Too many select signals Decoder reduces # of select signals K = log 2 N 1
2 Array-Structured Memory Problem: ASPECT RATIO or HEIGHT >> WIDTH 2 L-K Bit Line Storage Cell A K A K+1 A L-1 Row Decoder Word Line Sense Amplifiers / Drivers M.2 K Amplify swing to rail-to-rail amplitude A 0 A K-1 Column Decoder Selects appropriate word Input-Output (M bits) Array Decoding 2
3 Hierarchical Memory Arrays Row Address Column Address Block Address Control Circuitry Block Selector Global Amplifier/Driver Global Data Bus I/O Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings Memory Timing Definitions Read Cycle READ Read Access Read Access Write Cycle WRITE Data Valid Write Access DATA Data Written 3
4 Memory Timing Approaches MSB LSB Address Bus Row Address Column Address RAS CAS Address Bus Address Address transition initiates memory operation RAS-CAS timing DRAM Timing Multiplexed Adressing SRAM Timing Self-timed Example: HM6264 8kx8 SRAM 4
5 HM6264 Interface Function Table 5
6 Timing Read Cycle 1 6
7 Read Cycle 1 85ns min 85ns max 85ns max 10ns min 85ns max 10ns min 45ns max 5ns min 30ns min 30ns min 30ns min 10ns min Read Cycle 2 7
8 Read Cycle 2 85ns max 10ns min 10ns min Write Timing 8
9 Write Cycle Write Cycle 85ns min 75ns min 0ns min 0ns min 75ns min 55ns min 0ns min, 30ns max 40ns min 0ns min 9
10 What Does All This Mean For a read: If you assert CS1, CS2, address, and OE all at the same time, it will be max 85ns before valid data are available at chip outputs For a write: You can assert CS1, CS2, address, data, and WE all at the same time if you want to You need to wait 55ns from WE edge, or 75ns from CS1/CS2 edge for write to have happened R/W Memories In General STATIC (SRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential DYNAMIC (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended 10
11 SRAM Circuits SRAM Cell, Transistors 11
12 SRAM, Resistive Pullups Array-Structured Memory Problem: ASPECT RATIO or HEIGHT >> WIDTH 2 L-K Bit Line Storage Cell A K A K+1 A L-1 Row Decoder Word Line Sense Amplifiers / Drivers M.2 K Amplify swing to rail-to-rail amplitude A 0 A K-1 Column Decoder Selects appropriate word Input-Output (M bits) 12
13 Memory Column Each column has all the support circuits Reading the Bit Single-ended read using an inverter Dynamic pre-charge on the bit lines P-types pull bit lines high 13
14 Reading the Bit 2 Single-ended read using an inverter Dynamic pre-charge on the bit lines Note the N-types used as pull-ups Reading the Bit 3 Differential read using sense amp Static N-type pullup on the bit lines 14
15 Read Waveforms Sense Amp 15
16 Sense Amp Transistors Column Organization 16
17 Write Circuits Write Circuit Simulation 0 17
18 Analog Sim, Circuit WL V DD M2 M4 M5 Q Q M6 M1 M3 BL BL Analog Analysis, Write WL V DD M4 M5 Q = 0 Q = 1 M6 M1 BL = 1 V DD BL = 0 k nm6 V, ( DD V Tn ) V 2 DD V DD k 2 8 pm4 V, ( DD V Tp ) V 2 DD V = DD 2 8 (W/L) n,m (W/L) p,m4 k nm5, V V 2 DD DD V 2 Tn V 2 DD V k n, M1 ( V DD V Tn ) DD 2 8 = (W/L) n,m5 10 (W/L) n,m1 18
19 Analog Analysis, Read WL V DD BL M4 BL M5 Q = 0 Q = 1 M6 V DD M1 V DD V DD C bit C bit k nm , V V DD DD V 2 2 Tn V DD V 2 = k 2 nm1, ( V DD V Tn ) DD 2 8 (W/L) n,m5 10 (W/L) n,m1 (supercedes read constraint) 6T SRAM Layout 19
20 Another 6T SRAM Layout SRAM bit from makemem (v1) 20
21 SRAM bit from makemem (v2) Array-Structured Memory Problem: ASPECT RATIO or HEIGHT >> WIDTH 2 L-K Bit Line Storage Cell A K A K+1 A L-1 Row Decoder Word Line Sense Amplifiers / Drivers M.2 K Amplify swing to rail-to-rail amplitude A 0 A K-1 Column Decoder Selects appropriate word Input-Output (M bits) 21
22 Row Decoders Select exactly one of the memory rows Simple versions are just gates Row Decoder Gates Standard gates Or, pseudo-nmos gates with static pull up Easier to make large fan-in NOR 22
23 Pre-decode Row Decoder Multiple levels of decoding can be more efficient layout Pre-decode Row Decoder Other circuit tricks for building row decoders 23
24 Array-Structured Memory Problem: ASPECT RATIO or HEIGHT >> WIDTH 2 L-K Bit Line Storage Cell A K A K+1 A L-1 Row Decoder Word Line Sense Amplifiers / Drivers M.2 K Amplify swing to rail-to-rail amplitude A 0 A K-1 Column Decoder Selects appropriate word Input-Output (M bits) Array-Structured Memory 24
25 Sharing Sense Amps Sense Amp Mux 25
26 Sense Amp Mux Decoded Column Decode 26
27 Improving Speed, Power Multi-Port Memory Very common to require multiple read ports Think about a register file, for example 27
28 Multi-Port Register Re1 Re0 Slightly larger cell, but with single-ended read makes a great register file Register File Slightly larger cell, but with single-ended read makes a great register file 28
29 Dynamic RAM Get rid of the pull-ups! Store info on capacitors Means that stored information leaks away Dynamic RAM Once you agree to use a capacitor for charge storage there are other ways to build this 29
30 3T DRAM Circuit BL1 BL2 WWL RWL WWL RWL M1 X M2 M3 X BL1 V DD V DD -V T C S BL2 V DD -V T ΔV No constraints on device ratios Reads are non-destructive Value stored at node X when writing a 1 = V WWL -V Tn 3T DRAM Layout BL2 BL1 GND RWL M3 M2 WWL M1 30
31 1 T DRAM Circuit 2-T (1-T) DRAM layout Note the increased gate size of the storage transistor Increases the capacitance 31
32 1T DRAM Observations 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a 1 into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than V DD. WL 1T DRAM Read/Write BL WL Write "1" Read "1" M1 C S X GND V DD V T C BL BL V DD /2 V DD sensing V DD/2 Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance C S ΔV = V BL V PRE = ( V BIT V PRE ) C S + C BL Voltage swing is small; typically around 250 mv. 32
33 1T DRAM Cell Folded bit line Array of DRAM Cells Folded Bit Line 33
34 Reading a 1T DRAM Cell Charge Sharing DRAM Sense Amp 34
35 Photo of 1T DRAM Advanced DRAM Cells Try to get more capacitance per unit area Trench Capacitor 35
36 Examples of Advanced DRAMs Word line Insulating Layer Cell plate Capacitor dielectric layer Cell Plate Si Capacitor Insulator Storage Node Poly 2nd Field Oxide Refilling Poly Si Substrate Transfer gate Isolation Storage electrode Trench Cell Stacked-capacitor Cell Memory Timing Approaches MSB LSB Address Bus Row Address Column Address RAS CAS Address Bus Address Address transition initiates memory operation RAS-CAS timing DRAM Timing Multiplexed Adressing SRAM Timing Self-timed 36
37 DRAM Interface Extended Data Out Page Mode 37
38 Comments on Timing Architectural Issues 38
39 SDRAM - Use CAS for Bursts DDR SDRAM Double Data Rate 39
40 DRAM Timing RAMBUS DRAM (RDRAM) 40
41 RDRAM Bandwidth Maximum Bandwidth 41
42 Normal Bus for DRAM DIMMs RDRAM Bus 42
43 Deep Pipelining - High Latency RDRAM Addressing 43
44 Row Activate Command RDRAM System Arch 44
45 RDRAM Internal Arch Regular DRAM 45
46 Single Bank DRAM Multi-Bank DRAM 46
47 Peak Bandwidth ROM 47
48 ROM V DD Pull-up devices WL[0] WL[1] GND WL[2] WL[3] GND BL[0] BL[1] BL[2] BL[3] ROM 48
49 ROM ROM Layout Metal1 on top of diffusion WL[0] WL[1] Basic cell 10 λ x 7 λ GND (diffusion) Polysilicon Metal1 WL[2] 2 λ WL[3] Only 1 layer (contact mask) is used to program memory array Programming of the memory can be delayed to one of last process steps 49
50 ROM Layout Precharged ROM φpre V DD Precharge devices WL[0] WL[1] GND WL[2] WL[3] GND BL[0] BL[1] BL[2] BL[3] PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design. 50
51 Precharged ROM Other Memory Cells 51
52 EPROM Non-Volatile ROM Erasable Programmable ROM EEPROM Electrically Erasable Programmable ROM Flash EEPROM Electrically Erasable Programmable ROM that is erased in large chunks All these devices rely on trapping charge on a floating gate Source Floating gate EPROM Gate Drain D t ox G t ox n + Substrate p n + S (a) Device cross-section (b) Schematic symbol 52
53 20 V Programming EPROM 0 V 5 V 20 V 10 V 5 V 5 V 0 V 2.5 V 5 V S D S D S D Avalanche injection. Removing programming voltage leaves charge trapped. Higher Vth (around 7v) means that 5v Vgs no longer turns on the transistor SiO2 is an excellent insulator Trapped charge can stay for years Programming results in higher V T. Erasing an EPROM Erase by shining UV light through window in the package UV radiation makes oxide slightly conductive Erasure is slow - from seconds to minutes depending on UV intensity Also the erase/program cycles are limited (around 1000), mainly as a result of the UV erasing But, EPROMs are simple and dense 53
54 Source Floating gate EEPROM Gate Drain I n nm Substrate p 10 nm (a) Flotox transistor Floating Gate Tunneling Oxide transistor WL n + V DD 10 V V GD 10 V (b) Fowler-Nordheim I-V characteristic BL (c) EEPROM cell during a read operation Thin oxide allows erasing in-system Fowler-Nordheim Tunneling EEPROM Two transistors instead of one The second keeps you from removing too much charge during erasure Bigger and not as dense as EPROM But, more erase/program cycles On the order of 10 5 Eventually you get permanently trapped charge in the SiO2 54
55 Flash EEPROM Control gate Floating gate erasure Thin tunneling oxide n + source programming n + drain p-substrate Essentially the same as EEPROM But, large regions erased at once Means you can monitor the voltages and don t need the extra access transistor Flash EEPROM 55
56 Realistic PROM Devices Content Addressable Mem Asks the question: Are there are any locations that hold this value? Used for tag memories in associative caches Or translation lookaside buffers Or other pattern matching applications 56
57 Content Addressable Mem Add the Match line Essentially a distributed NOR gate Content Addressable Mem 57
58 Programmable Logic Array Product Terms AND PLANE x 0 x 1 x 2 OR PLANE f 0 f 1 x 0 x 1 x 2 PLA Still useful for random combinational logic Standard cell ASIC tools may be replacing them They can generate dense AND-OR circuits 58
59 Pseudo-Static PLA Circuit GND GND GND GND V DD GND GND GND V DD x 0 x 0 x 1 x 1 x 2 x 2 f 0 f 1 AND-PLANE OR-PLANE φ AND Dynamic PLA GND V DD φ OR V DD φ AND x 0 x 0 x 1 x 1 x 2 x 2 AND-PLANE f 0 f 1 GND OR-PLANE φ OR 59
60 PLA Layout V DD And-Plane Or-Plane φ GND x 0 x 0 x 1 x 1 x 2 x 2 Pull-up devices f 0 f 1 Pull-up devices PLA vs. ROM Programmable Logic Array structured approach to random logic two level logic implementation NOR-NOR (product of sums) NAND-NAND (sum of products) IDENTICAL TO ROM! Main difference ROM: fully populated PLA: one element per minterm Note: Importance of PLA s has drastically reduced 1. slow 2. better software techniques (mutli-level logic synthesis) 60
61 FPGAs Field Programmable Gate Arrays Array of P-type and N-type transistors Sources and drains connected to Power and ground Metal Map gate structures to sea of gates Less expensive only modify metal masks 61
Semiconductor Memories
Semiconductor Memories Semiconductor memories array capable of storing large quantities of digital information are essential to all digital systems Maximum realizable data storage capacity of a single
More information1. Memory technology & Hierarchy
1. Memory technology & Hierarchy RAM types Advances in Computer Architecture Andy D. Pimentel Memory wall Memory wall = divergence between CPU and RAM speed We can increase bandwidth by introducing concurrency
More informationChapter 9 Semiconductor Memories. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 9 Semiconductor Memories Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2 Outline Introduction
More informationRAM & ROM Based Digital Design. ECE 152A Winter 2012
RAM & ROM Based Digital Design ECE 152A Winter 212 Reading Assignment Brown and Vranesic 1 Digital System Design 1.1 Building Block Circuits 1.1.3 Static Random Access Memory (SRAM) 1.1.4 SRAM Blocks in
More informationA N. O N Output/Input-output connection
Memory Types Two basic types: ROM: Read-only memory RAM: Read-Write memory Four commonly used memories: ROM Flash, EEPROM Static RAM (SRAM) Dynamic RAM (DRAM), SDRAM, RAMBUS, DDR RAM Generic pin configuration:
More informationModule 2. Embedded Processors and Memory. Version 2 EE IIT, Kharagpur 1
Module 2 Embedded Processors and Memory Version 2 EE IIT, Kharagpur 1 Lesson 5 Memory-I Version 2 EE IIT, Kharagpur 2 Instructional Objectives After going through this lesson the student would Pre-Requisite
More informationMemory Basics. SRAM/DRAM Basics
Memory Basics RAM: Random Access Memory historically defined as memory array with individual bit access refers to memory with both Read and Write capabilities ROM: Read Only Memory no capabilities for
More informationComputer Architecture
Computer Architecture Random Access Memory Technologies 2015. április 2. Budapest Gábor Horváth associate professor BUTE Dept. Of Networked Systems and Services ghorvath@hit.bme.hu 2 Storing data Possible
More informationCHAPTER 16 MEMORY CIRCUITS
CHPTER 6 MEMORY CIRCUITS Chapter Outline 6. atches and Flip-Flops 6. Semiconductor Memories: Types and rchitectures 6.3 Random-ccess Memory RM Cells 6.4 Sense-mplifier and ddress Decoders 6.5 Read-Only
More informationMemory. The memory types currently in common usage are:
ory ory is the third key component of a microprocessor-based system (besides the CPU and I/O devices). More specifically, the primary storage directly addressed by the CPU is referred to as main memory
More informationHomework # 2. Solutions. 4.1 What are the differences among sequential access, direct access, and random access?
ECE337 / CS341, Fall 2005 Introduction to Computer Architecture and Organization Instructor: Victor Manuel Murray Herrera Date assigned: 09/19/05, 05:00 PM Due back: 09/30/05, 8:00 AM Homework # 2 Solutions
More informationADVANCED PROCESSOR ARCHITECTURES AND MEMORY ORGANISATION Lesson-17: Memory organisation, and types of memory
ADVANCED PROCESSOR ARCHITECTURES AND MEMORY ORGANISATION Lesson-17: Memory organisation, and types of memory 1 1. Memory Organisation 2 Random access model A memory-, a data byte, or a word, or a double
More informationFlash Memories. João Pela (52270), João Santos (55295) December 22, 2008 IST
Flash Memories João Pela (52270), João Santos (55295) IST December 22, 2008 João Pela (52270), João Santos (55295) (IST) Flash Memories December 22, 2008 1 / 41 Layout 1 Introduction 2 How they work 3
More informationChapter 5 :: Memory and Logic Arrays
Chapter 5 :: Memory and Logic Arrays Digital Design and Computer Architecture David Money Harris and Sarah L. Harris Copyright 2007 Elsevier 5- ROM Storage Copyright 2007 Elsevier 5- ROM Logic Data
More informationClass 18: Memories-DRAMs
Topics: 1. Introduction 2. Advantages and Disadvantages of DRAMs 3. Evolution of DRAMs 4. Evolution of DRAMs 5. Basics of DRAMs 6. Basics of DRAMs 7. Write Operation 8. SA-Normal Operation 9. SA-Read Operation
More informationMemory unit. 2 k words. n bits per word
9- k address lines Read n data input lines Memory unit 2 k words n bits per word n data output lines 24 Pearson Education, Inc M Morris Mano & Charles R Kime 9-2 Memory address Binary Decimal Memory contents
More informationWith respect to the way of data access we can classify memories as:
Memory Classification With respect to the way of data access we can classify memories as: - random access memories (RAM), - sequentially accessible memory (SAM), - direct access memory (DAM), - contents
More informationCS250 VLSI Systems Design Lecture 8: Memory
CS250 VLSI Systems esign Lecture 8: Memory John Wawrzynek, Krste Asanovic, with John Lazzaro and Yunsup Lee (TA) UC Berkeley Fall 2010 CMOS Bistable 1 0 Flip State 0 1 Cross-coupled inverters used to hold
More informationRead-only memory Implementing logic with ROM Programmable logic devices Implementing logic with PLDs Static hazards
Points ddressed in this Lecture Lecture 8: ROM Programmable Logic Devices Professor Peter Cheung Department of EEE, Imperial College London Read-only memory Implementing logic with ROM Programmable logic
More informationHandout 17. by Dr Sheikh Sharif Iqbal. Memory Unit and Read Only Memories
Handout 17 by Dr Sheikh Sharif Iqbal Memory Unit and Read Only Memories Objective: - To discuss different types of memories used in 80x86 systems for storing digital information. - To learn the electronic
More informationFeatures. DDR SODIMM Product Datasheet. Rev. 1.0 Oct. 2011
Features 200pin, unbuffered small outline dual in-line memory module (SODIMM) Fast data transfer rates: PC-2100, PC-2700, PC3-3200 Single or Dual rank 256MB(32Megx64), 512MB (64Meg x 64), 1GB(128 Meg x
More informationChapter 7 Memory and Programmable Logic
NCNU_2013_DD_7_1 Chapter 7 Memory and Programmable Logic 71I 7.1 Introduction ti 7.2 Random Access Memory 7.3 Memory Decoding 7.5 Read Only Memory 7.6 Programmable Logic Array 77P 7.7 Programmable Array
More informationAN1837. Non-Volatile Memory Technology Overview By Stephen Ledford Non-Volatile Memory Technology Center Austin, Texas.
Order this document by /D Non-Volatile Memory Technology Overview By Stephen Ledford Non-Volatile Memory Technology Center Austin, Texas Introduction Today s microcontroller applications are more sophisticated
More informationAlgorithms and Methods for Distributed Storage Networks 3. Solid State Disks Christian Schindelhauer
Algorithms and Methods for Distributed Storage Networks 3. Solid State Disks Institut für Informatik Wintersemester 2007/08 Solid State Disks Motivation 2 10 5 1980 1985 1990 1995 2000 2005 2010 PRODUCTION
More information1 / 25. CS 137: File Systems. Persistent Solid-State Storage
1 / 25 CS 137: File Systems Persistent Solid-State Storage Technology Change is Coming Introduction Disks are cheaper than any solid-state memory Likely to be true for many years But SSDs are now cheap
More informationObjectives. Units of Memory Capacity. CMPE328 Microprocessors (Spring 2007-08) Memory and I/O address Decoders. By Dr.
CMPE328 Microprocessors (Spring 27-8) Memory and I/O address ecoders By r. Mehmet Bodur You will be able to: Objectives efine the capacity, organization and types of the semiconductor memory devices Calculate
More informationSequential Circuit Design
Sequential Circuit Design Lan-Da Van ( 倫 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2009 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines
More informationRandom-Access Memory (RAM) The Memory Hierarchy. SRAM vs DRAM Summary. Conventional DRAM Organization. Page 1
Random-ccess Memor (RM) The Memor Hierarch Topics Storage technologies and trends Localit of reference Caching in the hierarch Ke features RM is packaged as a chip. Basic storage unit is a cell (one bit
More informationSOLVING HIGH-SPEED MEMORY INTERFACE CHALLENGES WITH LOW-COST FPGAS
SOLVING HIGH-SPEED MEMORY INTERFACE CHALLENGES WITH LOW-COST FPGAS A Lattice Semiconductor White Paper May 2005 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: (503)
More informationGR2DR4B-EXXX/YYY/LP 1GB & 2GB DDR2 REGISTERED DIMMs (LOW PROFILE)
GENERAL DESCRIPTION The Gigaram is a 128M/256M bit x 72 DDDR2 SDRAM high density JEDEC standard ECC Registered memory module. The Gigaram consists of eighteen CMOS 128MX4 DDR2 for 1GB and thirty-six CMOS
More informationTable 1 SDR to DDR Quick Reference
TECHNICAL NOTE TN-6-05 GENERAL DDR SDRAM FUNCTIONALITY INTRODUCTION The migration from single rate synchronous DRAM (SDR) to double rate synchronous DRAM (DDR) memory is upon us. Although there are many
More informationContents. Overview... 5-1 Memory Compilers Selection Guide... 5-2
Memory Compilers 5 Contents Overview... 5-1 Memory Compilers Selection Guide... 5-2 CROM Gen... 5-3 DROM Gen... 5-9 SPSRM Gen... 5-15 SPSRM Gen... 5-22 SPRM Gen... 5-31 DPSRM Gen... 5-38 DPSRM Gen... 5-47
More informationModeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit
Modeling Sequential Elements with Verilog Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 4-1 Sequential Circuit Outputs are functions of inputs and present states of storage elements
More informationEvaluating Embedded Non-Volatile Memory for 65nm and Beyond
Evaluating Embedded Non-Volatile Memory for 65nm and Beyond Wlodek Kurjanowicz DesignCon 2008 Sidense Corp 2008 Agenda Introduction: Why Embedded NVM? Embedded Memory Landscape Antifuse Memory evolution
More informationModule 7 : I/O PADs Lecture 33 : I/O PADs
Module 7 : I/O PADs Lecture 33 : I/O PADs Objectives In this lecture you will learn the following Introduction Electrostatic Discharge Output Buffer Tri-state Output Circuit Latch-Up Prevention of Latch-Up
More informationStatic-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology
Static-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology Nahid Rahman Department of electronics and communication FET-MITS (Deemed university), Lakshmangarh, India B. P. Singh Department
More informationComputer Architecture
Computer Architecture Slide Sets WS 2013/2014 Prof. Dr. Uwe Brinkschulte M.Sc. Benjamin Betting Part 11 Memory Management Computer Architecture Part 11 page 1 of 44 Prof. Dr. Uwe Brinkschulte, M.Sc. Benjamin
More informationTable 1: Address Table
DDR SDRAM DIMM D32PB12C 512MB D32PB1GJ 1GB For the latest data sheet, please visit the Super Talent Electronics web site: www.supertalentmemory.com Features 184-pin, dual in-line memory module (DIMM) Fast
More informationNTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter
NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter Description: The NTE2053 is a CMOS 8 bit successive approximation Analog to Digital converter in a 20 Lead DIP type package which uses a differential
More informationComputer Systems Structure Main Memory Organization
Computer Systems Structure Main Memory Organization Peripherals Computer Central Processing Unit Main Memory Computer Systems Interconnection Communication lines Input Output Ward 1 Ward 2 Storage/Memory
More information1.1 Silicon on Insulator a brief Introduction
Table of Contents Preface Acknowledgements Chapter 1: Overview 1.1 Silicon on Insulator a brief Introduction 1.2 Circuits and SOI 1.3 Technology and SOI Chapter 2: SOI Materials 2.1 Silicon on Heteroepitaxial
More informationNAND Flash FAQ. Eureka Technology. apn5_87. NAND Flash FAQ
What is NAND Flash? What is the major difference between NAND Flash and other Memory? Structural differences between NAND Flash and NOR Flash What does NAND Flash controller do? How to send command to
More informationMemory Systems. Static Random Access Memory (SRAM) Cell
Memory Systems This chapter begins the discussion of memory systems from the implementation of a single bit. The architecture of memory chips is then constructed using arrays of bit implementations coupled
More informationDDR SDRAM SODIMM. MT9VDDT1672H 128MB 1 MT9VDDT3272H 256MB MT9VDDT6472H 512MB For component data sheets, refer to Micron s Web site: www.micron.
Features DDR SDRAM SODIMM MT9VDDT1672H 128MB 1 MT9VDDT3272H 256MB MT9VDDT6472H 512MB For component data sheets, refer to Micron s Web site: www.micron.com Features 200-pin, small-outline dual in-line memory
More informationECE410 Design Project Spring 2008 Design and Characterization of a CMOS 8-bit Microprocessor Data Path
ECE410 Design Project Spring 2008 Design and Characterization of a CMOS 8-bit Microprocessor Data Path Project Summary This project involves the schematic and layout design of an 8-bit microprocessor data
More informationFLASH TECHNOLOGY DRAM/EPROM. Flash. 1980 1982 1984 1986 1988 1990 1992 1994 1996 Year Source: Intel/ICE, "Memory 1996"
10 FLASH TECHNOLOGY Overview Flash memory technology is a mix of EPROM and EEPROM technologies. The term flash was chosen because a large chunk of memory could be erased at one time. The name, therefore,
More informationGETTING STARTED WITH PROGRAMMABLE LOGIC DEVICES, THE 16V8 AND 20V8
GETTING STARTED WITH PROGRAMMABLE LOGIC DEVICES, THE 16V8 AND 20V8 Robert G. Brown All Rights Reserved August 25, 2000 Alta Engineering 58 Cedar Lane New Hartford, CT 06057-2905 (860) 489-8003 www.alta-engineering.com
More informationAdvanced VLSI Design CMOS Processing Technology
Isolation of transistors, i.e., their source and drains, from other transistors is needed to reduce electrical interactions between them. For technologies
More informationDDR SDRAM SODIMM. MT8VDDT3264H 256MB 1 MT8VDDT6464H 512MB For component data sheets, refer to Micron s Web site: www.micron.com
SODIMM MT8VDDT3264H 256MB 1 MT8VDDT6464H 512MB For component data sheets, refer to Micron s Web site: www.micron.com 256MB, 512MB (x64, SR) 200-Pin SODIMM Features Features 200-pin, small-outline dual
More informationThe MOSFET Transistor
The MOSFET Transistor The basic active component on all silicon chips is the MOSFET Metal Oxide Semiconductor Field Effect Transistor Schematic symbol G Gate S Source D Drain The voltage on the gate controls
More informationDDR2 SDRAM SODIMM MT16HTF12864H 1GB MT16HTF25664H 2GB
Features DDR2 SDRAM SODIMM MT16HTF12864H 1GB MT16HTF25664H 2GB For component data sheets, refer to Micron s Web site: www.micron.com Features 200-pin, small outline dual in-line memory module (SODIMM)
More informationLecture 5: Gate Logic Logic Optimization
Lecture 5: Gate Logic Logic Optimization MAH, AEN EE271 Lecture 5 1 Overview Reading McCluskey, Logic Design Principles- or any text in boolean algebra Introduction We could design at the level of irsim
More informationMemory Testing. Memory testing.1
Memory Testing Introduction Memory Architecture & Fault Models Test Algorithms DC / AC / Dynamic Tests Built-in Self Testing Schemes Built-in Self Repair Schemes Memory testing.1 Memory Market Share in
More informationDDR SDRAM UDIMM MT16VDDT6464A 512MB MT16VDDT12864A 1GB MT16VDDT25664A 2GB
DDR SDRAM UDIMM MT16VDDT6464A 512MB MT16VDDT12864A 1GB MT16VDDT25664A 2GB For component data sheets, refer to Micron s Web site: www.micron.com 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM Features
More informationHere we introduced (1) basic circuit for logic and (2)recent nano-devices, and presented (3) some practical issues on nano-devices.
Outline Here we introduced () basic circuit for logic and (2)recent nano-devices, and presented (3) some practical issues on nano-devices. Circuit Logic Gate A logic gate is an elemantary building block
More informationUser s Manual HOW TO USE DDR SDRAM
User s Manual HOW TO USE DDR SDRAM Document No. E0234E30 (Ver.3.0) Date Published April 2002 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2002 INTRODUCTION This manual is intended for users
More informationCHAPTER 7: The CPU and Memory
CHAPTER 7: The CPU and Memory The Architecture of Computer Hardware, Systems Software & Networking: An Information Technology Approach 4th Edition, Irv Englander John Wiley and Sons 2010 PowerPoint slides
More informationYaffs NAND Flash Failure Mitigation
Yaffs NAND Flash Failure Mitigation Charles Manning 2012-03-07 NAND flash is one of very few types of electronic device which are knowingly shipped with errors and are expected to generate further errors
More informationLow Power AMD Athlon 64 and AMD Opteron Processors
Low Power AMD Athlon 64 and AMD Opteron Processors Hot Chips 2004 Presenter: Marius Evers Block Diagram of AMD Athlon 64 and AMD Opteron Based on AMD s 8 th generation architecture AMD Athlon 64 and AMD
More informationPass Gate Logic An alternative to implementing complex logic is to realize it using a logic network of pass transistors (switches).
Pass Gate Logic n alternative to implementing complex logic is to realize it using a logic network of pass transistors (switches). Switch Network Regeneration is performed via a buffer. We have already
More informationSwitch Fabric Implementation Using Shared Memory
Order this document by /D Switch Fabric Implementation Using Shared Memory Prepared by: Lakshmi Mandyam and B. Kinney INTRODUCTION Whether it be for the World Wide Web or for an intra office network, today
More informationSemiconductor Memory Design
CHAPTER 8 Semiconductor Memory Design CHAPTER OUTLINE 8.1 Introduction 8.2 MOS Decoders 8.3 Static RAM Cell Design 8.4 SRAM Column I/O Circuitry 8.5 Memory Architecture 8.6 Summary References Prolems 8.1
More informationData remanence in Flash Memory Devices
Data remanence in Flash Memory Devices Sergei Skorobogatov 1 Data remanence Residual representation of data after erasure Magnetic media SRAM and DRAM Low-temperature data remanence Long-term retention
More informationADQYF1A08. DDR2-1066G(CL6) 240-Pin O.C. U-DIMM 1GB (128M x 64-bits)
General Description ADQYF1A08 DDR2-1066G(CL6) 240-Pin O.C. U-DIMM 1GB (128M x 64-bits) The ADATA s ADQYF1A08 is a 128Mx64 bits 1GB DDR2-1066(CL6) SDRAM over clocking memory module, The SPD is programmed
More informationDDR3 SDRAM UDIMM MT8JTF12864A 1GB MT8JTF25664A 2GB
DDR3 SDRAM UDIMM MT8JTF12864A 1GB MT8JTF25664A 2GB 1GB, 2GB (x64, SR) 240-Pin DDR3 SDRAM UDIMM Features For component data sheets, refer to Micron s Web site: www.micron.com Features DDR3 functionality
More informationChapter 10 Advanced CMOS Circuits
Transmission Gates Chapter 10 Advanced CMOS Circuits NMOS Transmission Gate The active pull-up inverter circuit leads one to thinking about alternate uses of NMOS devices. Consider the circuit shown in
More informationFeatures. DDR3 SODIMM Product Specification. Rev. 1.7 Feb. 2016
Features DDR3 functionality and operations supported as defined in the component data sheet 204pin, small-outline dual in-line memory module (SODIMM) Fast data transfer rates: DDR3-1066(PC3-8500) DDR3-1333(PC3-10600)
More informationLecture 030 DSM CMOS Technology (3/24/10) Page 030-1
Lecture 030 DSM CMOS Technology (3/24/10) Page 030-1 LECTURE 030 - DEEP SUBMICRON (DSM) CMOS TECHNOLOGY LECTURE ORGANIZATION Outline Characteristics of a deep submicron CMOS technology Typical deep submicron
More informationLayout and Cross-section of an inverter. Lecture 5. Layout Design. Electric Handles Objects. Layout & Fabrication. A V i
Layout and Cross-section of an inverter Lecture 5 A Layout Design Peter Cheung Department of Electrical & Electronic Engineering Imperial College London V DD Q p A V i V o URL: www.ee.ic.ac.uk/pcheung/
More informationMemory ICS 233. Computer Architecture and Assembly Language Prof. Muhamed Mudawar
Memory ICS 233 Computer Architecture and Assembly Language Prof. Muhamed Mudawar College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals Presentation Outline Random
More informationDDR2 SDRAM SODIMM MT8HTF3264HD 256MB MT8HTF6464HD 512MB MT8HTF12864HD 1GB For component data sheets, refer to Micron s Web site: www.micron.
DDR2 SDRAM SODIMM MT8HTF3264HD 256MB MT8HTF6464HD 512MB MT8HTF12864HD 1GB For component data sheets, refer to Micron s Web site: www.micron.com 256MB, 512MB, 1GB (x64, DR): 200-Pin DDR2 SODIMM Features
More informationA 10,000 Frames/s 0.18 µm CMOS Digital Pixel Sensor with Pixel-Level Memory
Presented at the 2001 International Solid State Circuits Conference February 5, 2001 A 10,000 Frames/s 0.1 µm CMOS Digital Pixel Sensor with Pixel-Level Memory Stuart Kleinfelder, SukHwan Lim, Xinqiao
More informationPACKAGE OUTLINE DALLAS DS2434 DS2434 GND. PR 35 PACKAGE See Mech. Drawings Section
PRELIMINARY DS2434 Battery Identification Chip FEATURES Provides unique ID number to battery packs PACKAGE OUTLINE Eliminates thermistors by sensing battery temperature on chip DALLAS DS2434 1 2 3 256
More informationFairchild Solutions for 133MHz Buffered Memory Modules
AN-5009 Fairchild Semiconductor Application Note April 1999 Revised December 2000 Fairchild Solutions for 133MHz Buffered Memory Modules Fairchild Semiconductor provides several products that are compatible
More informationDDR2 SDRAM SODIMM MT8HTF6464HDZ 512MB MT8HTF12864HDZ 1GB. Features. 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM. Features
DDR SDRAM SODIMM MT8HTF6464HDZ 5MB MT8HTF864HDZ GB 5MB, GB (x64, DR) 00-Pin DDR SODIMM Features Features 00-pin, small-outline dual in-line memory module (SODIMM) Fast data transfer rates: PC-300, PC-400,
More information1 Products A. MEMORY. Personal Computer. Portable Permanent Storage. Main Unit. Main Permanent Storage. Display. Keyboard.
1 Products A. MEMORY Memory and data storage take many forms, even in a single computer system. Figure 1-1 shows a simplified block diagram of a personal computer, indicating the various active sections
More informationClass 11: Transmission Gates, Latches
Topics: 1. Intro 2. Transmission Gate Logic Design 3. X-Gate 2-to-1 MUX 4. X-Gate XOR 5. X-Gate 8-to-1 MUX 6. X-Gate Logic Latch 7. Voltage Drop of n-ch X-Gates 8. n-ch Pass Transistors vs. CMOS X-Gates
More informationCMOS Logic Integrated Circuits
CMOS Logic Integrated Circuits Introduction CMOS Inverter Parameters of CMOS circuits Circuits for protection Output stage for CMOS circuits Buffering circuits Introduction Symetrical and complementary
More informationBasic Computer Organization
Chapter 2 Basic Computer Organization Objectives To provide a high-level view of computer organization To describe processor organization details To discuss memory organization and structure To introduce
More informationDDR2 SDRAM SODIMM MT4HTF6464HZ 512MB. Features. 512MB (x64, SR) 200-Pin DDR2 SODIMM. Features. Figure 1: 200-Pin SODIMM (MO-224 R/C C)
DDR2 SDRAM SODIMM MT4HTF6464HZ 512MB 512MB (x64, SR) 200-Pin DDR2 SODIMM Features Features 200-pin, small-outline dual in-line memory module (SODIMM) Fast data transfer rates: PC2-3200, PC2-4200, PC2-5300,
More informationMobile SDRAM. MT48H16M16LF 4 Meg x 16 x 4 banks MT48H8M32LF 2 Meg x 32 x 4 banks
Features Mobile SDRAM MT48H6M6LF 4 Meg x 6 x 4 banks MT48H8M32LF 2 Meg x 32 x 4 banks Features Fully synchronous; all signals registered on positive edge of system clock V DD /V D =.7.95V Internal, pipelined
More informationUniversity of Texas at Dallas. Department of Electrical Engineering. EEDG 6306 - Application Specific Integrated Circuit Design
University of Texas at Dallas Department of Electrical Engineering EEDG 6306 - Application Specific Integrated Circuit Design Synopsys Tools Tutorial By Zhaori Bi Minghua Li Fall 2014 Table of Contents
More information路 論 Chapter 15 System-Level Physical Design
Introduction to VLSI Circuits and Systems 路 論 Chapter 15 System-Level Physical Design Dept. of Electronic Engineering National Chin-Yi University of Technology Fall 2007 Outline Clocked Flip-flops CMOS
More informationDS1220Y 16k Nonvolatile SRAM
Not Recommended for New Design DS122Y 16k Nonvolatile SRAM www.maxim-ic.com FEATURES years minimum data retention in the absence of external power Data is automatically protected during power loss Directly
More informationINSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad - 500 043
INSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad - 500 043 ELECTRONICS AND COMMUNICATION ENGINEERING Course Title VLSI DESIGN Course Code 57035 Regulation R09 COURSE DESCRIPTION Course Structure
More informationFlash Memory Jan Genoe KHLim Universitaire Campus, Gebouw B 3590 Diepenbeek Belgium
Flash Memory Jan Genoe KHLim Universitaire Campus, Gebouw B 3590 Diepenbeek Belgium http://www.khlim.be/~jgenoe [1] http://en.wikipedia.org/wiki/flash_memory Geheugen 1 Product evolution Jan Genoe: Geheugen
More informationWinbond W971GG6JB-25 1 Gbit DDR2 SDRAM 65 nm CMOS DRAM Process
Winbond W971GG6JB-25 1 Gbit DDR2 SDRAM 65 nm CMOS DRAM Process Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor
More informationUnderstanding Memory TYPES OF MEMORY
Understanding Memory TYPES OF MEMORY In this study unit, you ll learn about physical and logical memory. Physical memory comes in two types, random access memory (RAM) and read-only memory (ROM). Typically,
More informationSequential 4-bit Adder Design Report
UNIVERSITY OF WATERLOO Faculty of Engineering E&CE 438: Digital Integrated Circuits Sequential 4-bit Adder Design Report Prepared by: Ian Hung (ixxxxxx), 99XXXXXX Annette Lo (axxxxxx), 99XXXXXX Pamela
More informationSTMicroelectronics. Deep Sub-Micron Processes 130nm, 65 nm, 40nm, 28nm CMOS, 28nm FDSOI. SOI Processes 130nm, 65nm. SiGe 130nm
STMicroelectronics Deep Sub-Micron Processes 130nm, 65 nm, 40nm, 28nm CMOS, 28nm FDSOI SOI Processes 130nm, 65nm SiGe 130nm CMP Process Portfolio from ST Moore s Law 130nm CMOS : HCMOS9GP More than Moore
More informationDS1225Y 64k Nonvolatile SRAM
DS1225Y 64k Nonvolatile SRAM www.maxim-ic.com FEATURES years minimum data retention in the absence of external power Data is automatically protected during power loss Directly replaces 2k x 8 volatile
More informationLogical Operations. Control Unit. Contents. Arithmetic Operations. Objectives. The Central Processing Unit: Arithmetic / Logic Unit.
Objectives The Central Processing Unit: What Goes on Inside the Computer Chapter 4 Identify the components of the central processing unit and how they work together and interact with memory Describe how
More informationDDR SDRAM SODIMM MT16VDDF6464H 512MB MT16VDDF12864H 1GB
SODIMM MT16VDDF6464H 512MB MT16VDDF12864H 1GB 512MB, 1GB (x64, DR) 200-Pin DDR SODIMM Features For component data sheets, refer to Micron s Web site: www.micron.com Features 200-pin, small-outline dual
More informationCO2005: Electronics I (FET) Electronics I, Neamen 3th Ed. 1
CO2005: Electronics I The Field-Effect Transistor (FET) Electronics I, Neamen 3th Ed. 1 MOSFET The metal-oxide-semiconductor field-effect transistor (MOSFET) becomes a practical reality in the 1970s. The
More information1.55V DDR2 SDRAM FBDIMM
1.55V DDR2 SDRAM FBDIMM MT18RTF25672FDZ 2GB 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Features Features 240-pin, fully buffered DIMM (FBDIMM) Very low-power DDR2 operation Component configuration: 256 Meg
More informationMICROPROCESSOR BCA IV Sem MULTIPLE CHOICE QUESTIONS
MICROPROCESSOR BCA IV Sem MULTIPLE CHOICE QUESTIONS 1) Which is the microprocessor comprises: a. Register section b. One or more ALU c. Control unit 2) What is the store by register? a. data b. operands
More informationFeatures. DDR3 Unbuffered DIMM Spec Sheet
Features DDR3 functionality and operations supported as defined in the component data sheet 240-pin, unbuffered dual in-line memory module (UDIMM) Fast data transfer rates: PC3-8500, PC3-10600, PC3-12800
More informationDDR2 SDRAM SODIMM MT8HTF12864HZ 1GB MT8HTF25664HZ 2GB. Features. 1GB, 2GB (x64, SR) 200-Pin DDR2 SDRAM SODIMM. Features
DDR2 SDRAM SODIMM MT8HTF12864HZ 1GB MT8HTF25664HZ 2GB 1GB, 2GB (x64, SR) 200-Pin DDR2 SDRAM SODIMM Features Features 200-pin, small-outline dual in-line memory module (SODIMM) Fast data transfer rates:
More informationComputers. Hardware. The Central Processing Unit (CPU) CMPT 125: Lecture 1: Understanding the Computer
Computers CMPT 125: Lecture 1: Understanding the Computer Tamara Smyth, tamaras@cs.sfu.ca School of Computing Science, Simon Fraser University January 3, 2009 A computer performs 2 basic functions: 1.
More informationInterfacing 3V and 5V applications
Authors: Tinus van de Wouw (Nijmegen) / Todd Andersen (Albuquerque) 1.0 THE NEED FOR TERFACG BETWEEN 3V AND 5V SYSTEMS Many reasons exist to introduce 3V 1 systems, notably the lower power consumption
More information