Memory Design. Random Access Memory. Row decoder. n bit address. 2 m+k memory cells wide. n-1:k. Column Decoder. k-1:0.

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1 Memory Design Random Access Memory Row decoder 2 m+k memory cells wide n-1:k k-1:0 Column Decoder n bit address Sense Amplifier m bit data word

2 Memory Timing: Approaches Address bus Row Address Column Address RAS CAS Address Bus Address Address transition initiates memory operatio RAS -CAS timing DRAM Timing Multiplexed Adressing SRAM Timing Self-timed

3 Memory Timing DRAM read cycle Activate RAS, and place row address on bus Row decoders select appropriate row Activate CAS, and place column address on bus Sense amps are activated and data is placed on the data bus

4 Memory Timing from Ars Technica RAM Guide, by Jon Stokes, Ars Technica LLC

5 Read-Only Memory Cells BL BL BL 1 WL WL V DD WL BL BL BL 0 WL WL WL GND Diode ROM MOS ROM 1 MOS ROM 2

6 MOS OR ROM BL[0] BL[1] BL[2] BL[3] WL[0] V DD WL[1] WL[2] V DD WL[3] V bias Pull-down loads

7 MOS NOR ROM V DD Pull-up devices WL[0] WL [1] GND WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3]

8 MOS NOR ROM Layout BL0 BL1 BL2 BL3 Cell (9.5λ x 7λ) WL0 WL1 GND Programmming using the Active Layer Only WL2 WL3 GND Polysilicon Metal1 Diffusion Metal1 on Diffusion

9 MOS NOR ROM Layout Cell (11λ x 7λ) Programmming using the Contact Layer Only Polysilicon Metal1 Diffusion Metal1 on Diffusion

10 MOS NAND ROM V DD Pull-up devices BL[0] BL[1] BL[2] BL[3] WL[0] WL[1] WL[2] WL[3] All word lines high by default with exception of selected row

11 MOS NAND ROM Layout Cell (8λ x 7λ) Programmming using the Metal-1 Layer Only No contact to VDD or GND necessary; drastically reduced cell size Loss in performance compared to NOR ROM Polysilicon Diffusion Metal1 on Diffusion

12 Equivalent Transient Model for MOS NOR ROM Model for NOR ROM V DD BL WL r word C bit c word Word line parasitics Wire capacitance and gate capacitance Wire resistance (polysilicon( polysilicon) Bit line parasitics Resistance not dominant (metal) Drain and Gate-Drain capacitance

13 Equivalent Transient Model for MOS NAND ROM Model for NAND ROM V DD BL r bit C L WL r word c bit c word Word line parasitics Similar to NOR ROM Bit line parasitics Resistance of cascaded transistors dominates Drain/Source and complete gate capacitance

14 Decreasing Word Line Delay WL Driver Polysilicon word line Metal word line (a) Driving the word line from both sides Metal bypass WL K cells (b) Using a metal bypass Polysilicon word line (c) Use silicides

15 Precharged MOS NOR ROM f pre V DD Precharge devices WL [0] WL [1] GND WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3] PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design.

16 Non-Volatile Memories The Floating-gate transistor (FAMOS) Source Floating gate Gate Drain D t ox G n + Substrate p t ox n +_ S Device cross-section Schematic symbol

17 Floating-Gate Transistor Programming 20 V 0 V 5 V 10 V 5 V 20 V -5 V 0 V -2.5 V 5 V S D S D S D Avalanche injection Removing programming voltage leaves charge trapped Programming results in higher V T.

18 FLOTOX EEPROM Floating gate Source Gate Drain I nm n 1 Substrate p n 1 10 nm -10 V 10 V V GD FLOTOX transistor Fowler-Nordheim I-V characteristic

19 EEPROM Cell BL WL V DD Absolute threshold control is hard Unprogrammed transistor might be depletion 2 transistor cell

20 Flash EEPROM Control gate Floating gate erasure n + source programming p-substrate Thin tunneling oxide n + drain Many other options

21 Cross-sections of NVM cells Flash Courtesy Intel EPROM

22 Basic Operations in a NOR Flash Memory_ Erase cell array BL 0 BL 1 12 V G 0 V WL 0 S D 12V 0 V WL 1 open open

23 Basic Operations in a NOR Flash Memory_ Write 12 V BL 0 BL 1 G 6 V 12 V WL 0 S D 0 V WL 1 6 V 0 V

24 Basic Operations in a NOR Flash Memory_ Read 5 V G 1 V 5 V BL 0 BL 1 WL 0 S D 0 V WL 1 1 V 0 V

25 Memory Design Register File RAM with multiple read or write ports You can read or write multiple data values at the same time Useful in data processing applications

26 Memory Design Register File Cell RB1 RB0 RB1 RB0 Word select 0 Word select 1 Write enable Write data

27 Memory Design Content Addressable Memory (CAM) Instead of finding memory by address, find it by content Search or match every single word in memory array

28 Static CAM Memory Cell Word Bit CAM Bit Bit CAM Bit Bit M4 M8 M6 M9 M7 M5 Bit Word CAM CAM Word Match S M3 int M2 S M1 Wired-NOR Match Line

29 CAM in Cache Memory CAM ARRAY Hit Logic SRAM ARRAY AddressDecoder Input Drivers Sense Amps / Input Drivers Address Tag Hit R/W Data

30 Memory Design Other memory structures FIFOs LIFOs SIPOs

31 Periphery Decoders Sense Amplifiers Input/Output Buffers Control / Timing Circuitry

32 Memory Design Row decoder A1 A0

33 Memory Design Row decoder With multiple inputs (>4), two problems Speed of gates becomes a problem Use hierarchy of NANDS/NORS Use predecoding - decode upper bits first and use lower bits to select from there Increased fanout Use minimum sized input gates

34 Hierarchical Decoders Multi-stage implementation improves performance WL 1 WL 0 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 2 A 3 A 2 A 3 A 2 A 3 A 2 A 3 A 1 A 0 A 0 A 1 A 3 A 2 A 2 A 3 NAND decoder using 2-input pre-decoders

35 Dynamic Decoders Precharge devices GND GND V DD WL 3 V DD WL 3 WL 2 V DD WL 2 WL 1 WL 0 V DD WL 1 WL 0 V DD φ A 0 A 0 A 1 A 1 A 0 A 0 A 1 A 1 φ 2-input NOR decoder 2-input NAND decoder

36 Memory Design Column decoder Memory Cells A1 A0 Data Out

37 Memory Design Column decoder Memory Cells Data Out A1 A0

38 Memory Design Column decoder AND-decoder based On the order of N 2N N transistors Binary tree based Slow because of the series of pass- transistors Usually use a combination of the two

39 Memory Design Sense Amplifier Time to get through row decoder, column pull-down and column decoder can be very long Use a sense amplifier to speed it up Sense small differences in voltage and amplify it to rail voltage Can be differential or single-ended Usually use transistors with high threshold voltages

40 Sense Amplifiers t p = C Δ V I av make ΔV as small as possible large small Idea: Use Sense Amplifer small transition s.a. input output

41 Differential Sense Amplifier V DD M 3 M 4 y Out bit M 1 M 2 bit SE M 5 Directly applicable to SRAMs

42 Next class Memory Reliability and Yield Control logic