ELE 3230 Microprocessors and Computer Systems

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1 ELE 3230 Microprocessors and Computer Systems Chapter 8 Memory Address Decoding (Brey: Ch10-2; Hall: pp )

2 Memory Address Decoding Typically, a system memory is formed by many different memory chips. There are more lines on the address bus than the number of address pins available on a given memory chip. Address decoding is used to monitor all address lines not connected directly to the memory chip s address pins to decide whether a particular chip is being addressed. A ddress Bus Memory Chip data bus CS IO/ M SEL ELE Chapter 8 2

3 Memory Address Decoding (Cont.) The address decoder consists of logic gates and takes the address lines not used by the memory chip as input. Example: Suppose the memory chip has 11 address pins (the memory has 2 11 =2K addresses) and the address bus has 20 address lines (2 20 =1M address space). If we want to map the chip to a 2K block at the top of memory (FF800h to FFFFFh) then the decoder must generate a CS signal only when the address lines contains xxx xxxx xxxx x: don t care A 9-input AND gate connected to the 9 most significant address lines will perform the decoding function in this simple example. ELE Chapter 8 3

4 example of ROMS (32 Kbyte) ADDRESS INPUTS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 ROM D0 D1 D2 D3 D4 D5 D6 D7 DATA OUTPUT ADDRESS BUS 1 2 DATA BUS A0 A14 D0 A0 A14 D7D6 D5 D4 D3 D2 D1D0 A0 32 Kbyte 32 Kbyte A14 D7D6 D5 D4 D3 D2 D1D0 D7 Schematic symbol Connection in parallel ELE Chapter 8 4

5 Example of RAM Schematic Symbol ADDRESS INPUTS A0 A1 DATA A3 A4 A5 A6 A7 A8 A9 A10 A11 D0 D1 D2 D3 D4 D5 D6 D7 DATA INPUT/OUTPUTS R/ W READ/WRITE CHIP ENLE ELE Chapter 8 5

6 Memory Address Decoders In practice, logic gates (e.g. the AND gate in the previous example) are rarely used for memory decoding since a different set of logic gates would be needed to generate the CS signal for each memory chip. Integrated circuit address decoders e.g. 74LS138 are normally used. selection inputs Enable Inputs A 0 B 1 C 2 Outputs 74LS G2A 4 G2B 5 G1 6 7 Outputs ELE Chapter 8 6

7 Memory Address Decoders (cont.) 74LS138 can be used to decode 3 address lines to enable up to 8 memory chips (each of its output can be used to enable a different chip). All 8 outputs are not asserted when any of the enable inputs (G1, G2A, and G2B) are not asserted. Only one output is asserted when all three enable inputs are asserted, and the output asserted depends on the A,B,C selection inputs (one output for each possible combination). Sometimes an external logic gate may be used in conjunction with the 74LS138 to perform decoding using more than 3 address lines. ELE Chapter 8 7

8 Using the 74LS138 Decoder Task: Design a circuit to map eight different 2764 EPROM chips (each EPROM is organized as 8K x 8 bits) to a 64K-byte block of memory with a physical address in the range F0000h to FFFFFh. (Note: each address holds 1 byte=8 bit of data) Solution: Each 2764 EPROM may be mapped directly to an 8K-byte block. 1st block: F F1FFFh 2nd block: F F3FFFh 3rd block: F F5FFFh 4th block: F F7FFFh 5th block: F F9FFFh 6th block: FA000 - FBFFFh 7th block: FC000 - FDFFFh 8th block: FE000 - FFFFFh ELE Chapter 8 8

9 Using the 74LS138 Decoder (cont.) It is helpful to write these numbers in binary to see (1) which address lines are common to all chips and (2) which are common to all address in one chip, so they can be used to generate chip enable and chip selection. In this example, the most significant hexadecimal digit must be F (in this example) to address the 8 EPROMS. Hence address lines A16-A19 may be used to enable the 138 decoder (so that signals are only generated if A16-A19 are all asserted): G2A 74LS138 A17 A18 A19 A16 G2B G1 ELE Chapter 8 9

10 Address Decoding Example (Cont.) 1st block: F F1FFFh = nd block: F F3FFFh 3rd block: F F5FFFh 4th block: F F7FFFh Used for Used for Enable selection 5th block: F F9FFFh pins pins 6th block: FA000 - FBFFFh 7th block: FC000 - FDFFFh 8th block: FE000 FFFFFh = Notice the pattern of bits: In each 8K block, the 2nd most significant set of 4 address lines have three lines (i.e. A13-A15) which have the same values for each block but different to other blocks. We can therefore use A13-A15 to generate the individual chip selection signals of the 8 EPROMs. ELE Chapter 8 10

11 Address Decoding Example (cont.) The address pins of each EPROM must be connected to the 13 least significant address lines in order to address the 2 13 RD (=8K) bytes in each EPROM. A17 A18 A19 A13 A14 A15 A16 G2A G2B G1 74LS138 OE A0-A12 Q: What are the other possibilities to implement the input for the enable pins? data ELE Chapter 8 11

12 Example (2) of Address Decoding Task: Design the memory subsystem for a 16-bit microprocessor which has a 24-bit address bus. The system should use 64K byte SRAMS, which have a single CS input, and the total capacity should be 1M-Byte assigned to the lowest physical addresses. Show the connections to the address and data buses. Solution: Since the total memory is 1M-Byte, a total of 16 SRAM chips, each of 64k-Byte capacity, will be needed. As the data bus is 16-bits wide, the 8-bit SRAMs must be arranged in pairs. One possible solution is: ELE Chapter 8 12

13 Example (2) of Address Decoding (Cont.) Address bus (24) 24 A23 A19 A17A16 A1 A0 Chip Chip selects Word address Address bus (Selection even) 16 (Selection odd) BHE... Zero detect logic 3 Decoder EN Row 0 select Row 1 select 64K x8 SRAM 0 64K x8 SRAM 2 64K x8 SRAM 1 64K x8 SRAM 3 Row 7 select. 64K x8 SRAM K x8 SRAM 15 1-Mbyte Memory Board 16-bit data bus D0-D7 8 D8-D15 8 ELE Chapter 8 13

14 Other Address Decoders The 74LS139 is a two-to-four line decoder (i.e. 2 inputs, 4 outputs) that is sometimes used for address decoding. PROMS and EPROMS can also be used as decoders eg. A 82S147 (512x8). PROM can be used to completely replace the 74LS138 and NAND gate in the previous example, provided it has been programmed with the correct bit pattern to select the 8 chips. Programmable Logic Devices (PLA - programmable logic array, PAL - programmable array logic, and GAL - gated array logic) may also be used as address decoders. Eg. AMD 16L8 PAL: ELE Chapter 8 14

15 Other Address Decoders (Cont.) PAL16L8 ELE Chapter 8 15

16 FPLA FPLA, PROM, and PAL programmed to implement some simple logic functions A B FUSIBLE AND A B PLA FUSIBLE OR F1 = + = A B F2 = A + B F3 = F4 = A FUSIBLE OR A B (write once; like CD-R) A B PAL HARWIRED OR A O O A B PROM PROGRAMMLE AND (write many; like CD-RW) F1 = + = A B F2 = A + B F3 = F4 = A HARDWAIRED AND PAL F1 = + = A B F2 = + + = A + B F3 = F4 = + = A ELE Chapter 8 16

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