ARM. Architecture, Programming and Development Tools

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1 ARM Architecture, Programming and Development Tools

2 Lesson 1 ARM CPUs 2

3 Outline ARM Processors Features of a RISC architecture ARM Family and ARM many variant architectures 3

4 Examples of Systems needing highperformance precise- computing Image processing, Video games, Robotics and Adaptive control Mobile Devices 4

5 ARM Applications in Mobile Systems PDA Multimedia Phone Network Walkman Pocket PC Robot With Distributed Sensors Vending Machine with Wireless Support Pocket PC with VOIP 5

6 Mobile Device CPUs/MCUs - CPUs ARM-7 and ARM-9 (More than 50% devices) CPUs PowerPC 750,ColdFire, TigerSHARC MCUs ST72x, LPC21xx, 6

7 Embedded RISC Core ARM7TDMI (http://www.arm.com/news/5135.html) ARM family of general-purpose 32-bit microprocessors offers high performance and very low MIPS/watt power consumption 32-bit RISC architecture

8 Design centers around and concentrate on simple instructions Smaller and simpler processor circuit, Simpler decoding subunit. Lower power more space for other performing units 8

9 Outline.. ARM Processors Features of a RISC architecture ARM Family and ARM many variant architectures 9

10 RISC Features Same Length instructions Single Cycle Execution Hardwired implementation of Instructions Large Register Set(s) Load and Store Architecture- 10

11 Internal bus Fetch Decode Execution IR ID Hardwired Circuits Hardwired Implementation 11

12 Outline ARM Processors Features of a RISC architecture ARM family and ARM many variant architectures 12

13 ARM CPUs options- Extensive range of CPUs with third-party adaptation and application development tools 13

14 ARM Many Variant Architectures ARM Thumb (T) variants 14

15 ARM variants v1 ARM 1 v2 ARM 2, v2as -ARM 3, ARM250 v3 v3 full 32bit addressing for both data and code ARM 6, ARM 7, ARM 8 and Amulet 1 v3m - ARM 6, ARM 7 and ARM 8 v4 StrongARM, v4 ARM 9, v5 - ARM10 VFP1- ARM10 for high floating-point performance Some variants Single-precision and double-precision floating point arithmetic) on typical graphics and DSP algorithms 15

16 ARM Special Features Speed-critical control signals pipelining processing more than one instruction at the fetching, decoding and executing stages. 16

17 A three stage pipeline STAGE 1 Instruction A Execute Instruction B Execute Instruction C Execute STAGE 2 Instruction B Decode Instruction C Decode Instruction D Decode STAGE 3 Instruction C Fetch Instruction D Fetch Instruction E Fetch clock cycle n clock cycle n+1 clock cycle n+2 Time 17

18 Three stage Pipelining in superscalar processor facilitating each instruction fetch is in single cycle, decoding in single cycle and execute in the single cycle: Three times execution speed boost up Contd 18

19 ARM 7 common internal bus for the address and data of 32-bit in- 32-bit Princeton architecture bus and bus interface for 32-bit data and instructions. ARM9 - Harvard Architecture. Cond 19

20 Memory Architecture ARM 7 ARM 9 Address Data and Program, constants, stored tables Common Memory Address Program, constants and stored tables Memory Address Data Memory 20

21 Performance ARM 7 and ARM 9 support 300 MIPS (Million Instructions per Second) when die size is 0.13 µm. 21

22 ARM 7 architecture Uses 0.25µm and less die size HCMOS technology, very small die size facilitating low voltage operations and low power consumption, (very small power consumption means very low MIPS/Watt) 22

23 Processor operation on the words as per initialization. A word alignment can then be in big endian [least significant byte stored as higher bits (address 3) of a word] or little endian [least significant byte stored as lower bits (address 0) of a word]. Cond 23

24 A 32bit word Address Little Endian Big Endian Byte0 (LSB) byte1 byte2 Byte3 (MSB) Byte3 (MSB) byte2 byte1 Byte0 (LSB) Address0 Address1 Address2 Address3 Two Initialization options 24

25 Cond Fully static operation- MCU clock can be reduced to 0 and since fully MOSFETs based 25

26 Optimized for fast interrupts and DSP algorithms There are two types of requests for interrupts- Fast interrupt request (FIQ) and interrupt request (IRQ). Fast means high priority. Cond 4 gigabytes of linear address space 26

27 32-bit large set of 16 generalpurpose registers with program counter as one of the register (r15) plus CPSR and SPSR -are two other registers. Cond 27

28 ARM Family Programming Model 16 general-purpose registers with program counter as one of the register (R15). 28

29 - Registers R0 R1 R2 R3 R4 R5 R6 R7 Lo registers R8 R9 R10 R11 R12 Hi registers SP (R13) Stack Pointer LR (R14) Link Register PC (Rr15) Program Counter CPSR SPSR 29

30 CPSR and SPSR CPSR (Conditions and Processor Status Register) SPSR ( Saved Program Status Register) Saves Program Status Register from CPSR on branch and link (routine call) and SPSR can be stacked for each processor mode 30

31 Cond 32-bit RALU and highperformance multiplier Instructions have 8-, 16-, and 32- bit data types 31

32 RALU Temp 1 Temp 2 R0 R15 CPSR +, -, x Rotate ALU MAC Multi-bit shifter SPSR 32

33 Cond Coprocessor interface to connect coprocessors, like DSP processors and Java Accelerators 33

34 Cond System control functions implemented in standard lowpower logic Cost-effective, compact chip 34

35 ARM 7 T Variants 35

36 ARM TDMI instruction set options- 1. High-performance 32-bit instruction set- 2. High-code-density Thumb 16-bit instruction set than 32-bit instruction architecture 36

37 Summary

38 ARM family general-purpose 32-bit superscalar processors Three stage Pipeline High performance and very low MIPS/watt power consumption 32-bit RISC architecture

39 32 bit Sixteen Registers plus CPSR and SPSR ARM 9 and ARM7 Harvard and Princeton architectures Initialized options: little or big endian modes 32/16/8 bit data types Two interrupts - Fast interrupt request (FIQ) and interrupt request (IRQ)

40 - ARM has Many Variants - T variants give alternate option of high code density with 16-bit instructions ARM 7 and ARM 9 popularly used

41 ARM applications Mobile Devices, PocketPC, PDA, Control Systems, DSP based applications Speech and Image processing Robotics

42 End of Lesson 1 on ARM CPUs

43 THANK YOU 43

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