AP1910 Anwell Semiconductor Corp.

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1 Universal High Brightness LED Driver Controller Features Buck system efficiency:>90% Open loop peak current controller Internal 8~450V linear regulator Constant Current LED Driver LED string from one to hundreds of diodes Support linear and PWM dimming interface Requires few external components 8 Lead SOIC Packages RoHS Compliant and 00% Lead (Pb)-Free and Green (Halogen Free with Commercial Standard) Constant off time function when duty cycle over 50% Applications LED driver applications RGB backlighting LED driver General purpose constant current source Chargers Non-isolation LED bulb General Description The is a high-efficiency LED driver control IC. It drives LEDs with constant current and uses fewer components. The is an open loop, current mode control IC. It can be programmed to operate in either a constant frequency or constant off-time mode. It includes an 8~450V linear regulator which allows it to work in wide input voltage range without external low voltage power supply. The is recommended in buck LED drivers applications, LED luminance can be easily adjusted by 's 0~00% PWM dimming and 0~45mV linear dimming functions. The is suitable for buck LED drivers. The system has excellent stable response because of open loop current mode control. The controller achieves good output current regulation and need no compensation. Typical Application Circuit (A) Constant Frequency mode L FUSE 85~65VAC TVS C T CX C BD C3 R D LED N NTC CX LED R3 8 RT VIN L LD CS C4 6 5 VDD PWMD GND GATE 3 4 C5 R5 R4 All reserved by AnSC 0 Page: / V.6-04/09/9

2 (B) Constant Off-time mode L FUSE 85~65VAC TVS C T CX C BD C3 R D LED N NTC CX LED R3 8 RT VIN L LD CS C4 6 5 VDD PWMD GND GATE 3 4 C5 R5 R4 Ordering Information Accuracy Code Package Code Lead Free Code Version Code Version Code: A:First Issue B:Second Issue C Lead Free Code: P:Commercial Standard, Lead (Pb) Free and Phosphorous (P) Free Package G:Green (Halogen Free with Commercial Standard) Package Code: A:SOIC-8 Accuracy Code: = 4% Accuracy = % Accuracy All reserved by AnSC 0 Page: / V.6-04/09/9

3 8 Anwell Semiconductor Corp. Pin Description Part No. Pin Symbol Pin Description VIN Input voltage 8~450V DC CS Sense LED string current 8 (Top View) SOIC-8 3 GND Ground Pin 4 GATE Driver external N-Mosfet 5 PWMD PWM dimming input from 0%~00% 6 VDD Internal power source input for logic circuit LD Linear dimming input 8 RT Frequency controlled by external resistor. Constant off-time: resistor connected to GATE Constant frequency: resistor connected to GND Package Marking Information SOIC-8 (Top View) Represents Version Code Mark Description Version Code Represents Accuracy Mark Description =4% accuracy =% accuracy 3 Represents Products Lead Free type Mark Description G Green (Halogen Free) Example: 4 5 Represents Products Series Description date code 3 6 A G M T 4 5 Part No.:A-GA Year Code:0 Week Code: th week Green (Halogen Free) All reserved by AnSC 0 Page: 3/ V.6-04/09/9

4 Absolute Maximum Ratings Parameter (PIN) Symbol Ratings Units VIN to GND V VDD, LD, PWMD, GATE to GND V CS, RT, to GND -- V Junction Temperature T J +50 C Thermal Resistance SOIC-8 θ JA 30 C/W Power Dissipation SOIC-8 P D 630 mw Operating Ambient Temperature T OPR -40 ~ +85 C Storage Temperature T STG -55 ~ +50 C Lead Temperature (soldering, 0sec) C Note: * The power dissipation values are based on the condition that junction temperature T J and ambient temperature T A difference is 00 C. * Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and function operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum -rated conditions for extended periods may affect device reliability. *Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the recommended operating conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Function Block Diagram ` VIN VDD 6 HV Regulator.5V LDO 5V OSC 8 RT 45mV LD S R Q Driver 4 GATE CS OTP 3 GND 5 PWMD All reserved by AnSC 0 Page: 4/ V.6-04/09/9

5 Electrical Characteristics (T A =5, unless otherwise noted.) Symbol Parameter Test Conditions Min Typ Max Unit V INDC I INSD V DD UVLO Input DC supply voltage range Shut-Down mode supply current Internal regulated voltage VDD under voltage lockout threshold Line Voltage or DC input voltage V PWM_D to GND, VIN=8V ma V IN =8~450V V V DD rising V UVLO UVLO hysteresis V DD falling 500 mv V EN(hi) PWMD input high level V IN =8~450V.0 V V EN(lo) PWMD input low level V IN =8~450V 0.8 V V CS-TH V LD T BLANK F OSC T OFF Current sense pull-in threshold voltage Linear dimming pin voltage range Current sense blanking time Oscillator frequency Constant off-time V IN =8~450V,T A =5 o C mv V IN =8~ mv T A =5 o C, V LD = V DD, V CS = V CS-TH + 50mV after T BLANK ns R OSC = MΩ (Connect to RT and GND) KHz R OSC = 00KΩ (Connect to RT and GND) 93 KHz R OFF = MΩ (Connect to RT and GATE) 54 us R OFF = 00KΩ (Connect to RT and GATE) 3 us D MAX Maximum duty cycle HV floating 95 % I SOURCE GATE sourcing current V GATE =0V, V DD =.5V 65 ma I SINK GATE sinking current V GATE = V DD, V DD =.5V 65 ma t R GATE rising time C GATE = 500pF, V DD =.5V ns t F GATE falling time C GATE = 500pF, V DD =.5V ns T TST T TSH Thermal Shutdown Temperature Thermal Shutdown Hysteresis 55 C 40 C Note : The suggest Qg of NMOS around 6.5 nc(typ.),it can improve efficiency. All reserved by AnSC 0 Page: 5/ V.6-04/09/9

6 Detail Description The is a low-cost buck, boost or buck-boost converter controller specifically designed for driving multi LED strings or arrays. It can be operated from either universal 90~64Vac or DC voltage between 0 and 450Vdc. The can also drive multiple strings of High-Brightness (HB) LEDs. The could regulate constant current to ensure controlled brightness and spectrum of the LEDs. Constant current driving method can also improve LEDs lifetime. The supports soft start function to reduce inrush current. It can add resistor from VDD to LD pin to generate ~5uA current and charge LD capacitor. The voltage level will rising with slop and correspond to CS pin current limit level. The IC has feed-forward compensation by setting suitable resistor in CS pin to keep LED string constant current when line voltage variation. The include an internal high voltage linear regulator to generate fix VDD voltage supply to IC internal logic circuit. LED Driver Operation The controls all basic types of converters, non-isolated, operating in continuous or discontinuous conduction mode. N-MOSFET is turned on when PIN GATE is high, and the input energy is delivered to LED driver and stored in an inductor. The energy is stored in the inductor free wheeling itself through the string of LEDs when power switch off. When the VDD pin voltage exceeds the UVLO threshold, the internal power switch is enabled. The output current is controlled by mean of limiting peak current of CS pin. The peak current limit level is set by LD pin of the. The using Buck topology needs to design the duty cycle below 50% to prevent unregulated Gate output pulse. It can apply resistor between RT and Gate pin. That is constant off time function when duty over 50%. Supply Current A current of 0.mA is needed after start up the controller. This current is generated from internal HV regulator circuit. The without using bulky startup resistors typically required in the offline applications. Moreover, in many applications using can be continuously powered because of its internal linear regulator that provides a regulated voltage of.5v for internal circuits. The IC power consumption is very low when high line input voltage because of low operating current. Current Sense The current sense input of the goes to the non-inverting inputs of two comparators. The inverting terminal of one comparator is tied to an internal 45mV reference whereas the inverting terminal of the other comparator is connected to the LD pin. The outputs of both these comparators are fed into an or gate and the output of the or gate is fed into the reset pin of the flip-flop. Thus the comparator which has the lowest voltage at the inverting terminal determines when the GATE output is turned off. The outputs of the comparators also include a 500ns blanking time due to the turn on spike current. Some solution will add RC filter to prevent this situation. Linear Dimming The has two type dimming functions. The Linear dimming is setting LD pin voltage level to adjust current limit. PWM Dimming PWM dimming can be achieved by driving the PWMD pin with a low frequency square wave signal. When the PWM signal is zero, the GATE driver is turned off and when the PWMD signal if high, the GATE driver is enabled. On the other hand, the GATE driver is disabled. All reserved by AnSC 0 Page: 6/ V.6-04/09/9

7 Off-time (us) Frequency (KHz) Anwell Semiconductor Corp. Detail Description (Continued) Operating Frequency The operating frequency of can be set by the external resistor connected to RT pin. Connecting the resistor from RT to GND for constant frequency operation mode or RT to GATE for constant off-time operation mode. Following diagram is the reference data for setting switching frequency. Constant Freqency mode RT (KΩ) Inductor Design Constant Off-time mode RT (KΩ) Referring to the typical application circuit below the value can be calculated from the desired peak-to-peak LED ripple current in the inductor. Knowing the nominal rectified input line voltage V IN =0V*.44=0V. The switching duty ratio can be determined as: D V / V 30 / LEDS IN Then, given the switching frequency 50KHz. The required on time of the MOSFET transistor can be calculated: T D / f 3.5 s, T 6.48 s ON OSC OFF The required value of the inductor is given by: VIN VLED * TON 30%* ILED L L ( V V )* T / (0.3* I ) 4.69mH IN LED ON LED Input Bulk Capacitor An input filter capacitor should be designed to hold the rectified AC voltage above twice the LED string voltage throughout the AC line cycle. Assuming 5% relative voltage ripple across the capacitor, a simplified formula for the minimum value of the bulk input capacitor is given by: I LED *30%* VLED CMINVIN C I V V F MIN LED *0.06* LED / IN A passive PFC circuit at the input requires using two series connected capacitors at the place of calculated C MIN. Each of these identical capacitors should be rate for 0.5 of the input voltage and have twice as much capacitance. Typically, such ripple current is selected to be 30% of the nominal LED current in the example given here, the nominal current I LED is 350mA. The next step is determining the total voltage drop across the LED string. For example, when the string consists of 0 HB LEDs and each diode has forward voltage drop of 3V at its nominal current. The total LEDs voltage V LEDS is 30V. All reserved by AnSC 0 Page: / V.6-04/09/9

8 Package Outline SOIC-8 All reserved by AnSC 0 Page: 8/ V.6-04/09/9

9 Classification Reflow Profiles Average ramp-up rate (T L to T P ) Profile Feature Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (T L ) - Time (t L ) Pb-Free / Green Assembly 3 C/second max 50 C 00 C seconds C seconds Peak/Classification Temperature (Tp) See table Time within 5 C of actual Peak Temperature (tp) Ramp-down Rate Time 5 C to Peak Temperature Notes: ) All temperatures refer to topside of the package. ) Measured on the body surface seconds 6 C/second max 8 minutes max Classification Reflow Profiles (Continued) Table. Pb-free / Green Process Package Classification Reflow Temperatures Package Thickness Volume mm³ <350 Volume mm³ 350~000 Volume mm³ 000 <.5 mm C* C* C*.6-.5 mm C* C* C*.5 mm C* C* C* Notes: * Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0 C. For example 60 C+0 C) at the rated MSL level. All reserved by AnSC 0 Page: 9/ V.6-04/09/9

10 Appendix Date Code Rule Year Week Day-From Day-End Date-Code Year Week Day-From Day-End Date-Code 0 0// 0// LV /8/9 0/8/5 NG 0 0//8 0//4 LW /8/6 0/9/ NH 0 3 0//5 0// LX /9/ 0/9/8 NJ 0 4 0// 0//8 LY 0 3 0/9/9 0/9/5 NK 0 5 0//9 0//4 MA /9/6 0/9/ NL 0 6 0//5 0// MB /9/3 0/9/9 NM 0 0// 0//8 MC /9/30 0/0/6 NN 0 8 0//9 0//5 MD 0 4 0/0/ 0/0/3 NP 0 9 0//6 0/3/3 ME 0 4 0/0/4 0/0/0 NQ 0 0 0/3/4 0/3/0 MF /0/ 0/0/ NR 0 0/3/ 0/3/ MG /0/8 0//3 NS 0 0/3/8 0/3/4 MH //4 0//0 NT 0 3 0/3/5 0/3/3 MJ // 0// NU 0 4 0/4/ 0/4/ MK 0 4 0//8 0//4 NV 0 5 0/4/8 0/4/4 ML //5 0// NW 0 6 0/4/5 0/4/ MM // 0//8 NX 0 0/4/ 0/4/8 MN //9 0//5 NY 0 8 0/4/9 0/5/5 MP 0 5 0//6 0// PA 0 9 0/5/6 0/5/ MQ 0 5 0//3 0//9 PB 0 0 0/5/3 0/5/9 MR 0 0/5/0 0/5/6 MS 0 0/5/ 0/6/ MT 0 3 0/6/3 0/6/9 MU 0 4 0/6/0 0/6/6 MV 0 5 0/6/ 0/6/3 MW 0 6 0/6/4 0/6/30 MX 0 0// 0// MY 0 8 0//8 0//4 NA 0 9 0//5 0// NB // 0//8 NC 0 3 0//9 0/8/4 ND 0 3 0/8/5 0/8/ NE /8/ 0/8/8 NF All reserved by AnSC 0 Page: 0/ V.6-04/09/9

11 Appendix (Con t) Date Code Rule Year Week Day-From Day-End Date-Code Year Week Day-From Day-End Date-Code 03 0//30 03//5 PC /8/8 03/8/4 QN 03 03//6 03// PD /8/5 03/8/3 QP //3 03//9 PE /9/ 03/9/ QQ //0 03//6 PF /9/8 03/9/4 QR // 03// PG /9/5 03/9/ QS //3 03//9 PH /9/ 03/9/8 QT 03 03//0 03//6 PJ /9/9 03/0/5 QU // 03//3 PK /0/6 03/0/ QV //4 03/3/ PL /0/3 03/0/9 QW /3/3 03/3/9 PM /0/0 03/0/6 QX 03 03/3/0 03/3/6 PN /0/ 03// QY 03 03/3/ 03/3/3 PP //3 03//9 RA /3/4 03/3/30 PQ //0 03//6 RB /3/3 03/4/6 PR // 03//3 RC /4/ 03/4/3 PS //4 03//30 RD /4/4 03/4/0 PT // 03// RE 03 03/4/ 03/4/ PU //8 03//4 RF /4/8 03/5/4 PV //5 03// RG /5/5 03/5/ PW // 03//8 RH /5/ 03/5/8 PX //9 04//4 RJ 03 03/5/9 03/5/5 PY 03 03/5/6 03/6/ QA /6/ 03/6/8 QB /6/9 03/6/5 QC /6/6 03/6/ QD /6/3 03/6/9 QE 03 03/6/30 03//6 QF // 03//3 QG //4 03//0 QH // 03// QJ //8 03/8/3 QK /8/4 03/8/0 QL /8/ 03/8/ QM All reserved by AnSC 0 Page: / V.6-04/09/9

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