Presettable 4-Bit Binary UP/DOWN Counter High-Speed Silicon-Gate CMOS

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1 TECHNICAL DATA Presettable 4-Bit Binary UP/DOWN Counter High-Speed Silicon-Gate CMOS IN74AC193 The IN74AC193 is identical in pinout to the LS/ALS193, HC/HCT193. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. The counter has two separate clock inputs, a Count Up Clock and Count Down Clock inputs. The direction of counting is determined by which input is clocked. The outputs change state synchronous with the LOW-to-HIGH traitio on the clock inputs. This counter may be preset by entering the desired data on the P, P1, P2, P3 input. When the Parallel Load input is taken low the data is loaded independently of either clock input. This feature allows the counters to be used as devide-by-n by modifying the count lenght with the preset inputs. In addition the counter can also be cleared. This is accomplished by inputting a high on the Master Reset input. All 4 internal stages are set to low independently of either clock input.both a Terminal Count Down (TC D ) and Terminal Count Up (TC U ) Outputs are provided to enable cascading of both up and down counting functio. The TC D output produces a negative going pulse when the counter underflows and TC U outputs a pulse when the counter overflows. The counter can be cascaded by connecting the TC U and TC D outputs of one device to the Count Up Clock and Count Down Clock inputs, respectively, of the next device. Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2. to 6. V Low Input Current: 1. µa; 25 C High Noise Immunity Characteristic of CMOS Devices Outputs Source/Sink 24 ma ORDERING INFORMATION IN74AC193N Plastic IN74AC193D SOIC T A = -4 to 85 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM PIN 16 =V CC PIN 8 = GND 288

2 MAXIMUM RATINGS * Symbol Parameter Value Unit V CC DC Supply Voltage (Referenced to GND) -.5 to +7. V V IN DC Input Voltage (Referenced to GND) -.5 to V CC +.5 V V OUT DC Output Voltage (Referenced to GND) -.5 to V CC +.5 V I IN DC Input Current, per Pin ± ma I OUT DC Output Sink/Source Current, per Pin ±5 ma I CC DC Supply Current, V CC and GND Pi ±5 ma P D Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Tstg Storage Temperature -65 to + C T L Lead Temperature, 1 mm from Case for Seconds (Plastic DIP or SOIC Package) 75 5 * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditio. +Derating - Plastic DIP: - mw/ C from 65 to 5 C SOIC Package: : - 7 mw/ C from 65 to 5 C mw 26 C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit V CC DC Supply Voltage (Referenced to GND) V V IN, V OUT DC Input Voltage, Output Voltage (Referenced to GND) V CC V T J Junction Temperature (PDIP) C T A Operating Temperature, All Package Types C I OH Output Current - High -24 ma I OL Output Current - Low 24 ma t r, t f Input Rise and Fall Time * (except Schmitt Inputs) * V IN from 3% to 7% V CC V CC =3. V V CC = V V CC = V 4 25 /V This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V IN and V OUT should be cotrained to the range GND (V IN or V OUT ) V CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. 289

3 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) V CC Guaranteed Limits Symbol Parameter Test Conditio V 25 C -4 C to 85 C V IH V IL V OH Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage V OUT = V or V CC - V 3. V OUT = V or V CC - V 3. I OUT -5 µa Unit V V V * V IN =V IH or V IL I OH =- ma I OH =-24 ma I OH =-24 ma V OL Maximum Low-Level Output Voltage I OUT 5 µa 3. V I IN I OLD I OHD I CC Maximum Input Leakage Current +Minimum Dynamic Output Current +Minimum Dynamic Output Current Maximum Quiescent Supply Current (per Package) * V IN =V IH or V IL I OL = ma I OL =24 ma I OL =24 ma V IN =V CC or GND ± ±1. µa V OLD =1.65 V Max 75 ma V OHD =3.85 V Min -75 ma V IN =V CC or GND 8. 8 µa * All outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2. ms, one output loaded at a time. Note: I IN and I 3. V are guaranteed to be less than or equal to the respective V V CC FUNCTION TABLE Inputs Mode MR PL CP U CP D H X X X Reset(Asyn.) L L X X Preset(Asyn.) L H H No Count L H H Count Up L H H Count Down L H H No Count X = don t care The IN74AC193 is an UP/DOWN MODULO- 16 Binary Counter. Logic equatio For Terminal Count: TC U = Q Q 1 Q 2 Q 3 CP U TC D = Q Q 1 Q 2 Q 3 CP D 29

4 AC ELECTRICAL CHARACTERISTICS(C L =5pF,Input t r =t f =3. ) V CC * Guaranteed Limits Symbol Parameter V 25 C -4 C to 85 C Unit f max Maximum Clock Frequency (Figure 1) t PLH t PHL t PLH t PHL Propagation Delay, CP U or CP D to TC U or TC D (Figure 2) Propagation Delay, CP U or CP D to TC U or TC D (Figure 2) Propagation Delay, CP U or CP D to Q n (Figure 1) Propagation Delay, CP U or CP D to Q n (Figure 1) t PLH Propagation Delay, P n to Q n (Figure 3) t PHL Propagation Delay, P n to Q n (Figure 3) t PLH Propagation Delay, PL to Q n (Figure 4) t PHL Propagation Delay, PL to Q n (Figure 4) t PHL Propagation Delay, MR to Q n (Figure 5) t PLH Propagation Delay, MR to TC U (Figure 6) t PHL Propagation Delay, MR to TC D (Figure 6) t PLH t PHL t PLH t PHL Propagation Delay, PL to TC U or TC D (Figure 6) Propagation Delay, PL to TC U or TC D (Figure 6) Propagation Delay, P n to TC U or TC D (Figure 6) Propagation Delay, P n to TC U or TC D (Figure 6) Min Max Min Max C IN Maximum Input Capacitance pf MHz C,V CC = V C PD Power Dissipation Capacitance 45 pf * Voltage Range V is V ±.3 V Voltage Range V is V ±.5 V 291

5 TIMING REQUIREMENTS(C L =5pF, Input t r =t f =3. ) V CC * Guaranteed Limits Symbol Parameter V 25 C -4 C to 85 C t su Minimum Setup Time, P n to PL (Figure 7) t h Minimum Hold Time, PL to P n (Figure 7) t w Minimum Pulse Width, PL (Figure 4) t w Minimum Pulse Width, CP U or CP D (Figure 1) t w Minimum Pulse Width, MR (Figure 5) t rec t rec Minimum Recovery Time, PL to CP U or CP D (Figure 5) Minimum Recovery Time, MR to CP U or CP D (Figure 5) * Voltage Range V is V ±.3 V Voltage Range V is V ±.5 V Unit Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms 292

6 Figure 5. Switching Waveforms Figure 6. Switching Waveforms Figure 7. Switching Waveforms TIMING DIAGRAM 293

7 EXPANDED LOGIC DIAGRAM 294

8 This datasheet has been downloaded from: Datasheets for electronic components.

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