Overview. Ripple Counter Synchronous Binary Counters


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1 Counters
2 Overview Ripple Counter Synchronous Binary Counters Design with D FlipFlops Design with JK FlipFlops Serial Vs. Parallel Counters Updown Binary Counter Binary Counter with Parallel Load BCD Counter, Arbitrary sequence Counters Counters in VHDL Chapter 5ii: Registers ( ) 2
3 Counters A counter is a register that goes through a predetermined sequence of states upon the application of clock pulses. Counters are categorized as: Ripple Counters: The FF output transition serves as a source for triggering other FFs. No common clock. Synchronous Counter: All FFs receive the common clock pulse, and the change of state is determined from the present state. Chapter 5ii: Registers ( ) 3
4 Example: A 4bit Upward Counting Ripple Counter Less Significant Bit output is Clock for Next Significant Bit! (Clock is active low) Recall... Chapter 5ii: Registers ( ) 4
5 Example (cont.) The output of each FF is connected to the C input of the next FF in sequence. The FF holding the least significant bit receives the incoming clock pulses. The J and K inputs of all FFs are connected to a permanent logic 1. The bubble next to the C label indicates that the FFs respond to the negativegoing transition of the input. Chapter 5ii: Registers ( ) 5
6 Operation: Example (cont.) The least significant bit (Q 0 ) is complemented with each negativeedge clock pulse input. Every time that Q 0 goes from 1 to 0, Q 1 is complemented. Every time that Q 1 goes from 1 to 0, Q 2 is complemented. Every time that Q 2 goes from 1 to 0, Q 3 is complemented, and so on. Chapter 5ii: Registers ( ) 6
7 A 4bit Downward Counting Ripple Counter Use direct Set (S) signals instead of direct Reset (R), in order to start at Alternative designs: Change edgetriggering to positive (details in class) Connect the complement output of each FF to the C output of the next FF in the sequence (homework!) Chapter 5ii: Registers ( ) 7
8 Using D FlipFlops Replace each JK flipflop with the above D flipflop and its corresponding combinational logic. Chapter 5ii: Registers ( ) 8
9 Synchronous Binary Counters The design procedure for a binary counter is the same as any other synchronous sequential circuit. The primary inputs of the circuit are the CLK and any control signals (EN, Load, etc). The primary outputs are the FF outputs (present state). Most efficient implementations usually use T FFs or JKFFs. We will examine JK and D flipflop designs. Chapter 5ii: Registers ( ) 9
10 Synchronous Binary Counters: JK Flip Flop Design of a 4bit Binary Up Counter Chapter 5ii: Registers ( ) 10
11 Synchronous Binary Counters: JK Flip Flop Design of a Binary Up Counter (cont.) Chapter 5ii: Registers ( ) 11
12 Synchronous Binary Counters: JK Flip Flop Design of a Binary Up Counter (cont.) Chapter 5ii: Registers ( ) 12
13 Synchronous Binary Counters: JK Flip Flop Design of a Binary Up Counter (cont.) Chapter 5ii: Registers ( ) 13
14 Synchronous Binary Counters: JK Flip Flop Design of a Binary Up Counter (cont.) logic 1 Q 0 J C K J Q0 = 1 K Q0 = 1 J C K Q 1 J Q1 = Q 0 K Q1 = Q 0 J C K Q 2 J Q2 = Q 0 Q 1 K Q2 = Q 0 Q 1 J C K Q 3 J Q3 = Q 0 Q 1 Q 2 K Q3 = Q 0 Q 1 Q 2 CLK Chapter 5ii: Registers ( ) 14
15 Synchronous Binary Counters: JK Flip Flop Design of a Binary Up Counter with EN and CO EN = enable control signal, when 0 counter remains in the same state, when 1 it counts CO = carry output signal, used to extend the counter to more stages J Q0 = 1 EN K Q0 = 1 EN J Q1 = Q 0 EN K Q1 = Q 0 EN J Q2 = Q 0 Q 1 EN K Q2 = Q 0 Q 1 EN J Q3 = Q 0 Q 1 Q 2 EN K Q3 = Q 0 Q 1 Q 2 EN C0 = Q 0 Q 1 Q 2 Q 3 EN Chapter 5ii: Registers ( ) 15
16 Synchronous binary counters using D flipflops D Q0 = Q 0 EN D Q1 = Q 1 ( Q 0 EN) D Q2 = Q 2 ( Q 0 Q 1 EN ) D Q3 = Q 3 ( Q 0 Q 1 Q 2 EN ) C0 = Q 0 Q 1 Q 2 Q 3 EN JKFF equations See Figure 511 compare with Figure 511: JKbased design calls for 4 AND gates Dbased design calls for 4 AND and 4 XOR gates Chapter 5ii: Registers ( ) 16
17 Serial Vs Parallel Counters If serial gating (chain of gates, info ripples through) is used serial counter (ex. Fig. 511a) If serial gating is replaced with parallel gating (this is analogous with ripplelogic replaced with carrylookeahead logic in our adder designs) parallel counter (ex. Fig. 511b) Advantage of parallel over serial counter: faster in certain occasions ( ) Chapter 5ii: Registers ( ) 17
18 UpDown Binary Counter clock UD nbit UpDown Counter Q 0 Q 1 Q n1 UD = 0: count up UD = 1: count down Chapter 5ii: Registers ( ) 18
19 UpDown Binary Counter (cont.) UD Q2 Q1 Q0 Q2.D Q1.D Q0.D UD Q2 Q1 Q0 Q2.D Q1.D Q0.D UpCounter DownCounter Chapter 5ii: Registers ( ) 19
20 UpDown Binary Counter (cont.) UD Q2 Q1 Q Fillin the Karnaugh maps for Q2.D, Q1.D, and Q0.D, simplify, and derive the logic diagram using (a) DFFs and (b) TFFs Chapter 5ii: Registers ( ) 20
21 Binary Counter with Parallel Load (Next slide) gives the logic diagram and symbol of a 4bit synchronous binary counter with parallel load capability. The function table for this binary counter is Load Count Operation 0 0 Nothing 0 1 Count 1 x Load Chapter 5ii: Registers ( ) 21
22 Chapter 5ii: Registers ( ) 22
23 BCD counter The binary counter with parallel load can be converted into a synchronous BCD counter by connecting an external AND gate to it. Chapter 5ii: Registers ( ) 23
24 BCD counter (cont.) The counter starts with an allzero output. As long as the output of the AND gate is 0, each positive clock pulse transition increments the counter by one. When the output reaches the count of 1001, both Q 0 and Q 3 become 1, making the output of the AND gate equal to 1. This condition makes Load active, so on the next clock transition, the counter does not count, but is loaded from its four inputs. The value loaded then is Chapter 5ii: Registers ( ) 24
25 Arbitrary Sequence Counter Given an arbitrary sequence, design a counter that will generate this sequence. Procedure: Derive state table/diagram based on give sequence Simplify (using Kmaps, etc) Draw logic diagram Example: Use DFFs to draw the logic diagram for sequence generator (counter) for: ( ) Chapter 5ii: Registers ( ) 25
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