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2 Logic Diagram 2

3 Absolute Maximum Ratings(Note 1) (Note 2) DC Supply Voltage (V DD ) 0.5V to +18 V DC Input Voltage (V IN ) 0.5V to V DD V DC Storage Temperature Range (T S ) 65 C to +150 C Power Dissipation (P D ) Dual-In-Line 700 mw Small Outline 500 mw Lead Temperature (T L ) (Soldering, 10 seconds) 260 C Recommended Operating Conditions (Note 2) DC Supply Voltage (V DD ) 3V to 15 V DC Input Voltage (V IN ) 0V to V DD V DC Operating Temperature Range (T A ) 55 C to +125 C Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. Except for Operating Temperature Range they are not meant to imply that the devices should be operated at these limits. The table of Electrical Characteristics provides conditions for actual device operation. Note 2: V SS = 0V unless otherwise specified. CD4029BC DC Electrical Characteristics (Note 2) Symbol Parameter Conditions 55 C +25 C +125 C Min Max Min Typ Max Min Max I DD Quiescent Device Current V DD = 5V V DD = 10V V DD = 15V V OL LOW Level I O < 1 µa Output Voltage V DD = 5V V DD = 10V V DD = 15V V OH HIGH Level I O < 1 µa Output Voltage V DD = 5V V DD = 10V V DD = 15V V IL LOW Level V DD = 5V, V O = 0.5V or 4.5V Input Voltage V DD = 10V, V O = 1V or 9V V DD = 15V, V O = 1.5V or 13.5V V IH HIGH Level V DD = 5V, V O = 0.5V or 4.5V Input Voltage V DD = 10V, V O = 1V or 9V V DD = 15V, V O = 1.5V or 13.5V I OL LOW Level Output V DD = 5V, V O = 0.4V Current (Note 3) V DD = 10V, V O = 0.5V V DD = 15V, V O = 1.5V I OH HIGH Level Output V DD = 5V, V O = 4.6V Current (Note 3) V DD = 10V, V O = 9.5V V DD = 15V, V O = 13.5V I IN Input Current V DD = 15V, V IN = 0V V DD = 15V, V IN = 15V Note 3: I OH and I OL are tested one output at a time. Units µa V V V V ma ma µa 3

4 AC Electrical Characteristics (Note 4) T A = 25 C, C L = 50 pf, R L = 200k, Input t rcl = t fcl = 20 ns, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units CLOCKED OPERATION t PHL or t PLH Propagation Delay Time V DD = 5V to Q Outputs V DD = 10V ns V DD = 15V t PHL or t PLH Propagation Delay Time V DD = 5V to Carry Output V DD = 10V ns V DD = 15V t PHL or t PLH Propagation Delay Time C L = 15 pf to Carry Output V DD = 5V V DD = 10V ns V DD = 15V t THL or t TLH Transition Time/Q V DD = 5V or Carry Output V DD = 10V ns V DD = 15V t WH or t WL Minimum Clock V DD = 5V Pulse Width V DD = 10V ns V DD = 15V t rcl or t fcl Maximum Clock Rise V DD = 5V 15 and Fall Time V DD = 10V 10 µs V DD = 15V 5 t SU Minimum Set-Up Time V DD = 5V V DD = 10V ns V DD = 15V f CL Maximum Clock Frequency V DD = 5V V DD = 10V MHz V DD = 15V C IN Average Input Capacitance Any Input pf C PD Power Dissipation Capacitance Per Package (Note 5) 65 pf PRESET ENABLE OPERATION t PHL or t PLH Propagation Delay Time V DD = 5V to Q output V DD = 10V ns V DD = 15V t PHL or t PLH Propagation Delay Time V DD = 5V to Carry Output V DD = 10V ns V DD = 15V t WH Minimum Preset Enable V DD = 5V Pulse Width V DD = 10V ns V DD = 15V t REM Minimum Preset Enable V DD = 5V Removal Time V DD = 10V ns V DD = 15V CARRY INPUT OPERATION t PHL or t PLH Propagation Delay Time V DD = 5V to Carry Output V DD = 10V ns V DD = 15V t PHL, t PLH Propagation Delay Time C L = 15 pf to Carry Output V DD = 5V V DD = 10V ns V DD = 15V Note 4: *AC Parameters are guaranteed by DC correlated testing. Note 5: C PD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C Family Characteristics application note, AN

5 Logic Waveforms Decade Mode CD4029BC Binary Mode 5

6 Switching Time Waveforms Cascading Packages Parallel Clocking Ripple Clocking Carry out lines at the 2nd or later stages may have a negative-going spike due to differential internal delays. These spikes do not affect counter operation, but if the carry out is used to trigger external circuitry the carry out should be gated with the clock. 6

7 Physical Dimensions inches (millimeters) unless otherwise noted CD4029BC 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M16B 7

8 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 8

9 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E CD4029BC Presettable Binary/Decade Up/Down Counter Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness

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