Automotive-grade N-channel 60 V, 21 mω typ., 32 A STripFET F6 Power MOSFET in a PowerFLAT 5x6 package. Features. Description

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1 Automotive-grade N-channel 60 V, 21 mω typ., 32 A STripFET F6 Power MOSFET in a PowerFLAT 5x6 package Datasheet - production data Features Order code VDS RDS(on) max. ID PTOT STL8N6LF6AG 60 V 27 mω 32 A 55 W Figure 1: Internal schematic diagram Designed for automotive applications and AEC-Q101 qualified Very low on-resistance Very low gate charge High avalanche ruggedness Low gate drive power loss Wettable flank package Applications Switching applications Description This device is an N-channel Power MOSFET developed using the STripFET F6 technology with a new trench gate structure. The resulting Power MOSFET exhibits very low RDS(on) in all packages. Table 1: Device summary Order code Marking Package Packing STL8N6LF6AG 8N6LF6 PowerFLAT 5x6 Tape and reel January 2016 DocID Rev 2 1/14 This is information on a product in full production.

2 Contents STL8N6LF6AG Contents 1 Electrical ratings Electrical characteristics Electrical characteristics (curves) Test circuits Package information PowerFLAT 5x6 WF type R package information PowerFLAT 5x6 WF packing information Revision history /14 DocID Rev 2

3 Electrical ratings 1 Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 60 V VGS Gate-source voltage ±20 V ID ID (1) Drain current (continuous) at Tcase = 25 C 32 Drain current (continuous) at Tcase = 100 C 23 A Drain current (continuous) at Tpcb = 25 C 9.6 Drain current (continuous) at Tpcb = 100 C 6.8 A IDM (1)(2) Drain current (pulsed) 38 A IDM (2) Drain current (pulsed) 128 A PTOT Total dissipation at Tcase = 25 C 55 PTOT Total dissipation at Tpcb = 25 C 4.8 W Tstg Tj Storage temperature -55 to 175 C Operating junction temperature Notes: (1) When mounted on a 1-inch² FR-4, 2 Oz copper board, t < 10 s. (2) Pulse width is limited by safe operating area. Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case 2.7 Rthj-pcb (1) Thermal resistance junction-pcb 31.3 C/W Notes: (1) When mounted on a 1-inch² FR-4, 2 Oz copper board, t < 10 s. Table 4: Avalanche characteristics Symbol Parameter Value Unit IAV Avalanche current, not repetitive 32 A EAS (1) Single pulse avalanche energy 120 mj Notes: (1) starting Tj = 25 C, ID = IAV, VDD = 43.5 V. DocID Rev 2 3/14

4 Electrical characteristics STL8N6LF6AG 2 Electrical characteristics (Tcase = 25 C unless otherwise specified) Table 5: Static Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 250 µa 60 V IDSS Zero gate voltage drain current VGS = 0 V, VDS = 60 V 1 µa IGSS Gate-body leakage current VDS = 0 V, VGS = ±20 V ±100 na VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µa V RDS(on) VGS = 10 V, ID = 9.6 A Static drain-source on-resistance mω VGS = 4.5 V, ID = 9.6 A Table 6: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance Coss Output capacitance VDS = 25 V, f = 1 MHz, VGS = 0 V pf Crss Reverse transfer capacitance Qg Total gate charge VDD = 30 V, ID = 9.6 A, Qgs Gate-source charge VGS = 10 V (see Figure 14: "Test circuit for gate charge nc Qgd Gate-drain charge behavior") Table 7: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time VDD = 30 V, ID = 12.5 A RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Test tr Rise time circuit for resistive load switching td(off) Turn-off delay time times" and Figure 18: "Switching ns tf Fall time time waveform") Table 8: Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current A ISDM (1) Source-drain current (pulsed) - 38 A VSD (2) Forward on voltage VGS = 0 V, ISD = 9.6 A V trr Reverse recovery time ISD = 25 A, di/dt = 100 A/µs, ns Qrr Reverse recovery charge VDD = 48 V (see Figure 15: "Test circuit for inductive nc IRRM Reverse recovery current load switching and diode recovery times") A Notes: (1) Pulse width is limited by safe operating area. (2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. 4/14 DocID Rev 2

5 Electrical characteristics 2.1 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID Rev 2 5/14

6 Electrical characteristics Figure 8: Capacitance variations STL8N6LF6AG Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Source-drain diode forward characteristics 6/14 DocID Rev 2

7 Test circuits 3 Test circuits Figure 13: Test circuit for resistive load switching times Figure 14: Test circuit for gate charge behavior Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform DocID Rev 2 7/14

8 Package information STL8N6LF6AG 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. 4.1 PowerFLAT 5x6 WF type R package information Figure 19: PowerFLAT 5x6 WF type R package outline A0Y5_ _R_WF_Rev_12 8/14 DocID Rev 2

9 Dim. Package information Table 9: PowerFLAT 5x6 WF type R mechanical data mm Min. Typ. Max. A A A b C D D D D D D e 1.27 E E E E E E E K L L ϴ 0 12 DocID Rev 2 9/14

10 Package information Figure 20: PowerFLAT 5x6 recommended footprint (dimensions are in mm) STL8N6LF6AG _FOOTPRINT_R12 10/14 DocID Rev 2

11 4.2 PowerFLAT 5x6 WF packing information Figure 21: PowerFLAT 5x6 WF tape Package information Figure 22: PowerFLAT 5x6 package orientation in carrier tape DocID Rev 2 11/14

12 Package information Figure 23: PowerFLAT 5x6 reel STL8N6LF6AG 12/14 DocID Rev 2

13 Revision history 5 Revision history Table 10: Document revision history Date Revision Changes 06-Jul First release. 07-Jan Updated title and features in cover page. Updated Section 1: "Electrical ratings", Section 2: "Electrical characteristics" and Section 4.1: "PowerFLAT 5x6 WF type R package information". DocID Rev 2 13/14

14 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document STMicroelectronics All rights reserved 14/14 DocID Rev 2

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