output=q Q input=r S 11 Advanced Digital Logic Design EECS 303 Flip-flop introduction Introduction to sequential elements Reset/set latch

Transcription

1 Advanced igital Logic esign EEC 33 Flip-flop introduction Teacher: obert ick Office: L477 Tech Phone: tores, and outputs, a value Puts a special clock signal in charge of timing Allows output to change in respoe to clock traition More on this later Timing and sequential circuits 4 obert ick Advanced igital Logic esign to sequential elements Feedback and memory Feedback and memory Memory Latches Feedback is the root of memory Can compose a simple loop from NOT gates However, there is no way to switch the value 5 obert ick Advanced igital Logic esign 6 obert ick Advanced igital Logic esign TG and NOT-based memory eset/set latch Can break feedback path to load new value However, potential for timing problems 7 obert ick Advanced igital Logic esign 9 obert ick Advanced igital Logic esign eset/set timing latch state diagram eset Hold et eset et ace Utable state Utable state output= input= obert ick Advanced igital Logic esign obert ick Advanced igital Logic esign

2 Clocking terms Gated latch Input Clock Clock ising edge, falling edge, high level, low level, period etup time: Minimum time before clocking event by which input must be stable (T U ) Hold time: Minimum time after clocking event for which input must remain stable (T H ) Window: From setup time to hold time ENB 2 obert ick Advanced igital Logic esign 3 obert ick Advanced igital Logic esign Gated latch Memory element properties ENB Type Inputs sampled Outputs valid Unclocked latch Always LFT Level-seitive latch Clock high LFT (TU to TH) around falling clock edge Edge-triggered flip-flop Clock low-to-high traition elay from rising edge (TU to TH) around rising clock edge 4 obert ick Advanced igital Logic esign 5 obert ick Advanced igital Logic esign Timing for edge and level-seitive latches Active high traparent CLK Active low traparent CLK Clk Positive (rising) edge CLK Negative (falling) edge CLK edge level 7 obert ick Advanced igital Logic esign 8 obert ick Advanced igital Logic esign Latch timing specificatio Latch timing specificatio Example, negative (falling) edge-triggered flip-flop timing diagram Minimum clock width, T W Usually period / 2 Low to high propegation delay, P LH High to low propegation delay, P HL Worst-case and typical Clk 2 T w 2 T plh C» T phl C» T plh» 27 5 T phl» obert ick Advanced igital Logic esign 2 obert ick Advanced igital Logic esign

3 FF timing specificatio FF timing specificatio Example, positive (rising) edge-triggered flip-flop timing diagram Minimum clock width, T W Usually period / 2 Low to high propagation delay, P LH High to low propagation delay, P HL Clk 2 5 T w 25 T plh T phl obert ick Advanced igital Logic esign 22 obert ick Advanced igital Logic esign latch states JK latch + + Notes utable latch Use output feedback to eure that + = K + J 23 obert ick Advanced igital Logic esign 24 obert ick Advanced igital Logic esign JK latch JK race J K + hold reset set toggle et eset Toggle ace Condition 25 obert ick Advanced igital Logic esign 26 obert ick Advanced igital Logic esign Falling edge-triggered Falling edge-triggered Use two stages of latches When clock is high First stage samples input w.o. changing second stage econd stage holds value When clock goes low First stage holds value and sets or resets second stage econd stage tramits first stage + = One of the most commonly used flip-flops Clk= = Clock high 28 obert ick Advanced igital Logic esign 29 obert ick Advanced igital Logic esign

4 Falling edge-triggered Falling edge-triggered Holds when clock goes low Clk== Clk= = Holds when clock goes low Clock switching Inputs sampled on falling edge, outputs change after falling edge? Clock low 3 obert ick Advanced igital Logic esign 3 obert ick Advanced igital Logic esign Edge triggered timing clocked latch Positive edge t riggered FF torage element in narrow width clocked systems angerous Fundamental building block of many flip-flop types Negative edge t riggered FF 32 obert ick Advanced igital Logic esign 33 obert ick Advanced igital Logic esign JK flip-flop Versatile building block Building block for and T flip-flops Has two inputs resulting in increased wiring complexity on t use master/slave JK flip-flops Ones or zeros catching Edge-triggered varieties exist Minimizes input wiring imple to use Common choice for basic memory elements in sequential circuits 34 obert ick Advanced igital Logic esign 35 obert ick Advanced igital Logic esign Toggle (T) flip-flops Asynchronous inputs tate changes each clock tick Useful for building counters Can be implemented with other flip-flops JK with inputs high with XO feedback How can a circuit with numerous distributed edge-triggered flip-flops be put into a known state Could devise some sequence of input events to bring the machine into a known state Complicated low Not necessarily possible, given trap states Can also use sequential elements with additional asynchronous reset and/or set inputs 36 obert ick Advanced igital Logic esign 37 obert ick Advanced igital Logic esign

5 Latch and flip-flop equatio Latch and flip-flop equatio + = + + = JK T + = J + K + = T 38 obert ick Advanced igital Logic esign 39 obert ick Advanced igital Logic esign equential FM design example We ll walk through the design of an example finite state machine (FM) ome of the stages will be covered in more detail in later lectures I want you to have a high-level understanding of our overall goal before covering every detail of FM synthesis Naturally express control However, no simple direct HW implementation We want to get to sequential logic Need to go though other stages first 42 obert ick Advanced igital Logic esign 43 obert ick Advanced igital Logic esign (NFA) Can be expressed with regular expressio, examples Accept the empty string, Accept nothing, Accept or, ( + ) Accept anything starting with and one or more and ending with or, + ( + ) Accept anything starting with zero or more or and ending with, ( + ) tate graph Multiple states can be active at the same time ome states Accept The automata accepts if any accepting states are active 44 obert ick Advanced igital Logic esign 46 obert ick Advanced igital Logic esign NFA (FA) (++)() + a b c d e f g h i j k NFAs require multiple states to be simultaneously active Can t represent this with conventional logic state variables Need to convert to deterministic representation 47 obert ick Advanced igital Logic esign 49 obert ick Advanced igital Logic esign

6 FA FA to more explicit FM a b f (++)() + c d e i g h d ei cj ki j abfi g hi j k (++)() + z d ei cj ki j abfi g hi 5 obert ick Advanced igital Logic esign 5 obert ick Advanced igital Logic esign FA to FM Moore block diagram outputs combinational logic FA may only accept or reject imple to convert Moore FM Add explicit output values to states sequential elements feedback combinational logic inputs 53 obert ick Advanced igital Logic esign 54 obert ick Advanced igital Logic esign Mealy block diagram Moore FMs outputs sequential elements feedback A/ B/ combinational logic inputs / C/ 55 obert ick Advanced igital Logic esign 56 obert ick Advanced igital Logic esign to state reduction to state reduction s + s A A B B C B C A B A A s + s q AC AC B B AC B AC AC 58 obert ick Advanced igital Logic esign 59 obert ick Advanced igital Logic esign

7 tate assignment tate variable functio s + s q ABC ABC ABC ABC ABC Only two adjacent states, state assignment is trivial However, good to coider output, q s + s q s + (s) = q(s) = s 6 obert ick Advanced igital Logic esign 6 obert ick Advanced igital Logic esign Mealy FMs Mealy tabular form / / A /X / / / B / / C s + /q s A / B/X B C/ B/ C A/ B/ C/ C/ 62 obert ick Advanced igital Logic esign 63 obert ick Advanced igital Logic esign Mealy to Moore conversion tate variable combinational synthesis / / A /X B / / / / C / clock flip flops A/ B/X B/ q plain old combinational logic / C/ B/ C/ eparate sequential and combinational portio of circuit Conduct standard logic synthesis 64 obert ick Advanced igital Logic esign 65 obert ick Advanced igital Logic esign FM design summary ecommended reading pecify requirements in natural form regular expression or NFA Converting from NFA to FA is straightforward Converting from FA to FM is straightforward Minimize the number of states using compatible states, class sets, and binate covering Assign values to states to minimize logic complexity Allow only adjacent or path traitio for asynchronous machines Optimize implementation of state and output functio M. Morris Mano and Charles. Kime. Logic and Computer esign Fundamentals. Prentice-Hall, NJ, third edition, 24 Chapter 7 Chapter 6 66 obert ick Advanced igital Logic esign 68 obert ick Advanced igital Logic esign

8 Video controller repair lab Next lecture esign a finite state machine based on an English problem specification The design problem isn t very difficult Going from a real-world problem to a formal representation may be difficult Be careful not to use too many state variables!!! Could easily turn it from a 6 hour lab to a 2 hour lab More detail and examples on FM design and optimization 69 obert ick Advanced igital Logic esign 7 obert ick Advanced igital Logic esign