Single-Cycle Performance

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Derek Mills
7 years ago
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1 Lectre 9

2 Single-Cycle Performance Last time we saw a IPS single-cycle path and control nit. Today, we ll eplore factors that contribte to a processor s eection time, and specifically at the performance of the single-cycle machine. Net time, we ll eplore how to improve on the single cycle machine s performance sing pipelining.

3 Three Components of CPU Performance CPU time X,P = Instrctions eected P * CPI X,P * Clock cycle time X Cycles Per Instrction

4 Instrctions eected: Instrctions Eected We are not interested in the static instrction cont, or how many lines of code are in a program. Instead we care abot the dynamic instrction cont, or how many instrctions are actally eected when the program rns. There are three lines of code below, bt the nmber of instrctions eected wold be 2. li $a, Ostrich: sb $a, $a, bne $a, $, Ostrich

5 CPI The average nmber of clock cycles per instrction, or CPI, is a fnction of the machine and program. The CPI depends on the actal instrctions appearing in the program a floating-point intensive application might have a higher CPI than an integer-based program. It also depends on the CPU implementation. For eample, a Pentim can eecte the same instrctions as an older 8486, bt faster. So far we assmed each instrction took one cycle, so we had CPI =. The CPI can be > de to stalls and slow instrctions. The CPI can be < on machines that eecte more than instrction per cycle (sperscalar).

6 Clock cycle time One cycle is the minimm time it takes the CPU to do any work. The clock cycle time or clock period is jst the length of a cycle. The clock rate, or freqency, is the reciprocal of the cycle time. Generally, a higher freqency is better. Some eamples illstrate some typical freqencies. A 5Hz processor has a cycle time of 2ns. A 2GHz (2Hz) CPU has a cycle time of jst.5ns (5ps).

7 Eection time, again CPU time X,P = Instrctions eected P * CPI X,P * Clock cycle time X The easiest way to remember this is match p the nits: Seconds Instrctions Clock cycles Seconds = * * Program Program Instrctions Clock cycle ake things faster by making any component smaller!! Instrction Eected CPI Clock Cycle TIme Program Compiler ISA Organization Technology Often easy to redce one component by increasing another

8 Eample : ISA-compatible processors Let s compare the performances two 86-based processors. An 8Hz AD Dron, with a CPI of.2 for an P3 compressor. A GHz Pentim III with a CPI of.5 for the same program. Compatible processors implement identical instrction sets and will se the same eectable files, with the same nmber of instrctions. Bt they implement the ISA differently, which leads to different CPIs. CPU time AD,P = Instrctions P * CPI AD,P * Cycle time AD = = CPU time P3,P = Instrctions P * CPI P3,P * Cycle time P3 = =

9 How the add goes throgh the path PC+4 PC 4 Add Reg Shift left 2 Add PCSrc Instrction [3-] Instrction I [25-2] I [2-6] I [5 - ] RegDst register register 2 register 2 Registers ALUSrc ALU Zero Reslt ALUOp em Data em emtoreg I [5 - ] Sign etend... 2

10 Performance of Single-cycle Design CPU time X,P = Instrctions eected P * CPI X,P * Clock cycle time X

11 Edge-triggered state elements In an instrction like add $t, $t, $t2, how do we know $t is not pdated ntil after its original vale is read? We ll assme that or state elements are positive edge triggered, and are pdated only on the positive edge of a clock signal. The register file and have eplicit write control signals, Reg and em. These nits can be written to only if the control signal is asserted and there is a positive clock edge. In a single-cycle machine the PC is pdated on each clock cycle, so we don t bother to give it an eplicit write control signal. register register 2 register Reg em 2 Registers Data em PC

12 The path and the clock. On a positive clock edge, the PC is pdated with a new. 2. A new instrction can then be loaded from. The control nit sets the path signals appropriately so that registers are read, ALU otpt is generated, is read or written, and branch target es are compted. 3. Several things happen on the net positive clock edge. The register file is pdated for arithmetic or lw instrctions. Data is written for a sw instrction. The PC is pdated to point to the net instrction. In a single-cycle path everything in Step 2 mst complete within one clock cycle, before the net positive clock edge. How long is that clock cycle?

13 Compte the longest path in the add instrction PC+4 PC Instrction [3-] Instrction 4 I [25-2] I [2-6] I [5 - ] Add RegDst register register 2 register Reg ns 2 Registers Shift left 2 ALUSrc Add ALU Zero Reslt ALUOp PCSrc ns em Data em emtoreg ns I [5 - ] ns ns Sign etend

14 The slowest instrction... If all instrctions mst complete within one clock cycle, then the cycle time has to be large enogh to accommodate the slowest instrction. For eample, lw $t, 4($sp) is the slowest instrction needing ns. Assming the circit latencies below. Instrction [3-] Instrction I [25-2] I [2-6] I [5 - ] I [5 - ] ns register register 2 register ns 2 Registers Sign etend ns ns ALU Zero Reslt Data ns

15 The slowest instrction... If all instrctions mst complete within one clock cycle, then the cycle time has to be large enogh to accommodate the slowest instrction. For eample, lw $t, 4($sp) needs 8ns, assming the delays shown here. reading the instrction reading the base register $sp compting $sp-4 reading the storing back to $t 2ns ns 2ns 2ns ns 8ns Instrction [3-] Instrction I [25-2] I [2-6] I [5 - ] I [5 - ] ns register register 2 register ns 2 Registers Sign etend ns ns ALU Zero Reslt Data ns

16 ...determines the clock cycle time If we make the cycle time 8ns then every instrction will take 8ns, even if they don t need that mch time. For eample, the instrction add $s4, $t, $t2 really needs jst 6ns. reading the instrction reading registers $t and $t2 compting $t + $t2 storing the reslt into $s ns ns 6 ns Instrction [3-] Instrction I [25-2] I [2-6] I [5 - ] I [5 - ] ns register register 2 register ns 2 Registers Sign etend ns ns ALU Zero Reslt Data ns

17 How bad is this? With these same component delays, a sw instrction wold need 7ns, and beq wold need jst 5ns. Let s consider the gcc instrction mi from p. 89 of the tetbook. Instrction Freqency Arithmetic 48% Loads 22% Stores % Branches 9% With a single-cycle path, each instrction wold reqire 8ns. Bt if we cold eecte instrctions as fast as possible, the average time per instrction for gcc wold be: (48% 6ns) + (22% 8ns) + (% 7ns) + (9% 5ns) = 6.36ns The single-cycle path is abot.26 times slower!

18 It gets worse... We ve made very optimistic assmptions abot latency: ain accesses on modern machines is >5ns. For comparison, an ALU on an AD Opteron takes ~.3ns. Or worst case cycle (loads/stores) incldes 2 accesses A modern single cycle implementation wold be stck at <hz. Caches will improve common case access time, not worst case. Tying freqency to worst case path violates first law of performance!! ake the common case fast (we ll revisit this often)

19 Smmary Performance is one of the most important criteria in jdging systems. Here we ll focs on Eection time. Or main performance eqation eplains how performance depends on several factors related to both hardware and software. CPU time X,P = Instrctions eected P * CPI X,P * Clock cycle time X It can be hard to measre these factors in real life, bt this is a sefl gide for comparing systems and designs. A single-cycle CPU has two main disadvantages. The cycle time is limited by the worst case latency. It isn t efficiently sing its hardware. Net time, we ll see how this can be rectified with pipelining.

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