Frequency Synthesizer Architecture Design for DRM and DAB Receiver

Transcription

1 Progress In Electromagnetics Research Symposium, Hangzhou, China, March 24-28, Frequency Synthesizer Architecture Design for DRM and DAB Receiver Jianzheng Zhou 1,2 and Zhigong Wang 1 1 Institute of RF- & OE-ICs, Southeast University, Nanjing, China 2 School of Computer & Information, Hefei University of Technology, Hefei, China Abstract Based on the specifications of DRM/DAB receivers, 4 synthesizer structures were designed for the receiver which supports several radio standards including AM, DRM, FM, and DAB. Comparisons of the characteristics of the four structures were given. Analysis and calculations prove that the synthesizer structure 1 with a single VCO and a single loop filter is the most suitable one to be used in the DRM/DAB receivers with good performance in phase noise, reference spurs and lock time, at expense of little more power consumption. 1. INTRODUCTION A DRM/DAB receiver will need to support several radio standards including AM, DRM, FM, and DAB, and needs to provide the necessary flexibility for seamless receive. A key challenge in the full integration of such a DRM/DAB receiver is the design and implementation of its beating heart, i.e., the reconfigurable frequency synthesizer which acts as the local oscillator (LO) and covers all the frequency bands of the considered standards. This is due to the difficulty in meeting the performance requirements with on-chip components because of the diverse standards it needs to support. It is also due to the simulation of the synthesizer, a task that requires mixed-signal tools that should provide radio frequency, analog, and digital perspectives. We have proved that a double-conversion low-if structure is the most suitable architecture for the DRM/DAB receiver, and the first intermediate frequency (f IF1 ) is MHz and f IF2 is 2 MHz for DAB, 175 khz for other bands in this system. The receiver needs two quadrature LO signals, the first one is generated by a synthesizer and the second one is a fixed frequency, which is easy to be generated. So, only the synthesizer which generates the first quadrature LO is discussed in this work. 2. DESIGN SPECIFICATIONS Some of the main design specifications and considerations are given as follows Output Frequency Range and Resolution The output frequency range and resolution of the frequency synthesizer are listed in Table 1. Table 1: The output frequency range and resolution. Band Output frequency range (MHz) Resolution (khz) LF MF HF FM III band L band Phase Noise and Spurious Frequencies Numerical stipulation of phase noise for this design, a typical value of 80 khz is chosen. Generally speaking, all sidebands need to be approximately 70 to 80 db below the main carrier Switching Time Initial design switching time of less than 100 ms is aimed. Furthermore, generation of quadrature LO-signals is mandatory for low-if receiver architecture.

2 60 PIERS Proceedings, Hangzhou, China, March 24-28, FREQUENCY SYNTHESIZER ARCHITECTURE DESIGN [1] Since a direct analog frequency synthesizer (DAS) or a direct digital frequency synthesizer (DDFS or DDS) can provide an arbitrarily small frequency step size, at expense of higher complexity, higher dissipation and a larger die area, and thus they are often not suitable for DRM/DAB receivers, the charge-pump phase locked loop (PLL) frequency synthesizer is widely adopted. To address different application requirements, there are several PLL synthesizer architectures, such as fractional-n architecture, dual-loop architecture, or integer-n architecture. Each has advantages and drawbacks, depending upon the application. The Fractional-N PLL architecture enables a PLL synthesizer to generate output frequencies with a step size smaller than the reference frequency. But, it suffers from fractional spurs which degrade the spurious-tone performance. In Multi-Loop PLL Synthesizer [2 4], the basic idea of it is that spectral purity can be separated from the minimum step size specification, with the small tuning step requirement being satisfied with the addition of a second loop to the tuning system. This architecture can improve the tradeoff among phase noise, channel spacing, reference frequency, and locking speed of the synthesizer. Although more circuits are needed, the specifications for each building block are much relaxed [5]. Despite the advance of fractional-n or multi-loop PLL architectures, Integer-N architectures are still the most popular synthesizer architectures used in the industry due to its simple architecture, easy implementation, high reliability, low power, and low-cost in terms of design time. The basic limitation is the fact that the reference frequency is equal to the minimum step size of the PLL, which can lead to quite a few drawbacks including: (a) large division ratios increased area and power, (b) low bandwidth large lock times, and (c) reference spurious tones. So, conventional single-loop PLL synthesizers are not able to combine the requirements of small step size, good spectral purity, and wide loop bandwidth [3]. While in single-loop integer-n PLL Synthesizer with a divider shown in Fig. 1 [6 8], an additional frequency divider X is placed at the output of the VCO to allow for smaller frequency steps than the loop s reference frequency and improve the lock time, phase noise, and reference spurs. f PFD f VCO PFD/CP LPF VCO X Nf REF f DIV N Figure 1: Single-loop integer-n PLL synthesizer with divider. To address all these needs, 4 frequency synthesizer architectures are given in the following sections Synthesizer Structure 1 The frequency synthesizer architecture 1 given in Fig. 2 has been defined such that all reception bands can be accessed with a single VCO and a single loop filter. The VCO covers the band from 2600 to 3120 MHz. Mapping the frequency of the VCO to the different input bands is achieved by dividing its output frequency by different ratios, depending on the band to be received. A divide-by-2 and -4 circuits are included to generate the desired quadrature LO frequencies. Table 2 presents the frequency synthesizer parameter settings for various reception bands. In this configuration, f OUT = (f PFD N)/X. Some consequences for this architecture are given as follows. a) The minimum step size is indeed smaller than f PFD. REF DIV PFD/CP LPF VCO 1/5/6 /7/8 Main DIV 2/4/8/ 10/12 Figure 2: Synthesizer structure 1.

3 Progress In Electromagnetics Research Symposium, Hangzhou, China, March 24-28, Table 2: Reception bands with corresponding synthesizer Parameters [7]. Band (MHz) LO (MHz) X1 X2 f PFD (khz) LF: MF: HF: FM: III band: L band: b) Compared to the use of the standard integer-n architecture, the phase noise performance of this kind of synthesizer is optimized by 10 log(x) at the LO output. c) Reference spurs reduction: In this architecture, at f OUT, the spurious frequencies still exist at the integer multiples of the PFD frequency but they are reduced in amplitude by 20 log(x). d) Shorter lock time due to higher PFD frequency. The price of this improved performance is the extra cost of the output divider and the extra power consumption of the system as a whole. Thus, the improved performance must be a critical requirement for selecting this architecture Synthesizer Structure 2 Synthesizer structure 2 is shown in Fig. 3. This structure is similar to structure 1, except that f PDF, f VCO, and X is one half of these in structure 1. In other words, f VCO is divided by 40 for LF and MF bands, by 36, 32, 28, or 24 for HF band, by 12 or 10 for FM band, by 7, 6 or 5 for III band, and by 1 for L band. When X is odd number, path I is chosen, in this case a poly-phase filter (PPF) is used to generate the desired I/Q LO frequencies. When X is an even number, path II or III is chosen, a divide-by-2 circuits are included to generate the desired quadrature LO frequencies. REF DIV PFD/CP LPF VCO 1/5/7 Path II 6/8 Path I PPF Main DIV Path III 2/4/ 6/8 Figure 3: Synthesizer structure Synthesizer Structure 3 Synthesizer structure 3 is shown in Fig. 4 [9]. This structure is also similar to structure 1, but f PDF, f VCO, and X is one fourth of the counterpoint in stucture 1. In other words, the VCO covers 650 to 780 MHz, and divided by 20 for LF and MF bands, by 18, 16, 14, or 12 for HF band, by 6 or 5 for FM band, by 3.5, 3 or 2.5 for III band, and by 0.5 for L band. When X is a fraction number, such as 0.5, 2.5, and 3.5, path I is chosen. In this case the Delay-Locked loop (DLL) combines the functions of frequency multiplication and quadrature generation. It consists of a DLL with 2N

4 62 PIERS Proceedings, Hangzhou, China, March 24-28, 2008 tunable delay cells that can multiply the frequency of the incoming signal with a factor N, while also generating the quadrature LO-signals [10]. When X is an odd number, path I is used, but the DLL is used to generate the desired I/Q LO frequencies only. When X is an even number, path II is chosen, in which a divide-by-2 circuits are included to generate the desired quadrature LO frequencies. REF DIV PFD/ CP LPF VCO Main DIV 1/3/ 4/ 5/7 2/4/6 Path II DLL with 4 Delay Cells Path I Figure 4: Synthesizer structure Synthesizer Structure 4 Another alternative solution is to use a dual-loop architecture shown in Fig. 5. Table 3 presents the VCO frequency and frequency synthesizer parameter settings for various reception bands. The VCO1 covers 37 to 1529 MHz. f REF1 PFD/CP LPF VCO 1 PLL 1 M SSB Mixer LO-I LO-Q f REF2 PFD/CP LPF VCO 2 X PLL 2 N Figure 5: Synthesizer structure. Table 3: VCO frequency and frequency synthesizer parameter settings for various reception bands. Band f REF1 (MHz) M X N f VCO2 (MHz) LF HF HF FM III band L band Comparison of These 4 Synthesizer Structures The total phase noise in a phase locked loop (db) can be expressed as follows [6]: P N tot = P N floor + 20 log N + 10 log f REF 20 log X (1) where, P N tot is the total phase noise of the synthesizer, f REF is the incoming PFD frequency of the synthesizer, P N floor is the phase noise due to the PLL synthesizer circuit itself. This provides

5 Progress In Electromagnetics Research Symposium, Hangzhou, China, March 24-28, a figure of merit for the PLL synthesizer circuit itself. For ADF4106, this figure is 219 khz. 20 log N is the increase of phase noise due to the frequency magnification associated with the feedback ratio, 1/N. 20 log X is the improvement of phase noise due to the division with the divider ratio, 1/X. On the other hand, the spurious frequencies exist at the integer multiples of the PFD frequency, and they are reduced in amplitude by 20 log X. Furthermore, shorter lock time due to higher PFD frequency. So the phase noise of structure 1 is 3 db, 6 db better than the counterpart of structure 2 and structure 3 respectively. And the reference spurs of structure 1 is 6 db, 12 db better than the counterpart of structure 2 and structure 3, respectively. And the lock time is much shorter than structure 2 and structure 3. The f VCO of Structure 1 is two and four times of that of the structure 2 and 3, respectively, it needs more power consumption. However, it easier to implement on-chip than that of Structure 2 and 3. Moreover, Structure 2 and 3 need extra PPF or DLL to generate the quadrature LO signals, so they need a more complex circuit, a larger chip area and even more power consumption. The phase noise, reference spurs and lock time of Structure 4 maybe better than these of other structures, at expense of higher complexity and a larger die area. Especially, the tunable frequency range of VCO 1 and VCO 2 is too large to implement on-chip, and VCO 1 need output quadrature LO signals, and the performance of synthesizer also lies on the perfect single side-band mixer. So this design is not the best solution for DRM/DAB receivers synthesizer. Based on the analyses given above, we can know that the synthesizer structure 1 is the most suitable one for DRM/DAB receiver. 4. PERFORMANCE ANALYSIS OF THE SYNTHESIZER STRUCTURES Suppose that the P N floor of the PLL is better than 210 khz, we can obtain the performance of the synthesizer structure 1, which is given in Table 4, based on the formula (1) and the experiential formula that the switch time t sw < 25/f PFD. Band Table 4: The performance of synthesizer structure 1. Step Size (khz) Phase noise (dbc/hz@1 khz) Ref. spur Reduction (db) Switch Time (ms) LF 3 < < 0.1 MF 1 < < 0.3 HF 5 < 107 > 33.6 < 0.1 FM 25 < 103 > 26 < 0.05 III band 64 < 99 > 20 < 0.04 L band 64 < < CONCLUSIONS In the quest for true reconfigurable DRM/DAB receiver, four frequency synthesizer architectures are given, enabling the generation of quadrature LO signals over extremely wide frequency ranges. Theoretical analysis shows that structure 1 will be the best one to be used with good performance in phase noise, reference spurs and lock time, at expense of little more power consumption. As we can see from the Table 4, synthesizer structure 1 can meet the design specification, is very suitable for DRM/DAB receivers, need few external components and require no mechanical alignments. REFERENCES 1. Sinha, S., Design of an integrated CMOS PLL frequency synthesizer, Proceedings of 11th Mediterranean Electrotechnical Conference, MELECON 2002, , 7 9 May Leenarts, D. M. W. and C. S. Vaucher, Frequency synthesizers for RF transceivers, Proceedings of the 2003 Bipolar/BiCMOS Circuits and Technology Meeting, , Sept Vaucher, C. and D. Kasperkovitz, A wide-band tuning system for fully integrated satellite receivers, IEEE Journal of Solid-State Circuits, Vol. 33, No. 7, , July 1998.

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