ESE 345 Computer Architecture Virtual Memory and Translation Look-Aside Buffers Virtual Memory

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1 Computer Architecture ESE 345 Computer Architecture and Translation Look-Aside Buffers 1

2 The Limits of Physical Addressing Physical addresses of memory locations A0-A31 CPU D0-D31 A0-A31 Memory D0-D31 Data All programs share one address space: The physical address space Machine language programs must be aware of the machine organization No way to prevent a program from accessing any machine resource 2

3 Use main memory as a cache for secondary (disk) storage Managed jointly by CPU hardware and the operating system (OS) Programs share main memory Each gets a private virtual address space holding its frequently used code and data Protected from other programs CPU and OS translate virtual addresses to physical addresses VM block is called a page VM translation miss is called a page fault 3

4 Three Advantages of Translation: Program can be given consistent view of memory, even though physical memory is scrambled Makes multithreading reasonable (now used a lot!) Only the most important part of program ( Working Set ) must be in physical memory. Contiguous structures (like stacks) use only as much physical memory as necessary yet still grow later. Protection: Different threads (or processes) protected from each other. Different pages can be given special behavior (Read Only, Invisible to user programs, etc). Kernel data protected from User programs Very important for protection from malicious programs Sharing: Can map same physical page to multiple users ( Shared memory ) 4

5 Page tables encode virtual address spaces virtual address Page Table (One per ASID) Physical Memory Space frame frame frame frame A virtual address space is divided into blocks of memory called pages A machine usually supports pages of a few sizes (MIPS R4000): OS manages the page table for each ASID A page table is indexed by a virtual address A valid page table entry codes physical memory frame address for the page 5

6 Paged virtual memory Virtual Address Space Physical Address Space Virtual Address V page no. 10 offset Page Table Base Reg index into page table Page Table V Access Rights Virtual memory => treat memory as a cache for the disk Terminology: blocks in this cache are called Pages Typical size of a page: 1K 8K Page table maps virtual page numbers to physical frames PTE = Page Table Entry PA table located in physical memory P page no. offset 10 Physical Address 6

7 Mapping Pages to Storage with Page Tables Page table stores placement information Array of page table entries, indexed by virtual page number Page table register in CPU points to page table in physical memory If page is present in memory PTE stores the physical page number Plus other status bits (referenced, dirty, ) If page is not present PTE can refer to location in swap space on disk 7

8 Large Address Space Support Virtual Address: 10 bits 10 bits 12 bits Offset Virtual P1 index Virtual P2 index Physical Address: Physical Page # Offset 4KB PageTablePtr 4 bytes Single-Level Page Table Large 4KB pages for a 32-bit address 1M entries Each process needs own page table! Multi-Level Page Table Can allow sparseness of a page table Portions of a table can be swapped to disk 4 bytes 8

9 What is in a Page Table Entry (PTE)? What is in a Page Table Entry (or PTE)? Pointer to next-level page table or to actual page Permission bits: valid, read-only, read-write, write-only Example: Intel x86 architecture PTE: Address same format previous slide (10, 10, 12-bit offset) Intermediate page tables called Directories Page Frame Number (Physical Page Number) Free (OS) 0 L D A PWT PCD U W P P: Present (same as valid bit in other architectures) W: Writeable U: User accessible PWT: Page write transparent: external cache write-through PCD: Page cache disabled (page cannot be cached) A: Accessed: page has been accessed recently D: Dirty (PTE only): page has been modified recently L: L=1 4MB page (directory only). 0 9

10 Page Fault Penalty On page fault, the page must be fetched from disk Takes millions of clock cycles Handled by OS code Try to minimize page fault rate Fully associative placement Smart replacement algorithms 10

11 Page Fault Handler Use faulting virtual address to find PTE Locate page on disk Choose page to replace If dirty, write to disk first Read page into memory and update page table Make process runnable again Restart from faulting instruction 11

12 Replacement and Writes To reduce page fault rate, prefer least-recently used (LRU) replacement Reference bit (aka use bit) in PTE set to 1 on access to page Periodically cleared to 0 by OS A page with reference bit = 0 has not been used recently Disk writes take millions of cycles Block at once, not individual locations Write through is impractical Use write-back Dirty bit in PTE set when page is written 12

13 Clock Algorithm: Not Recently Used Set of all pages in Memory Clock Algorithm: Approximate LRU Replace an old page, not the oldest page Details: Hardware use bit per physical page: Hardware sets use bit on each reference If use bit isn t set, means not referenced in a long time On page fault: Advance clock hand (not real time) Check use bit: 1 used recently; clear and leave alone 0 selected candidate for replacement Single Clock Hand: Advances only on page fault! Check for pages not used recently Mark pages as not used recently dirty used Page Table... 13

14 Memory Protection Different tasks can share parts of their virtual address spaces But need to protect against errant access Requires OS assistance Hardware support for OS protection Privileged supervisor mode (aka kernel mode) Privileged instructions Page tables and other state information only accessible in supervisor mode System call exception (e.g., syscall in MIPS) 14

15 MIPS R4000: Address Space Model Process A 0 Address Error 2 GB ASID = Address Space Identifier Process B Process A and B have independent ASID = 12 ASID = 13 address spaces All address spaces translated to standard map May only be accessed by kernel/supervisor When Process A writes its address 9, it writes to a different physical memory location than Process B s address 9 To let Process A and B share memory, OS maps parts of ASID 12 and ASID 13 to the same physical memory locations. Still works (slowly!) if a process accesses more virtual memory than the machine has physical memory 0 Address Error 2 GB 15

16 Fast Translation Using a TLB Address translation would appear to require extra memory references One to access the PTE Then the actual memory access But access to page tables has good locality So use a fast cache of PTEs within the CPU Called a Translation Look-aside Buffer (TLB) Typical: PTEs, cycle for hit, cycles for miss, 0.01% 1% miss rate Misses could be handled by hardware or software 16

17 Fast Translation Using a TLB 17

18 Translation Look-Aside Buffers Translation Look-Aside Buffers (TLB) Cache on translations Fully Associative, Set Associative, or Direct Mapped hit VA PA miss CPU TLB Cache Main Memory Translation with a TLB miss Translation hit TLBs are: data Small typically not more than entries Fully Associative in general although can be n-way Set Associative as well 18

19 Caching Applied to Address Translation CPU Virtual Address TLB Cached? Yes No Physical Address Physical Memory Translate (MMU) Data Read or Write (untranslated) Can we have a TLB hierarchy? Sure: multiple levels at different sizes/speeds 19

20 Example: R3000 Pipeline MIPS R3000 Pipeline Inst Fetch Dcd/ Reg ALU / E.Addr Memory Write Reg TLB I-Cache RF Operation WB ASID V. Page Number Offset E.Addr TLB D-Cache TLB 64 entry, on-chip, fully associative, software TLB fault handler Virtual Address Space 0xx User segment (caching based on PT/TLB entry) 100 Kernel physical space, cached 101 Kernel physical space, uncached 11x Kernel virtual space Allows context switching among 64 user processes without TLB flush 20

21 MIPS R4000 TLB: A closer look... Checked against CPU ASID A0-A31 CPU D0-D31 Virtual Addresses Data Virtual Physical Translation Look-Aside Buffer (TLB) Physical Addresses A0-A31 Memory System D0-D31 Physical space larger than virtual space! 21

22 What Actually Happens on a TLB Miss? Hardware traversed page tables: On TLB miss, hardware in MMU looks at current page table to fill TLB (may walk multiple levels) If PTE valid, hardware fills TLB and processor never knows If PTE marked as invalid, causes Page Fault, after which kernel decides what to do afterwards Software traversed Page tables (like MIPS) On TLB miss, processor receives TLB fault Kernel traverses page table to find PTE If PTE valid, fills TLB and returns from fault If PTE marked as invalid, internally calls Page Fault handler Most chip sets provide hardware traversal Modern operating systems tend to have more TLB faults since they use translation for many things Examples: shared segments user-level portions of an operating system 22

23 Reducing translation time further As described, TLB lookup is in serial with cache lookup: Virtual Address V page no. 10 offset TLB Lookup V Access Rights PA P page no. offset 10 Physical Address Machines with TLBs go one step further: they overlap TLB lookup with cache access. Works because offset available early 23

24 Overlapping TLB & Cache Access Here is how this might work with a 4K cache: 32 TLB assoc lookup index 4K Cache 1 K Hit/ Miss 20 page # Physical Frame Number (PFN) What if cache size is increased to 8KB? Overlap not complete Need to do something else (next slide) Another option: Virtual Caches Tags in cache are virtual addresses 10 2 disp 00 Translation only happens on cache misses = 4 bytes PFN Data Hit/ Miss 24

25 Problems With Overlapped TLB Access Overlapped access requires address bits used to index into cache do not change as result translation This usually limits things to small caches, large page sizes, or high n-way set associative caches if you want a large cache Example: suppose everything the same except that the cache is increased to 8 K bytes instead of 4 K: cache index virt page # disp Solutions: go to 8K byte page sizes; go to 2-way set associative cache; or SW guarantee VA[13]=PA[13] This bit is changed by VA translation, but is needed for cache lookup K 2-way set assoc. cache 25

26 TLB and Cache Interaction If cache tag uses physical address Need to translate before cache lookup Alternative: use virtual address tag Complications due to aliasing Different virtual addresses for shared physical address 26

27 Use virtual addresses for cache? A0-A31 CPU D0-D31 Virtual Addresses Virtual Cache D0-D31 Virtual Physical Translation Look-Aside Buffer (TLB) Physical Addresses A0-A31 Main Memory D0-D31 Only use TLB on a cache miss! Downside: a subtle, fatal problem. What is it? A. Synonym problem. If two address spaces share a physical frame, data may be in cache twice. Maintaining consistency is a nightmare. 27

28 Summary: TLB, Page tables map virtual address to physical address TLBs are important for fast translation TLB misses are significant in processor performance funny times, as most systems can t access all of 2nd level cache without TLB misses! Caches, TLBs, all understood by examining how they deal with 4 questions: 1) Where can block be placed? 2) How is block found? 3) What block is replaced on miss? 4) How are writes handled? Today VM allows many processes to share single memory without having to swap all processes to disk; 28

29 Acknowledgements These slides contain material developed and copyright by: Morgan Kauffmann (Elsevier, Inc.) Arvind (MIT) Krste Asanovic (MIT/UCB) Joel Emer (Intel/MIT) James Hoe (CMU) John Kubiatowicz (UCB) David Patterson (UCB) 29

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