ECE 4750 Computer Architecture. T16: Address Translation and Protection

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1 ECE 4750 Computer Architecture Topic 16: Translation and Protection Christopher Batten School of Electrical and Computer Engineering Cornell University! ECE 4750 T16: Translation and Protection

2 Memory Management From early absolute addressing schemes, to modern virtual memory systems with support for virtual machine monitors Can separate into orthogonal functions: Translation (mapping of virtual address to physical address) Protection (permission to access word in memory) Virtual memory (transparent extension of memory space using slower disk storage) But most modern systems provide support for all the above functions with a single page-based system ECE 4750 T16: Translation and Protection 2!

3 Bare Machine PC Inst. Cache D Decode E + M Data Cache W Memory Controller Main Memory (DRAM) In a bare machine, the only kind of address is a physical address ECE 4750 T16: Translation and Protection 3!

4 Dynamic Translation Motivation In the early machines, I/O operations were slow and each word transferred involved the CPU Higher throughput if CPU and I/O of 2 or more programs were overlapped. How? multiprogramming Location-independent programs Programming and storage management ease need for a base register Protection Independent programs should not affect each other inadvertently need for a bound register prog1 prog2 Memory ECE 4750 T16: Translation and Protection 4!

5 Simple Base and Bound Translation Load X Program Space Bound Register Effective Base Register Segment Length + Bounds Violation? Base current segment Base and bounds registers are visible/accessible only when processor is running in the supervisor mode Memory ECE 4750 T16: Translation and Protection 5!

6 Separate Areas for Program and Data Load X Program Space Data Bound Register Effective Addr Register Data Base Register + Program Bound Register Program Counter < < Bounds Violation? Bounds Violation? data segment program segment Memory Program Base Register + What is an advantage of this separation? ECE 4750 T16: Translation and Protection 6!

7 Base and Bound Machine Prog. Bound Register Logical Data Bound < Bounds Register Violation? Logical < Bounds Violation? PC + Program Base Register Inst. Cache D Decode E + M Memory Controller Data Base Register + Data Cache W Main Memory (DRAM) [ Can fold addition of base register into (base+offset) calculation using a carry-save adder (sum three numbers with only a few gate delays more than adding two numbers) ] ECE 4750 T16: Translation and Protection 7!

8 Memory Fragmentation user 1 user 2 user 3 OS Space 16K 24K 24K 32K Users 4 & 5 arrive user 1 user 2 user 4 user 3 OS Space 16K 24K 16K 8K 32K Users 2 & 5 leave user 1 user 4 user 3 OS Space 16K 24K 16K 8K 32K free 24K user 5 24K 24K As users come and go, the storage is fragmented. Therefore, at some stage programs have to be moved around to compact the storage. ECE 4750 T16: Translation and Protection 8!

9 Paged Memory Systems Processor generated address can be interpreted as a pair <page number, offset> page number offset A page table contains the physical address of the base of each page Space of User-1 Page Table of User-1 2 Page tables make it possible to store the pages of a program non-contiguously. ECE 4750 T16: Translation and Protection 9!

10 Private Space per User User 1 VA1 Page Table Memory OS pages User 2 VA1 Page Table User 3 VA1 Each user has a page table Page Table Page table contains an entry for each user page free ECE 4750 T16: Translation and Protection 10!

11 Where Should Page Tables Reside? Space required by the page tables (PT) is proportional to the address space, number of users, size of each page,... Space requirement is large Too expensive to keep in registers Idea: Keep PTs in the main memory needs one reference to retrieve the page base address and another to access the data word doubles the number of memory references! ECE 4750 T16: Translation and Protection 11!

12 Page Tables in Memory PT User 1 VA1 User 1 PT User 2 VA1 User 2 ECE 4750 T16: Translation and Protection 12!

13 Linear Page Table Page Table Entry (PTE) contains: A bit to indicate if a page exists is the physical page number, ie where virtual page is mapped into physical memory Status bits for protection and usage Page Table Offset Data Pages Data word OS sets the Page Table Base Register whenever active user process changes VPN PT Base Register VPN Offset Virtual address ECE 4750 T16: Translation and Protection 13!

14 Size of Linear Page Table With 32-bit addresses, 4-KB pages & 4-byte PTEs: Potentially 4 GB of physical memory needed per user 4-KB page means VPN is 20 bits and offset is 12 bits 2 20 PTEs, i.e, 4 MB page table overhead per user Larger pages? Internal fragmentation (Not all memory in a page is used) What about 64-bit virtual address space??? 1MB pages means VPN is 44 bits and offset is 20 bits Would still require byte PTEs (35 TB!) How can this possibly ever work? sparsity of virtual address usage ECE 4750 T16: Translation and Protection 14!

15 Hierarchical (Two-Level) Page Table Virtual p1 p2 offset 0 10-bit L1 index Root of the Current Page Table (Processor Register) 10-bit L2 index p1 Level 1 Page Table p2 offset page in memory PTE of a nonexistent page Level 2 Page Tables Data Pages ECE 4750 T16: Translation and Protection 15!

16 Two-Level Page Tables in Memory Virtual Spaces VA1 User 1 Memory Level 1 PT User 1 Level 1 PT User 2 VA1 User2/VA1 User1/VA1 User 2 Level 2 PT User 2 ECE 4750 T16: Translation and Protection 16!

17 Translation & Protection Kernel/User Mode Virtual Virtual Page No. (VPN) offset Read/Write Protection Check Translation Exception? Page No. () offset Every instruction and data access needs address translation and protection checks A good translation and protection design needs to be fast (~ one cycle) and space efficient ECE 4750 T16: Translation and Protection 17!

18 Translation Lookaside Buffers translation is very expensive! In a two-level page table, each reference becomes several memory accesses Solution: Cache translations in TLB TLB hit Single Cycle Translation TLB miss Page Table Walk to refill TLB virtual address VPN offset V R W D tag (VPN = virtual page number) ( = physical page number) hit? physical address offset ECE 4750 T16: Translation and Protection 18!

19 TLB Designs Typically entries, usually fully associative Each entry maps large number of consecutive addresses so most spatial locality within page as opposed to across pages -> More likely that two entries conflict Sometimes larger TLBs ( entries) are 4-8 way set-associative Larger systems sometimes have multi-level (L1 and L2) TLBs Random or FIFO replacement policy No process information in the TLB Flush TLB on process context switch TLB Reach: Size of largest virtual address space that can be simultaneously mapped by TLB Example: 64 TLB entries, 4KB pages, one page per entry TLB Reach =? 64 entries * 4 KB = 256 KB (if contiguous) ECE 4750 T16: Translation and Protection 19!

20 Translation in CPU Pipeline PC Inst TLB Inst. Cache D Decode E + M Data TLB Data Cache W TLB miss? Protection violation? TLB miss? Protection violation? Software handlers need restartable exception on TLB fault Handling a TLB miss needs a hardware or software mechanism to refill TLB Need mechanisms to cope with the additional latency of a TLB: slow down the clock pipeline the TLB and cache access virtual address caches parallel TLB/cache access ECE 4750 T16: Translation and Protection 20!

21 Handling a TLB Miss Software (MIPS, Alpha) TLB miss causes an exception and the operating system walks the page tables and reloads TLB. A privileged untranslated addressing mode used for walk Hardware (SPARC v8, x86, PowerPC) A memory management unit (MMU) walks the page tables and reloads the TLB, any additional complexities encountered during walk causes MMU to give up and signal an exception ECE 4750 T16: Translation and Protection 21!

22 Page-Based Memory Management Machine (Hardware Page Table Walk) Protection violation? Protection violation? Virtual Virtual PC Inst. TLB Inst. Cache D Decode E + M Data TLB Data Cache W Miss? P Register Memory Controller Miss? Hardware Page Table Walker Main Memory (DRAM) Assumes page tables held in untranslated physical memory ECE 4750 T16: Translation and Protection 22!

23 Acknowledgements These slides contain material developed and copyright by: Arvind (MIT) Krste Asanovic (MIT/UCB) Joel Emer (Intel/MIT) James Hoe (CMU) John Kubiatowicz (UCB) David Patterson (UCB) MIT material derived from course UCB material derived from course CS252 & CS152 ECE 4750 T16: Translation and Protection 23!

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