with exposed thermal pad Typical Application Circuit V OUT R OVP2 OVP DRIVER VIN VBIAS A8512 LED1 DRIVER SENSE1 SENSE2 LED2 PWM LED3 LED4 LED5 LED6

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1 essop rademarked Feaures and Benefis Six inegraed high curren sinks Fixed frequency curren mode conrol wih inegraed gae driver 300 khz o 1 MHz adjusable swiching frequency Conrolled sarup using opions of Enable, WM signal, or baery volage ramp arallel operaion wih one boos conroller (maser) and up o five slave conrollers Acive curren sharing beween LED srings for ±0.6% accuracy and maching No audible MLCC noise during WM dimming Adjusable overvolage proecion (OV) Open or shored LED sring proecion Overemperaure, cycle-by-cycle curren limi, and undervolage proecion SOIC 24-pin package for easy single-side CB manufacuring, or TSSO 24-pin and QFN 28-conac packages wih exposed hermal pad for beer hermal performance ackages: 28-conac QFN wih exposed hermal pad (ET ackage) 24-pin SOICW wih inernally fused pins (LB package) 24-pin TSSO wih exposed hermal pad (L package) No o scale Descripion The A8512 is a muli-oupu WLED/RGB driver for backlighing LCD moniors and elevisions. I inegraes a boos conroller o drive exernal MOSFET, and six inernal currensinks. The boos converer operaes in consan frequency (programmable) curren mode conrol. WM dimming allows LED currens o be conrolled in 500:1 raio. The LED sink curren is se by an exernal R_ISET resisor (see char below). More han one LED sinks can be combined ogeher o achieve even higher curren per LED sring. Muliple A8512s can be conneced in parallel, wih one maser conroller conrolling he boos sage, and up o five slave conrollers, which ac as LED sinks. This allows up o 36 LED srings o be powered by jus one boos converer. The A8512 operaes from a single supply of 8 o24 V. I provides proecion agains overvolage, open or shored LED sring, and overemperaure. A dual level cycle-by-cycle curren limi funcion provides sof sar and proecs agains overloads. The device is provided in a 24-pin SOICW package (LB), wih inernally fused pins for enhanced hermal dissipaion, and a 28-conac 5 mm 5 mm QFN package (ET) and a 24-pin TSSO package (L), boh wih an exposed hermal pad for enhanced hermal dissipaion. All packages are lead (b) free, wih 100% mae in leadframe plaing. Typical Applicaion Circui V BAT 8 o 24 V L1 DRIVER VIN VBIAS Q1 R SC D1 R OV1 SENSE1 SENSE2 OV C3 C4 18 LEDs per sring V BAT DRIVER SENSE1 SENSE2 VIN VBIAS R OV2 OV 18 LEDs per sring LED Curren versus ISET Resisor Value V REF = 1.24 V, Gain = 640 Faul Enable WM R1 Rz1 Cz1 C5 R FSET R ISET C6 FAULT EN WM COM FSET ISET VREG7V A8512 Maser LED1 LED2 LED3 LED4 LED5 LED6 AGND AGND LGND LGND GND Conrol Bus Rz2 Cz2 C7 R FSET R ISET C8 FAULT EN WM COM FSET ISET VREG7V A8512 Slave A LED1 LED2 LED3 LED4 LED5 LED6 AGND AGND LGND LGND GND To addiional slaves (ma) R ISET (kω) Figure 1. Typical applicaion circui for single IC operaion, and (in doed box) maser/slave muliple IC operaion. A8512L-DS, Rev.7

2 confirm wih acical Selecion Guide markeing ar Number acking ackage A8512ELBTR-T pieces per 13-in. reel 24-pin SOICW, wih inernally fused pins for enhanced hermal dissipaion A8512ELTR-T 4000 pieces per 13-in. reel 24-pin TSSO, wih exposed hermal pad for enhanced hermal dissipaion A8512EETTR-T 1500 pieces per 7-in. reel 28-conac QFN, wih exposed hermal pad for enhanced hermal dissipaion 1 Varian is no longer in producion. The device should no be purchased for new design applicaions. Samples are no longer available. Dae of saus change: December 1, 2015 Absolue Maximum Raings his? Characerisic Symbol Noes Raing Uni VIN in Inpu Volage V IN 0.3 o 34 V LED1-LED6 in Volage V LEDx 0.3 o 40 V OV in Inpu Volage V OV 0.3 o 50 V SENSE1 and SENSE2 in Inpu Volage V SENx 0.3 o 1 V VBIAS, VREG7V, and DRIVER ins 0.3 o 10 V Remaining ins Inpu Volage 0.3 o 7 V Operaing Ambien Temperaure T A Range E 40 o 85 ºC Maximum Juncion Temperaure T J (max) 150 ºC Sorage Temperaure T sg 55 o 150 ºC Thermal Characerisics may require deraing a maximum condiions, see applicaion informaion Characerisic Symbol Tes Condiions* Value Uni ackage ET, 4-layer CB, based on JEDEC sandard 32 ºC/W ackage Thermal Resisance R θja ackage LB, on 2-layer CB, 1-in. 2 2-oz copper exposed area 51 ºC/W ackage LB, on 4-layer CB, based on JEDEC sandard 35 ºC/W ackage L, on 4-layer CB, based on JEDEC sandard 28 ºC/W *Addiional hermal informaion available on he Allegro websie 2

3 Funcional Block Diagram V IN L1 D1 Q1 R SC R OV VIN DRIVER SENSE1 SENSE2 OV FSET R FSET OSC Curren Mode Boos Conroller Overvolage roecion Ref COM OC SS C COM Conrol and Feedback 6 LED1 +5 V 10 kω R ISET ISET WM EN VREG7V 0.1 µf VBIAS 0.1 µf FAULT LDO 7 V 5 V 50 kω Conrol Logic/ UVLO OV OC TSD Reference Curren LED Selec Logic Open/Shor LED Deec 6 6 LED2 LED3 LED4 LED5 LED6 ET and L Only AD GND AGND AGND DGND LGND LGND 3

4 in-ou Diagrams DRIVER VREG7V NC VIN NC VBIAS OV SENSE GND SENSE NC ISET EN DGND WM AD AGND AGND FSET FAULT COM LED LED5 LED4 LGND LGND LED3 LED2 LED1 EN 1 GND 2 DRIVER 3 VREG7V 4 VIN 5 AGND 6 AGND 7 VBIAS 8 OV 9 SENSE2 10 SENSE1 11 ISET WM 23 FAULT 22 LED6 21 LED5 20 LED4 19 LGND 18 LGND 17 LED3 16 LED2 15 LED1 14 COM 13 FSET EN 1 GND 2 DRIVER 3 VREG7V 4 VIN 5 VBIAS 6 NC 7 OV 8 SENSE2 9 SENSE1 10 ISET 11 AGND 12 AD 24 DGND 23 WM 22 FAULT 21 LED6 20 LED5 19 LED4 18 LGND 17 LED3 16 LED2 15 LED1 14 COM 13 FSET ackage ET ackage LB ackage L Terminal Lis Table Number ET LB L Name Funcion EN Device Enable. Apply logic-high signal o enable, low o shu down GND ower ground for exernal FET gae driver. Connec direcly o R SC ground and o common sar ground DRIVER Gae driver erminal o drive exernal MOSFET VREG7V Gae driver supply from inernal volage regulaor. Bypass wih 0.1 o 1 µf ceramic capacior o GND VIN Inpu supply volage for he IC. 11, 12 6, 7 12 AGND Analog (signal) GND for he IC. Connec o common sar ground VBIAS Bias supply volage from inernal regulaor. Bypass wih 0.1 o 1 µf ceramic capacior o AGND OV Overvolage roecion erminal. Connec his pin o oupu capacior hrough a resisor R OV o se he OV hreshold SENSE2 Connec o ground side of curren sense resisor R SC SENSE1 Connec o high side of curren sense resisor R SC ISET Ses 100% Curren hrough LED srings; connec R ISET from ISET o AGND FSET Ses swiching frequency; connec R FSET from FSET o AGND COM Compensaion pin; connec C COM (1 μf ypical) capacior o AGND. 15,16,17 15,16,17 15,16,17 LED1-3 LED curren sinks; connec unused LEDx pins o ground o disable. 18,19 18,19 18 LGND LED curren sink ground; connec o common sar ground. 20,21,22 20,21,22 19,20,21 LED4-6 LED curren sinks; connec unused LEDx pins o ground o disable F ĀŪ L T This open-drain oupu is pulled low when faul condiion occurs; connec o exernal pull-up resisor WM ulse widh modulaion LED-curren conrol; apply logic level WM for dimming DGND Digial ground for inpu conrol signals (EN and WM); connec o common sar ground. 3,5,27 7 NC No conneced elecrically. AD AD AD Exposed pad. Solder o GND plane for enhanced hermal dissipaion. 4

5 ELECTRICAL CHARACTERISTICS Valid a V IN = 12 V; T A = 25 C, R FSET = 52 kω, R ISET = 12.4 kω, excep specificaions guaraneed over he full operaing emperaure range wih T A = T J, unless oherwise noed indicaes Characerisics Symbol Tes Condiions Min. Typ. 1 Max. Uni Inpu Volage Range V IN 8 24 V Inernal Bias Volage Range V BIAS V Inernal Gae Driver Volage V DRIVER V IN 10 V V Undervolage Lockou Threshold for V IN V UVLO V IN falling V Undervolage Lockou Hyseresis for V IN V UVLOHYS 0.55 V Supply Curren 2 I VIN Swiching a no load 7 ma Shudown, EN = V IL, T A = 25 C µa Sandby, EN = V IH, WM = V IL, sof sar compleed 2 3 ma Boos Conroller Swiching Frequency f SW MHz Minimum Swich Off-Time off(min) Driver oupu 72 ns Minimum Swich On-Time on(min) Driver oupu 72 ns Logic Inpu Levels (EN and WM pins) Inpu Volage Level Low V IL 0.4 V Inpu Volage Level High V IH 1.5 V Inpu Leakage Curren 2 I IN EN = WM = 5 V 100 µa Error Amplifier COM in Source Curren I EA(src) V COM = 1.5 V 160 µa COM in Sink Curren I EA(snk) V COM = 1.5 V 20 µa COM in ull-down Resisance R COMD F Ā Ū L T = kω Driver Secion eak Source Curren 5 I pk(src) Measured a V DRIVER = 0 V 2 A eak Sink Curren 5 I pk(snk) Measured a V DRIVER = V REG7V 2 A High Side Gae Drive On Resisance R DS(on)H Measured a V DRIVER = V REG7V / 2 4 Ω Low Side Gae Drive On Resisance R DS(on)L Measured a V DRIVER = V REG7V / 2 3 Ω Sense Overcurren Threshold Volage V SEN V SENSE1 V SENSE mv LED Curren Sinks LEDx in Regulaion Volage V LEDx = 80 ma 1.4 V I SET o x Curren Gain A ISET I SET = 100 µa 640 A/A ISET in Volage V ISET V I SET Allowable Curren Range 2 I SET µa Coninued on he nex page 5

6 ELECTRICAL CHARACTERISTICS (coninued) Valid a V IN = 12 V; T A = 25 C, R FSET = 52 kω, R ISET = 12.4 kω, excep indicaes specificaions guaraneed over he full operaing emperaure range wih T A = T J, unless oherwise noed Characerisics Symbol Tes Condiions Min. Typ. 1 Max. Uni LEDx Accuracy 3 Err ILEDX LED1 hrough LED6 = 1.5 V, a 100% Curren 3 ±0.6 3 % LEDx Maching 4 ΔX LED1 hrough LED6 = 1.5 V, I SET = 100 µa 3 ±0.6 3 % LEDx Swich Leakage Curren 2 I SL V LEDx = 12 V, EN = 0 48 µa LEDx Bleeder Resisor o GND R LEDX WM = Low, V LEDx = 10 V 250 kω Sof Sar Sof Sar Sense Threshold Volage V SENS Sense volage for boos swich curren sensing Sof Sar LEDx Curren Limi Relaive o LED 100% Curren roecion Feaures (SS) Curren hrough enabled LEDx pins during sof sar 28.5 mv 8 % Thermal Shudown Threshold T TSD T J rising 165 C Shor Circui Deec Volage V SC Measured on any LEDx pin 25 V Oupu Overvolage Threshold V OV R OV = V? V OV in Leakage Curren 2 I OVLK V OV = 22 V, EN = V IL, or WM=V IL 0.1 (per OV μa Overvolage roecion Sense Curren 2 I OVH secion) μa F Ā Ū L T in Oupu Leakage 2 I FLT V = 5 V 1 µa F Ā Ū L T in Oupu Volage V OL I = 500 µa 0.4 V 1 Typical specificaions are a T A = 25ºC. 2 For inpu and oupu curren specificaions, negaive curren is defined as coming ou of he node or pin (sourcing), posiive curren is defined as going ino he node or pin (sinking). 3 LED accuracy is defined as (I SET 640 (av)) / (I SET 640), (av) measured as he average of 1 hrough 6. Refer o characerizaion char for variaion over emperaure range. 4 LED curren maching is defined as (x (av)) / (av), wih (av) as defined in foonoe 3. Refer o characerizaion char for variaion over emperaure range. 5 Guaraneed by design and characerizaion. Variaion of Toal LED Curren versus Ambien Temperaure 100% Curren = 64 ma per channel a 25 C Normalized Toal ILED(av) (%) Temperaure, T A ( C) 6

7 Characerisic erformance Efficiency (%) Efficiency versus Baery Volage for Various LED Configuraions FET = IRFR120N, V IN = 12 V, f SW = 500 khz L = 22 µh, Load = W92050C LEDs a 112 ma per sring 3 srings 18 LEDs per sring 60 V, OUT 20.2 W 2 srings 18 LEDs per sring 60 V, OUT 13.4 W 3 srings 14 LEDs per sring 47 V, OUT 15.8 W 2 srings 14 LEDs per sring 47 V, OUT 10.5 W Efficiency (%) Efficiency versus Baery Volage for Various LED Configuraions FET = FQB17N08L, V IN = 12 V, f SW = 500 khz L = 22 µh, Load = W92050C LEDs a 112 ma per srin 3 srings 18 LEDs per sring 60 V, OUT 20.2 W 2 srings 18 LEDs per sring 60 V, OUT 13.4 W 3 srings 14 LEDs per sring 47 V, OUT 15.8 W 2 srings 14 LEDs per sring 47 V, OUT 10.5 W V BAT (V) V BAT (V) Efficiency of he boos converer sage is affeced by he selecion of power MOSFET, swiching frequency, inpu/oupu volages, and oupu power. The exernal MOSFET used for he above char is he IRFR120N, which has a relaively high R DS(on) = 0.21 Ω. This causes higher conducion loss, especially a lower inpu volage. The power MOSFET is replaced wih FQB17N08L, which has a lower R DS(on) = Ω. This resuls in less conducion loss a lower inpu volage, however, he swiching loss becomes more significan a higher inpu volage Swiching Frequency versus FSET Resisor Value f SW (MHz) = 52 / R FSET (kω) fsw (khz) R FSET (kω) 7

8 Normal Sarup ower Sequences V BAT = 12 V, Load = 6 srings, 16 LEDs each sring, 56 ma per sring, Oupu capaciors = µf ceramic The A8512 can sarup wih any combinaion of inpu and power sequences, as shown in waveforms below: C3,C4 V WM V EN Symbol arameer Unis/Division V EN 10 V V WM 10 V C3 10 V C4 Toal 100 ma ime 2 ms Normal sarup wih EN = Low-o- High ransiion (WM = High) C3,C4 V WM V EN Symbol arameer Unis/Division V EN 10 V V WM 10 V C3 10 V C4 Toal 100 ma ime 2 ms Normal sarup wih WM = Low-o- High ransiion (EN = High) C3,C4 V WM V EN Symbol arameer Unis/Division V EN 10 V V WM 10 V C3 10 V C4 Toal 100 ma ime 2 ms Normal sarup wih WM signal oggling a 500 Hz, 50% duy cycle C3,C4 V WM V EN Symbol arameer Unis/Division V EN 10 V V WM 10 V C3 10 V C4 Toal 100 ma ime 2 ms Normal sarup wih baery volage ramping up from 2 o 12 V (EN= WM = High) 8

9 Typical WM Operaion Waveforms V BAT = 12 V, Load = 6 srings, 16 LEDs each sring, 56 ma per sring, Oupu capaciors = µf ceramic Symbol arameer Unis/Division V EN 10 V V WM 10 V * 1 V C4 Toal 100 ma ime 2 ms *Offse = 46 V V WM V EN WM dimming a 200 Hz 10% duy cycle; Oupu volage ripple approximaely 0.8 V (ou of 50 V) Symbol arameer Unis/Division V EN 10 V V WM 10 V * 1 V C4 100 ma ime 50 µs C4 V WM V EN *Offse = 46 V WM dimming a 5 khz 10% duy cycle Raio of LED Curren versus WM Duy Cycle WM frequency = 200 Hz Raio of LED Curren versus WM Frequency WM duy cycle = 10% Raio of LED Curren (%) 10 1 Raio of LED Curren (%) Compensaed pulse widh Uncompensaed pulse widh WM Duy Cycle (%) WM Frequency (khz) To improve he accuracy of WM dimming a very high frequency and/or very low duy cycle, i is necessary o compensae he WM pulse widh, as described in Applicaion Informaion secion. 9

10 Normal Operaion and Faul Condiions V BAT = 12 V, Load = 6 srings, 18 LEDs each sring, 56 ma per sring, Oupu capaciors = µf ceramic, ROV = 249 kω (OV a 69 V) Symbol arameer Unis/Division V EN 10 V V LEDx 10 V C3 10 V C4 Toal 100 ma ime 2 ms C4,C3 V LEDx V EN Normal sarup wih V BAT = 12 V, ( 58 V when cold) OV ripped Symbol arameer Unis/Division V EN 10 V V LEDx 10 V C3 10 V C4 Toal 100 ma ime 2 ms C4,C3 V LEDx Sarup wih one LED sring open; (OV ripped a 69 V. Open sring removed from regulaion. Remaining srings operae normally.) V EN OV ripped Symbol arameer Unis/Division V EN 10 V V LEDx 10 V C3 10 V C4 Toal 100 ma ime 2 ms C4,C3 V LEDx V EN Sarup wih all LED srings conneced, hen one LED sring becomes open; (OV ripped a 69 V. Open sring removed from regulaion. Remaining srings operae normally) Symbol arameer Unis/Division V FAULT 10 V V LEDx 10 V C3 10 V C4 Toal 100 ma ime 2 ms C4,C3 V LEDx V FAULT LED shordeec ripped OV sepoin oo high for he applicaion. Sarup wih one sring open; volage a LEDx pin exceeded Shor-Deec hreshold (25 V) before OV could be ripped. IC shus down. 10

11 Funcional Descripion his? his? Overview The A8512 is a muli-oupu WLED/RGB conroller for backlighing medium-size displays. I has an inegraed gae driver for driving an exernal N-channel boos MOSFET. The gae driver volage is regulaed a 7 V, which allows a wide selecion of power MOSFET (in conras o being limied o logic-level MOSFETs when using a 5 V gae driver). The boos conroller operaes in fixed-frequency curren-mode conrol. The swiching frequency can be se in he range from 300 khz o 1 MHz, by an exernal resisor, R FSET, conneced beween FSET and ground. The exernal MOSFET swich is proeced by pulse-by-pulse curren limiing. The curren limi is independen of duy cycle, and is se using an exernal sense resisor, R SC. The A8512 has six well-mached curren sinks ha provide regulaed curren hrough he LEDs for uniform display brighness. The boos converer is conrolled by monioring all LEDx pins simulaneously and coninuously. Muliple A8512 can be conneced in parallel, for applicaions ha require more han six LED srings. One maser conroller is in charge of he boos converer sage, while oher slave conrollers ac as LED curren sinks only. The converer oupu volage will be boosed o a level jus sufficien for all LED currens o be wihin regulaion. Up o six A8512s (1 maser + 5 slaves) can be conneced in parallel, which allows up o 36 LED srings o be powered by jus one boos converer. The maximum number of LEDs wihin each sring is limied only by he volage raings of he exernal power componens (MOSFET, diode, and capaciors). LED Curren Seing The maximum LED curren can be se, a up o 130 ma/channel, hrough he ISET pin. Connec a resisor, R ISET, beween his pin and ground o se he reference curren level, I SET. The value of I SET (ma) is deermined by: I SET = / R ISET (kω). (1) The resuling curren is muliplied inernally wih a gain of 640 and mirrored on all enabled LEDx pins: = I SET 640. (2) This ses he maximum curren hrough each LEDx, referred as he 100% Curren. The LEDx curren can be reduced from he 100% Curren value by applying an exernal WM signal on he WM pin. Conversely, we can calculae R ISET according o he LED curren required: R ISET = ( / ) 640. (3) In seady-sae operaion, he maximum average LED curren ha can be handled by he IC depends on is hermal budge. Tha is, maximum power dissipaion and accepable emperaure rise. The hermal budge is affeced by various parameers, such as CB size, copper plane around IC, LED V f mismach, selecion of power componens (MOSFET, inducor and diode), maximum board emperaure, and so on. Boos Swiching Frequency Seing Connec an exernal resisor beween he FSET pin and GND, o se boos swiching frequency, f SW. The value of f SW (MHz) is deermined by: f SW = 52 / R FSET, (4) where f SW is in MHz and R FSET is in kω. The ypical range of R FSET is approximaely 51 o 174 kω, which corresponds o 1 MHz o 300 khz. Enable The IC urns on when a high signal is applied on he EN pin, and urns off when his pin is pulled low. The LED curren sinks are urned on when boh he EN and he WM inpus are high. Channel Selecion The A8512 can be used o drive 1 o 6 LED channels. During sarup, he IC deecs LED sink pins which are shored o ground, and disables he corresponding LED channel. Therefore, any unused LED pins mus be conneced o ground, oherwise he IC will go ino overvolage proecion faul during sarup. LED pins can be paralleled ogeher for higher curren. For example for a 3 parallel sring configuraion, connec LED1 2, LED3 4, and LED5 6 ogeher o deliver up o wice he curren per LED. WM Dimming The A8512 has a very wide range for WM signal inpu. I can accep a WM signal from 100 Hz o 5 khz. When a WM high signal is applied, he LEDx pins sink WM D Figure 13. ropagaion delay from he WM signal rising edge o x reaching he 90% level 11

12 remove "ypical" oherwise V OV (yp) always = 36 V? 100% Curren. When he WM signal is low, he LED sinks urn off. Referring o figure 13, here is a ramp-up delay beween when he WM signal is applied and when he curren reaches he 90% level. To improve curren dimming lineariy for WM pulse widhs less han 100 µs, increase he applied WM pulse-widh by 3 o 5 μs o compensae for his delay. Sarup Sequence When EN is pulled high, he IC eners sof sar. The IC firs ries o deermine which LEDx pins are being used, by raising he LEDx pin volage wih a small curren. Afer a duraion of 512 swiching cycles, he LEDx pin volage is checked. Any LEDx channel wih a drain volage smaller hen 100 mv is removed from he conrol loop. This is he reason why unused LEDx pins should be conneced o GND, Afer he firs WM posiive rigger, he boos curren is limied o 30% of normal value and all acive LEDx pins sink 1 / 12 of he se curren unil oupu volage reaches sufficien regulaion level. When he device comes ou of sof sar, boos curren and he LEDx pin currens are se o normal operaing level. Wihin a few cycles, he oupu capacior charges o he volage required o supply full LEDx curren. Afer oupu volage,, reaches he required level, LEDx curren oggles beween 0% and 100% wih each WM command signal. In case of a heavy overload on a sarup, he device will say in sof sar mode indefiniely, as he oupu volage canno rise o he LED regulaion level. LED Shor Deec Any LEDx pins ha have a volage exceeding he Shor Circui Deec Volage, V SC, cause he device o shu down and his condiion is lached. This fauls occurs when muliple LEDs shor. In case only a few LEDs shor, he IC will This? coninue o work as long as power dissipaion in he IC is limied. This? Overvolage roecion The A8512 has an adjusable overvolage proecion feaure o proec he power componens (exernal MOSFET, oupu diode and capaciors) agains oupu overvolage. The overvolage level can be se, from 19.5 V o a higher volage, wih an exernal resisor, R OV. When he curren hough he OV pin exceeds 200 μa, inernal OV comparaor goes high and he device shus down. The OV faul disables all LEDx srings ha are below regulaion, hus prevening hem from conrolling he boos oupu volage. Calculae he value for R OV (Ω) as follows: R OV = (V OV 19.5) / 200 μa, (5) where V OV is he required OV level in V. For single-ic operaion, selec R OV such ha is OV sepoin is approximaely 10 V above he LED operaing volage a cold. For example, given he pin regulaion volage, V LEDx of 1.4 V (yp.), if LED V F = 3.4 V (max.) and here are 15 LEDs in series, hen he operaing volage is approximaely: = 3.4 V V = 52.4 V. In his case, selec OV a abou 60 V, which gives R OV = 200 kω. Open LED roecion During normal operaion, if any enabled LED sring opens, volage on he corresponding LEDx pin goes o zero. The boos loop operaes in open loop ill he OV level is reached. The A8512 idenifies he open LED sring when overvolage is deeced. Open srings are hen removed from he regulaion loop. Aferwards, he boos conroller operaes in normal manner, and he oupu volage is regulaed o drive he remaining srings. If he open LED sring is reconneced, i will sink curren up o he programmed curren level. Noe: Open srings are removed from boos regulaion, bu no disabled. This keeps he sring in operaion if LEDs open for only a shor lengh of ime, or reach OV level on a ransien even. The disconneced sring can be resored o normal mode by reenabling he IC. I can also be resored o normal operaion if he faul is removed from he corresponding LEDx pin, bu an OV even occurs on any oher LEDx pin. Overcurren roecion The IC provides pulse-by-pulse curren limiing for he boos MOSFET. The curren limi level, I SC (A), can be se by selecing he exernal resisor, R SC (Ω): R SC = / I SC. (6) If he boos oupu volage is unable o reach he regulaion arge even when he swich is operaing a maximum curren limi, he boos conrol loop will force he compensaing capacior, C COM, o rise in volage unil i reaches he overcurren faul level (3.4 V approximaely). The overcurren faul forces he device ino sof sar. Thermal Shudown (TSD) The IC shus down when juncion emperaure exceeds 165 C. I will recover auomaically when he juncion emperaure falls below 125 C approximaely. VIN Undervolage Lockou (UVLO) The device is shu down when inpu volage, V IN, falls below V UVLO. Any exising lached faul is cleared. V IN Operaing Range Consideraions When V IN is above V UVLO and below 10 V, he IC will operae correcly, bu is gae driver volage may no reach he regulaion arge of 7 V. This may cause excessive swiching and conducion loss if he exernal MOSFET is no fully enhanced. 12

13 During normal operaion, he IC draws approximaely 10 o 15 ma from he VIN pin, depending on swiching frequency and he exernal MOSFET. A V IN = 12 V, his ranslaes ino 120 o 180 mw of power consumpion, mos of i dissipaed in inernal linear regulaors. This power increases proporionally wih inpu volage. Therefore i is highly recommended o keep V IN beween 10 and 24 V during normal operaion. If he inpu baery volage mus be higher han 24 V, a beer soluion is o power he VIN pin separaely using a 12 V supply. Doing his reduces he hea dissipaion of he IC, and improves he overall sysem efficiency. Faul Mode in Single-Conroller Operaion Faul Sae Overvolage roecion ulseby-ulse Curren Limi Overcurren roecion Overemperaure roecion LED Shor roecion VIN UVLO Auo- Descripion Resar Faul occurs when oupu volage exceeds he OV sepoin volage. Used o preven Yes he oupu volage from damaging he power componens. Yes Yes Yes No No Faul occurs when he curren hrough he exernal MOSFET increases such ha he volage across he SENSE1 and SENSE2 pins exceeds 95 mv ypical. The MOSFET swich is urned off on a cycle-per-cycle basis. Muliple pulse-by-pulse curren limis will cause he COM pin volage o rise. Afer a ime period deermined by he COM pin curren and he COM capacior, he COM volage will exceed he overcurren deec hreshold, forcing a faul. Sysem may hiccup if he oal curren requiremen is oo high. Faul occurs when he die emperaure exceeds he over-emperaure hreshold, 165 C ypical. Faul occurs when he LED pin volage exceeds V SC, 25 V ypical. Faul occurs when VIN drops below V UVLO, 6.5 V ypical. This faul reses all lached fauls. arallel Operaion The A8512 is designed o operae wih up o six A8512 devices conneced in parallel, in order o drive a greaer number of LED srings. In his case, he A8512 which conrols he boos converer is designaed he maser, while he oher devices are slaves which serve as curren sinks for heir own LED srings. Slaves communicae wih he maser hrough he shared COM signal. WM dimming and proecion mechanisms work consisenly across all devices. Selec R OV1 for he maser conroller such ha is OV sepoin is approximaely 10 V above he LED operaing volage a cold. Selec R OV2 for each slave conroller a approximaely 15 o 25 kω lower han ha for he maser. This ensures ha, in he case in which an open-led faul occurs, he slave conrollers will enable OV before he maser does. 13

14 Applicaion Informaion Edied names o mach schemaics CB Layou Guidelines As wih any swiching power supply, care should be aken in laying ou he board. A swiching power supply has sources of high dv/d and high di/d which can cause malfuncion. All general norms should be followed for board layou. Refer o figure 14 for a ypical applicaion schemaic. The A8512 evaluaion board provides a useful model for designing applicaion circui layous. The following guidelines should be observed: lace bypass capaciors physically close o heir respecive pins (VIN, VBIAS, and VREG7V). Roue analog ground, digial signal ground, LED ground (LGND pin), and power ground (GND pin) separaely. Connec all hese grounds a he common ground plane under he A8512, serving as a sar ground. lace he inpu capaciors (, ), inducor (L1), boos diode (D1), MOSFET (Q1), and oupu capaciors (C3, C4) so ha hey form he smalles loop pracical. Avoid long races for hese pahs. lace he resisors R FSET and R ISET, and he compensaion componens (Rz and Cz) close o he FSET, ISET, and COM pins, respecively. Connec he oher ends o he common sar ground. A8512 has 50 kω inernal pull-down resisors on he EN and WM pins o keep hese pins low while driving hrough ri-sae sae (for example, shudown). Add exernal resisors R2 and R3 beween he EN and WM pins and ground, for added noise immuniy. Connec hese resisors close o he pins and reurn o he common sar ground. Sense volage across R SC wih smaller lengh races. lace he SENSE1 and SENSE2 races as close o each oher as possible o minimize noise pickup. Connec he SENSE2 race o he negaive end of he resisor and do no connec i o power ground plane. rovide a subsanial copper plane near MOSFET Q1 and he IC, o provide good hermal conducion. When using muli-layer CB, make sure here are sufficien numbers of hermal vias underneah and around he IC's exposed pads.? V BAT 8 o 24 V L1 Q1 R SC D1 R OV C3 C4 18 LEDs per sring DRIVER VIN VBIAS SENSE1 SENSE2 OV R1 C5 FAULT A8512 LED1 EN WM LED2 R2 R3 R FSET R ISET COM FSET ISET LED3 LED4 Rz1 VREG7V LED5 Cz1 C6 LED6 AGND AGND LGND LGND GND R2, R3 opional (A8512 has inernal pull-down resisors) Figure 14. Typical applicaion circui wih single conroller; VIN pin ied o V BAT. 14

15 V BAT 24 o 48 V L1 Q1 R SC D1 R OV C3 C4 36 LEDs per sring V IN 12 V R1 C5 DRIVER SENSE1 SENSE2 OV VIN VREG7V VBIAS FAULT EN A8512 LED1 C6 WM LED2 R2 R3 R FSET R ISET COM FSET ISET LED3 LED4 Rz1 Cz1 LED5 LED6 AGND AGND LGND LGND GND R2, R3 opional (A8512 has inernal pull-down resisors) Figure 15. Typical high-volage applicaion circui wih single conroller; VIN pin separae from V BAT. V BAT 12 o 48 V L1 Q1 R SC D1 R OV C3 C4 18 LEDs per sring V IN 12 V R2 R1 R3 Rz1 C5 R FSET R ISET DRIVER SENSE1 SENSE2 OV VIN VBIAS A8512 FAULT EN WM COM FSET ISET VREG7V LED1 LED2 LED3 LED4 LED5 Cz1 C6 LED6 AGND AGND LGND LGND GND R2, R3 opional (A8512 has inernal pull-down resisors) Figure 16. Typical medium-volage applicaion circui driving high-curren (up o 160 ma) LED srings. 15

16 ackage ET 28-Conac QFN ± A ± X D 0.08 C SEATING LANE 0.90 ±0.10 C C 4.80 CB Layou Reference View 0.73 MAX B 3.15 For Reference Only; no for ooling use (reference JEDEC MO-220VHHD-1) Dimensions in millimeers Exac case and lead configuraion a supplier discreion wihin limis shown A Terminal #1 mark area B Exposed hermal pad (reference only, erminal #1 idenifier appearance a supplier discreion) C Reference land paern layou (reference IC7351 QFN50500X500X100-29V1M); All pads a minimum of 0.20 mm from all adjacen pads; adjus as necessary o mee applicaion process requiremens and CB layou olerances; when mouning on a mulilayer CB, hermal vias a he exposed hermal pad land can improve hermal dissipaion (reference EIA/JEDEC Sandard JESD51-5) D Coplanariy includes exposed hermal pad and erminals 16

17 ackage LB 24-in SOICW wih Inernally Fused ins ± ± ± A 1.40 REF 1 2 Branded Face BSC X 0.10 C SEATING LANE C SEATING LANE GAUGE LANE B CB Layou Reference View BSC 2.65 MAX ins 6, 7, 18, and 19 inernally fused for enhanced hermal dissipaion For Reference Only; no for ooling use (reference MS-013AD) Dimensions in millimeers Dimensions exclusive of mold flash, gae burrs, and dambar prorusions Exac case and lead configuraion a supplier discreion wihin limis shown A B Terminal #1 mark area Reference pad layou (reference IC SOI271030X265-24M) All pads a minimum of 0.20 mm from all adjacen pads; adjus as necessary o mee applicaion process requiremens and CB layou olerances 17

18 ackage L 24-in TSSO wih Exposed Thermal ad ±0.10 8º 0º B 3 NOM 4.40± ± ±0.15 A 1.00 REF 24X 0.10 C NOM SEATING LANE C 0.25 BSC SEATING LANE GAUGE LANE 1.65 C 4.32 CB Layou Reference View BSC MAX For Reference Only; no for ooling use (reference MO-153 ADT) Dimensions in millimeers Dimensions exclusive of mold flash, gae burrs, and dambar prorusions Exac case and lead configuraion a supplier discreion wihin limis shown A Terminal #1 mark area B Exposed hermal pad (boom surface); dimensions may vary wih device C Reference land paern layou (reference IC7351 TSO65640X120-25M); all pads a minimum of 0.20 mm from all adjacen pads; adjus as necessary o mee applicaion process requiremens and CB layou olerances; when mouning on a mulilayer CB, hermal vias a he exposed hermal pad land can improve hermal dissipaion (reference EIA/JEDEC Sandard JESD51-5) Copyrigh , reserves he righ o make, from ime o ime, such deparures from he deail specificaions as may be required o permi improvemens in he performance, reliabiliy, or manufacurabiliy of is producs. Before placing an order, he user is cauioned o verify ha he informaion being relied upon is curren. Allegro s producs are no o be used in life suppor devices or sysems, if a failure of an Allegro produc can reasonably be expeced o cause he failure of ha life suppor device or sysem, or o affec he safey or effeciveness of ha device or sysem. The informaion included herein is believed o be accurae and reliable. However, assumes no responsibiliy for is use; nor for any infringemen of paens or oher righs of hird paries which may resul from is use. For he laes version of his documen, visi our websie: 18