FPGA FixedPoint Math Library User Guide


 Alexia Lucas
 2 years ago
 Views:
Transcription
1 Contents 1. Overview DISCLAIMER: National Instruments does not support the FPGA FixedPoint Math Library. The library is an internal product, so you are using the library at your own risk. 2. Common Characteristics 3. VI Reference 3.1. AddSub 3.2. Discrete Delay 3.3. Integer Accumulator 3.4. FXP To FixedPoint 3.5. FXP Add 3.6. FXP Subtract 3.7. FXP Multiply 3.8. FXP Divide 3.9. FXP Reciprocal FXP Square Root CORDIC VIs FXP Sin & Cos FXP Atan FXP Polar To Rect FXP Rect To Polar FXP Sinh & Cosh FXP Exponential FXP Natural Logarithm FPGA FixedPoint Math Library User Guide Page 1 of 50
2 1. Overview The fixedpoint math library contains a set of FPGA IPs for elementary mathematical functions that work with the LabVIEW FPGA Module. These IPs are grouped into two categories: basic elements and fixedpoint math VIs. The basic elements perform integer computation, while the fixedpoint VIs perform fixedpoint computation. Specifically, the following VIs are in the library: Basic elements: 1). AddSub 2). Discrete delay 3). Integer accumulator Fixedpoint math VIs: 1). To FixedPoint 2). Add 3). Subtract 4). Multiply 5). Divide 6). Reciprocal 7). Square root 8). CORDIC VIs: a. Sin & Cos b. Atan2 c. Polar To Rect d. Rect To Polar e. Sinh & Cosh f. Exponential g. Natural logarithm where CORDIC VIs refer to VIs implemented with CORDIC algorithms. National Instruments implemented all above VIs as configurable nodes. The VIs generate optimized FPGA code according to your configuration. Meanwhile, all VIs support bittrue and cycleaccurate simulation. So you can develop and simulate your applications on the desktop first and then compile them and deploy them to hardware targets. Page 2 of 50
3 2. Common Characteristics 2.1 Configurability All VIs are configurable. You can display the configuration dialog box by either doubleclicking a VI or rightclicking the VI and selecting Properties from the shortcut menu. Some options on configuration dialog boxes might not be configurable or applicable depending on the VI and other configuration options. Nonconfigurable or inapplicable options are dimmed. For example, the input of FXP Square Root can only be unsigned, so the Signed and Unsigned options of x type are dimmed and the Unsigned option is always selected. As another example, in FXP Sin & Cos, the Cycles per sample option is applicable only when the execution mode is Inside singlecycle timed loop. So, the option is dimmed if the execution mode is Outside singlecycle timed loop. All configuration dialog boxes have a Configuration Feedback section, which includes important implementation information corresponding to the current configuration. 2.2 Constraints on input fixedpoint data type Some VIs might not support the entire spectrum of the fixedpoint data type. For example, FXP Sin & Cos only supports inputs with word length that is greater than or equal to 4 bits. And FXP Square Root only supports unsigned fixedpoint inputs. Refer to the VI Reference section for the specific constraints of each VI. 2.3 Adapt to inputs Input terminals of fixedpoint type can adapt to supported input data types. You cannot configure the type information of an input terminal if it has adapted to the type wired to it because its type is determined by the input data type. 2.4 Execution mode VIs that take multiple cycles per computation have two different execution modes: Inside singlecycle timed loop and Outside singlecycle timed loop. Examples of such VIs include FXP Division, FXP Square Root, and all CORDIC VIs. You can select the execution mode in configuration dialog boxes. If you select Inside singlecycle timed loop for a VI, you can only place it inside a singlecycle timed loop. Similarly, if you select Outside singlecycle timed loop, you cannot place the VI inside a singlecycle timed loop. Otherwise, the Code Generation Errors window reports an error when you compile the VI. Outside singlecycle timed loop: Select this option to return a valid output after every call to the VI. Inside singlecycle timed loop: Select this option to guarantee that the VI executes in one cycle. The VI returns a computation result after each cycle and uses the output valid output to indicate whether the computation is complete and the returned result is the valid Page 3 of 50
4 final result. Refer to the Handshaking terminals section below for more information about the output valid output. 2.5 Handshaking terminals VIs configured with the Inside singlecycle timed loop execution mode have handshaking terminals (input valid, output valid, and ready for input) to assist interconnection with upstream and downstream VIs. The protocol for the handshaking terminals is specified as follows: (1) ready for input indicates that the VI can accept a new input on the next call to the VI. You must feed ready for input back through a shift register to the upstream logic to determine when to feed a new input. (2) input valid indicates to the VI whether there are new input data ready for computing at input terminals. The VI ignores all inputs when the last output of ready for input is FALSE. So, assign TRUE to input valid and feed inputs only when the last output of ready for input is TRUE. (3) The VI initiates a new computation when input valid is TRUE and the last output of ready for input is TRUE. The VI goes into a busy state and ready for input keeps FALSE until the VI can accept new inputs on the next call. (4) output valid indicates that the output from the VI is valid and ready to be read. output valid is shortlived for one cycle. So, the output must be read in the same cycle when output valid becomes TRUE. Otherwise, the output is overwritten by next call to the VI. The following diagram illustrates the application of the above handshaking terminals: The block diagram reads an input number from the input FIFO to compute its square root if the FXP Square Root VI is ready for input. If the input is read successfully (Timed Out? is FALSE) from the input FIFO, the input to input valid becomes TRUE so that the FXP Square Root starts to compute the square root. When output valid becomes TRUE, which means the FXP Square Root VI has already worked out the square root, the computed square root is passed to the output FIFO. 2.6 VI icon views Except the basic elements, all VIs in the library have two types of VI icon views. One is the expanded view with the inputs, outputs, and fixedpoint data type labeled on the icon. The other is the contracted view for saving block diagram space. You can toggle between these two types of icon by rightclicking the VI and selecting Expanded View or Contracted View from the shortcut menu. Page 4 of 50
5 3. VI Reference 3.1 AddSub Computes the sum or difference of x and y. The VI has optional terminals for cascading operations and can be configured as Add, Subtract, or Add/Subtract. Terminals x, y in load is sub? carryin borrowin carryin/no borrowin in in in in in Input operands that must be of the same type. Refer to the Supported Data Types and Remarks on Adapting to Input section for information on how the VI adapts to the input types of x and y. Specifies if the VI performs the load operation. Refer to the Functionality section for more information. This terminal is optional. Only available when you configure the VI as Add/Subtract. This terminal specifies if the operation is addition (is sub? is FALSE) or subtraction (is sub? is TRUE). Only available when you configure the VI as Add. This terminal specifies if there is an incoming carry. carryin is active high. This terminal is optional. There is no incoming carry if carryin is not visible on the block diagram. Only available when you configure the VI as Subtract. This terminal specifies if there is an incoming borrow. borrowin is active high. This terminal is optional. There is no incoming borrow if borrowin is not visible on the block diagram. Only available when you configure the VI as Add/Subtract. This terminal specifies if there is an incoming carry when is sub? is FALSE or if there is an incoming borrow when is sub? is TRUE. It is active high in the former case and active low in the latter case. This terminal is optional. There is no incoming carry or borrow if carryin/no borrowin is not visible on the block diagram. Page 5 of 50
6 s out The computed result. s is of the same type as x, y. carryout out Only available when you configure the VI as unsigned Add. This terminal indicates if there is an outgoing carry. carryout is active high. borrowout out Only available when you configure the VI as unsigned Subtract. This terminal indicates if there is an outgoing borrow. borrowout is active high. carryout/no borrowout out Only available when you configure the VI as unsigned Add/Subtract. This terminal indicates if there is an outgoing carry when is sub? is FALSE or if there is an outgoing borrow when is sub? is TRUE. It is active high in the former case and active low in the latter case. overflow out Only available when you configure the VI as signed. This terminal indicates if the result exceeds the range s can represent. overflow is always active high. AddSub Details Functionality You can configure AddSub as Add, Subtract, or Add/Subtract from the configuration dialog box. 1). Add The functionality of Add can be described by the equation below: x y c load FALSE s y c load TRUE where c 0 1 carry  in carry  in FALSE TRUE For unsigned Add, carryout is TRUE if there is an outgoing carry. For signed Add, overflow is TRUE if the result exceeds the range s can represent. 2). Subtract The functionality of Subtract can be described by the equation below: s where x y c y c c 0 1 load load FALSE TRUE borrow in borrow in FALSE TRUE For unsigned Subtract, borrowout is TRUE if there is an outgoing borrow. For signed Subtract, overflow is TRUE if the result exceeds the range s can represent. 3). Add/Subtract The functionality of Add/Subtract can be described by the equations below: Page 6 of 50
7 s x y y c c load load FALSE TRUE is sub? = FALSE where c 0 1 carry  in/noborrow in carry  in/noborrow in FALSE TRUE For unsigned Add/Subtract, carryout/no borrowout is TRUE if there is an outgoing carry. s x y c y c load load FALSE TRUE is sub? = TRUE where c 0 1 carry  in/noborrow in carry  in/noborrow in FALSE TRUE For unsigned Add/Subtract, carryout/no borrowout is FALSE if there is an outgoing borrow. For signed Add/Subtract, overflow is TRUE if the result exceeds the range s can represent. Supported Data Types The AddSub VI supports the data types listed in the following table. Supported data type Supported word length (bits) Integers (I8, U8, I16, U16, I32, U32, I64, U64) 8, 16, 32, 64 FixedPoint 1~64 Boolean 1 Boolean Array word length>=1 Notes: 1). The data type of x, y and s can be Boolean array with each element representing one bit of the number. The 0th element of the array corresponds to the least significant bit. For example, a Boolean array {TRUE, FALSE, FALSE} represents a binary number (001) binary. 2). If you configure the VI as unsigned and x, y, and s are represented in a Boolean array, the VI interprets input and output numbers as unsigned binaries. If you configure the VI as signed, the VI interprets the numbers as 2 s complement binaries. Remarks on Adapting to Inputs If both wired input x and y are of supported data type but different to each other, the AddSub VI adapts to the type with a higher priority. The priority order in adaptation of all supported types is listed in the following table. Highest > Lowest FixedPoint U64 I64 U32 I32 U16 I16 U8 I8 Boolean Array Boolean For example, if the input to x is of U64 type and the input to y is of I64, then the AddSub VI adapts to the type wired to x, i.e. U64. Page 7 of 50
8 If both wired inputs x and y are of fixedpoint data type or Boolean array, the AddSub VI adapts to the input with longer word length. If both have the same word length, then the AddSub VI adapts to the unsigned one. If both have the same word length and are both of unsigned or signed type, the AddSub VI adapts to the input with longer integer word length. Configuration Dialog Box Options Data Type  Specifies the encoding type of input x, y and output s. The AddSub VI performs integer computation and expects that x and y have the same data type. Thus integer word length makes no difference for the AddSub VI, though you can wire fixedpoint inputs to the VI. So the option to configure the integer word length is not presented on the configuration dialog box. If the VI adapts to the wired input, Data Type is dimmed. Refer to the Supported Data Types and Remarks on Adapting to Input sections for more information. Operation  Specifies the functionality of the VI. The value can be one of Add, Subtract, or Add/Subtract. Refer to the Functionality section for details about each operation. Optional Terminals Carryin/no borrowin When you select Add/Subtract as the Operation, place a checkmark in the Carryin/no borrowin checkbox if you want to show the carryin/no borrowin terminal on the block diagram. When you select Add as the Operation, place a checkmark in this checkbox if you want to show the carryin terminal. When you select Subtract as the Operation, place a checkmark in this checkbox if you want to show the borrowin terminal. Refer to the Terminals section for more information on these terminals. Page 8 of 50
9 Load Place a checkmark in this checkbox if you want to show the load terminal on the block diagram. Configuration Feedback  Displays some important implementation information corresponding to the current configuration. 3.2 Discrete Delay Delays input value for a number of loop iterations. This VI is analogous to a z n block where n can be constant or variable. Terminals D in Input data. The Discrete Delay VI loads D if enable is TRUE. Refer to the Supported Data Types section for the data types D supports. enable in Indicates if the VI is enabled. The VI loads input D and shifts data in internal registers if enable is TRUE. This terminal is optional. The VI is always enabled if this terminal is not presented. n1 in Specifies the number of loop iterations to delay. n1+1 is the number of loop iterations to delay. The input value to this terminal must be within the range specified in the brackets with the terminal name. This terminal is only available when you configure the VI as Dynamic Discrete Delay. Refer to the Functionality section for details. Q out Output data that the VI shifts out. Q is of the same data type as D. Discrete Delay Details Functionality The Discrete Delay VI implements discrete delay with 16bit shift register lookuptables (SRL16s) and a D flipflop. You can configure the VI as Constant Delay or Dynamic Delay. 1). Constant Delay If you configure the VI as Constant Delay, the number of loop iterations to delay is constant, and you can specify the delay in the configuration dialog box. For Constant Delay, if enable is TRUE, the VI outputs the data at the highest position of the shift registers, shifts all data to the next higher position, and then loads new input D to the lowest position. If enable is FALSE, the VI still outputs the data at the highest position but does not shift data or load new data. The functionality of a Constant Delay VI is shown as below. (The number of loop iterations to delay is 3 and enable is TRUE.) Page 9 of 50
10 Shift Register LookUpTable 0th 1th 2th Position Loop Iteration i D i Q i = 2 Loop Iteration i+1 D i+1 D i 0 1 Q i+1 = 1 Loop Iteration i+2 D i+2 D i D i+1 0 Q i+2 = 0 Loop Iteration i+3 D i+3 D i+2 D i+1 D i Q i+3 = D i 2). Dynamic Delay If you configure the VI as Dynamic Delay, the number of loop iterations to delay is dynamic and you can specify it through the n1 terminal at run time. The functionality of Dynamic Delay is the same as Constant Delay except that Dynamic Delay outputs the data in the (n1)th position instead of the constant highest position of the shift registers. Supported Data Types The Discrete Delay VI supports the data types listed in the following table. Supported data type Supported word length (bits) Integers (I8, U8, I16, U16, I32, U32, I64, U64) 8, 16, 32, 64 FixedPoint 1~64 Boolean 1 Boolean Array 1~64 Note: The data type of D and Q can be Boolean array with each element representing one bit of the number. The 0th element of the array corresponds to the least significant bit. For example, a Boolean array {TRUE, FALSE, FALSE} represents a binary number (001) binary. Page 10 of 50
11 Configuration Dialog Box Options Data Type General Page on the Configuration Dialog Box of Discrete Delay Word length  Specifies the word length of input D and output Q. If the VI adapts to the wired input, Word length is dimmed. Refer to the Supported Data Types section for information about what input types the VI can adapt to. Delay Settings Constant delay  Select this option if you want to configure the VI as Constant Delay. Refer to the Functionality section for details. Delay  Only applicable when you select Constant delay. This control specifies the number of loop iterations to delay. The number must be within [1, 129]. Dynamic delay  Select this option if you want to configure the VI as Dynamic Delay. Refer to the Functionality section for details. Maximum delay  Only applicable when you select Dynamic delay. This control specifies the maximum number of loop iterations to delay. The number must be within [16, 128]. Input value on the n1 terminal must be less than this number as shown in the terminal name. Page 11 of 50
12 Optional Terminals Enable  Place a checkmark in this checkbox if you want to show the enable terminal on the block diagram. Resulting schematic  Displays the schematic of how the VI implements discrete delay according to the current configuration. Configuration Feedback  Displays some important implementation information corresponding to the current configuration. Advanced Page on the Configuration Dialog Box of Discrete Delay Initial Value Configuration  Displays the bit pattern of initial values of the shift registers in the Discrete Delay VI. The indices in the left column of the listbox correspond to the positions in the shift registers. You can change the initial values individually in the list. Hex, Dec, and Bin  Specify format the listbox displays the bit pattern of initial values. Call Initialization VI  Click this button to open the Select Initialization VI dialog box. In the dialog box, you can select a VI to generate initial values for this VI. After you click OK in the dialog box, LabVIEW calls the selected VI and displays the generated values in the listbox in the Initial Value Configuration section. Page 12 of 50
13 Create Initialization VI  Click this button to open an instance of a template VI. You can edit this VI to generate initial values as you like and save it. You must close the configuration dialog box to edit the VI. 3.3 Integer Accumulator Accumulates the input x. The VI supports multichannel operations and feedback scaling. Terminals x load is sub? carryin/no borrowin s carryout/no borrow out overflow enable in in in in out out out in Input data to be accumulated. x can be represented as a fixedpoint data type or Boolean array. Specifies if the VI performs the load operation. Refer to the Functionality section for details. Specifies if the operation is addition (is sub? is FALSE) or subtraction (is sub? is TRUE). Specifies if there is an incoming carry when is sub? is FALSE or if there is an incoming borrow when is sub? is TRUE. It is active high in the former case and active low in the latter case. Returns the accumulated result. The data type of s is determined by the data type of x. The word length of s cannot be less than that of x. Only available when this VI is configured as an unsigned accumulator. This terminal indicates if there is an outgoing carry when is sub? is FALSE, or if there is an outgoing borrow when is sub? is TRUE. It is active high in the former case and active low in the latter case. Only available when this VI is configured as a signed accumulator. This terminal indicates if the result exceeds the range s can represent and is always active high. Specifies if the accumulator is enabled. If enable is FALSE, x will not be accumulated. Integer Accumulator Details Functionality The Integer Accumulator VI is an add/subtract based accumulator supporting multichannel operations. The functionality of the Integer Accumulator VI without feedback scaling is described as: Page 13 of 50
14 s s x x c c load load FALSE TRUE is sub? = FALSE where c 0 1 carry  in/noborrow in carry  in/noborrow in FALSE TRUE For unsigned accumulator, carryout/no borrowout is TRUE if there is an outgoing carry. s s x c x c load load FALSE TRUE is sub? = TRUE where c 0 1 carry  in/noborrow in carry  in/noborrow in FALSE TRUE For unsigned accumulator, carryout/no borrowout is FALSE if there is an outgoing borrow. The schematic of the Integer Accumulator VI is shown below. The VI has one loop iteration latency between input x and output s. There is also one loop iteration latency between carryout/no borrowout or overflow and x if you select Carryout registered? in the configuration dialog box. Feedback scaling scales s by a number of bits before feeding the number back to the add/subtract. FixedPoint Input If you wire a fixedpoint number to x, the VI adapts to the wired type. The fractional word lengths of x and s are identical, and the word length of s cannot be greater than 64. If you leave the x terminal unwired and set the word length of s greater than 64, the output and the input data type changes to Boolean array. Boolean Array Input If you wire a Boolean array to x, the VI interprets it as an unsigned number if you configure the type of x as unsigned, or 2 s complement binary if you configure the type of x as signed. You must interpret s the same way as x is interpreted. Page 14 of 50
15 Note: Each element in a Boolean array represents one bit of the number. The 0th element of the array corresponds to the least significant bit. For example, a Boolean array {TRUE, FALSE, FALSE} represents a binary number (001) binary. Configuration Dialog Box Options FixedPoint Configuration x Type  Specifies the type of input x. s Type  Specifies the type of output s. The signed/unsigned option is not configurable and is determined by x type. Accumulator Settings Feedback scaling  Specifies the number of bits to right shift s before feeding it back to the add/subtract computation unit. You can set Feedback scaling in range [0, 8]. Number of channels  Specifies the number of channels. The input data for multiple channels must be interleaved channel by channel. The accumulated result s and carryout/no borrowout or overflow will be output in the same way as the input. For example, a 2channel accumulator has the input and output sequences as below. Page 15 of 50
16 input sequence output sequence loop iteration i+4 loop iteration i+3 loop iteration i+2 loop iteration i+1 loop iteration i Ch1 input Ch2 input Ch1 input Ch2 input Ch1 input Ch2 output Ch1 output Ch2 output Ch1 output Ch2 output Carryout registered?  Specifies if you output the carryout/no borrowout or overflow directly from the add/subtract unit or through a register. Configuration Feedback  Displays some important implementation information corresponding to the current configuration. 3.4 FXP To FixedPoint Converts the fixedpoint input x to the fixedpoint output y. Terminals x in Input operand. y out The converted result. Indicates if the result exceeds the range y can represent. This overflow out terminal is optional. Page 16 of 50
17 Configuration Dialog Box Options FixedPoint Configuration x Type  Specifies the type of x. If the FXP Convert VI adapts to wired input, x Type is dimmed. y Type  Specifies the type of y. Overflow mode  Specifies the overflow handling mode of the VI. Rounding mode  Specifies the rounding mode of the VI. Optional Terminals Overflow  Place a checkmark in the checkbox if you want to show the overflow terminal on the block diagram. Configuration Feedback  Displays some important implementation information corresponding to the current configuration. Page 17 of 50
18 3.5 FXP Add Computes the sum of x and y. Terminals x, y in Input operands. x+y out The computed result. overflow out Indicates if the result exceeds the range it can represent. This terminal is optional. Page 18 of 50
19 Configuration Dialog Box Options FixedPoint Configuration x Type  Specifies the type of x. If the VI adapts to wired input, x, y Type is dimmed. y Type  Specifies the type of y. If the VI adapts to wired input, x, y Type is dimmed. x+y Type  Specifies the type of x+y. When you select Default type, this control is dimmed and the VI applies the default x+y type according to the input data types. Overflow never occurs if you select the Default type for the x+y Type. Overflow mode  Specifies the overflow handling mode of the VI. Page 19 of 50
20 Rounding mode  Specifies the rounding mode of the VI. Optional Terminals Overflow  Place a checkmark in the checkbox if you want to show the overflow terminal. Configuration Feedback  Displays some important implementation information corresponding to the current configuration. 3.6 FXP Subtract Computes the difference of x and y. Terminals x, y in Input operands. xy out The computed result. overflow out Indicates if the result exceeds the range xy can represent Page 20 of 50
21 Configuration Dialog Box Options FixedPoint Configuration x Type  Specifies the type of x. y Type  Specifies the type of y. xy Type  Specifies the type of xy. When you select Default type, this control is disabled and the VI selects a data type according to the input data types automatically. The computation result cannot overflow when you select Default type. Overflow mode  Specifies the overflow handling mode. Rounding mode  Specifies the rounding mode. Page 21 of 50
22 Optional Terminals Overflow  Place a checkmark in the checkbox if you want to show the overflow terminal on the block diagram. Configuration feedback  Displays some important implementation information corresponding to the current configuration. 3.7 FXP Multiply Computes the product of the inputs. Terminals x in Multiplicand. y in Multiplicator. x*y out The product of x multiplied by y. overflow out Indicates if the result exceeds the range x*y can represent. This terminal is optional. input valid in Terminals for handshaking signals. These terminals are available when you pipeline the VI and configure the execution mode to be Inside singlecycle output valid out timed loop. The ready for input terminal is not visible with this VI because the VI is always ready for input. Refer to Execution mode and Handshaking terminals in the Common Characteristics section for more information. FXP Multiply Details Pipelined Multiplier You can improve the timing performance on FPGA by pipelining the multiplier. The functionality of a pipelined multiplier is equivalent to a normal multiplier cascaded by a certain number of registers as shown below. The number of the registers is equal to the number of pipelining stages. Page 22 of 50
23 x y DFF DFF x*y normal multiplier Configuration Dialog Box Options FixedPoint Configuration x Type  Specifies the type of x. y Type  Specifies the type of y. x*y Type  Specifies the type of product x*y. When you select Default type, the x*y Type control is dimmed and the VI applies the default x*y type according to the input data types. Overflow never occurs if you select Default type for x*y. Page 23 of 50
24 Overflow mode  Specifies overflow handling mode. Rounding mode  Specifies rounding mode. Pipelining Options Pipeline the multiplier  Specifies if the VI is a pipelined multiplier. Place a checkmark in the Pipeline the multiplier checkbox to pipeline the multiplier. Number of pipelining stages  Specifies the number of pipelining stages. Number of pipelining stages must be within [1, 12]. Implement with LUT  Specifies if you want to implement the multiplier with lookuptable (LUT). If you place a checkmark in the Implement with LUT checkbox, the VI implements the multiplier using LUT. Otherwise, the VI automatically chooses to use LUT or embedded block multipliers to implement the multiplier. The LUT implementation might have better timing performance at the cost of increased resource usage. Execution Mode  Applies only if you pipeline the multiplier. Outside singlecycle timed loop  Select this option to return an output after every call to the VI. If you select this option and place the VI inside a singlecycle timed loop, the Code Generation Errors window reports an error when you compile the VI including the VI. Inside singlecycle timed loop  Select this option to guarantee that the VI executes in one cycle. If you select this option but do not place the VI inside a singlecycle timed loop, the Code Generation Errors window reports an error when you compile the VI. Optional Terminals Overflow  Place a checkmark in the checkbox if you want to show the overflow terminal on the block diagram. Configuration Feedback  Displays some important implementation information corresponding to the current configuration. Page 24 of 50
25 3.8 FXP Divide Computes the quotient of inputs. Terminals x in Dividend. y in Divisor. x/y out Quotient. overflow out Indicates if the result exceeds the range x/y can represent. This terminal is optional. input valid in Terminals for handshaking signals. These terminals are output valid out available when you configure the execution mode to be Inside singlecycle timed loop. Refer to Execution mode and ready for out Handshaking terminals in the Common Characteristics section input for more information. FXP Divide Details Functionality The FXP Divide VI computes fixedpoint division and the result is always rounded towards zero. Divide by Zero If divisor y is 0, both x/y and overflow are undefined. Execution This VI takes more than one cycle to complete a computation. Refer to Execution Mode in the Common Characteristics section for details. Page 25 of 50
26 Configuration Dialog Box Options FixedPoint Configuration x Type  Specifies the type of input x. If the VI adapts to wired input, x Type is dimmed. y Type  Specifies the type of input y. If the VI adapts to wired input, y Type is dimmed. x/y Type  Specifies the type of output x/y. If you select Default type, LabVIEW determines x/y Type according to the types of x and y. Page 26 of 50
27 Execution Mode Outside singlecycle timed loop  Select this option to return an output after every call to the VI. If you select this option and place the VI inside a singlecycle timed loop, the Code Generation Errors window reports an error when you compile the VI. Inside singlecycle timed loop  Select this option to guarantee that the VI executes in one cycle. If you select this option but do not place the VI inside a singlecycle timed loop, the Code Generation Errors window reports an error when you compile the VI. Cycles per sample  Only applicable when Execution Mode is Inside singlecycle timed loop. You can set this value to provide a new x/y every nth call to the VI where n equals Cycles per sample. Optional Terminals Overflow  Place a checkmark in the checkbox if you want to show the overflow terminal on the block diagram. Configuration Feedback  Displays some important implementation information corresponding to the current configuration. 3.9 FXP Reciprocal Computes the reciprocal of the input value. Terminals x in Input operand. 1/x out Reciprocal of x. overflow out Indicates if the result exceeds the range 1/x can represent. This terminal is optional. input in valid Terminals for handshaking signals. These terminals are available output when you configure the execution mode to be Inside singlecycle out valid timed loop. Refer to Execution mode and Handshaking terminals ready for in the Common Characteristics section for more information. out input FixedPoint Reciprocal Details Functionality Page 27 of 50
28 FXP Reciprocal computes fixedpoint reciprocal of input x and the result is always rounded towards zero. Divide by Zero If x is 0, both 1/x and overflow are undefined. Execution This VI takes more than one cycle to complete a computation. Refer to Execution Mode in the Common Characteristics section for details. Configuration Dialog Box Options Page 28 of 50
29 FixedPoint Configuration x Type  Specifies the type of input x. If the VI adapts to wired input, x Type is dimmed. 1/x Type  Specifies the type of output 1/x. If you select Default type, LabVIEW determines 1/x Type according to the type of x. Execution Mode Outside singlecycle timed loop  Select this option to return an output after every call to the VI. If you select this option and place the VI inside a singlecycle timed loop, the Code Generation Errors window reports an error when you compile the VI. Inside singlecycle timed loop  Select this option to guarantee that the VI executes in one cycle. If you select this option but do not place the VI inside a singlecycle timed loop, the Code Generation Errors window reports an error when you compile the VI. Cycles per sample  Only applicable when Execution Mode is Inside singlecycle timed loop. You can set this value to provide a new 1/x every nth call to the VI, where n equals Cycles per sample. Optional Terminals Overflow  Place a checkmark in this checkbox if you want to show the overflow terminal on the block diagram. Configuration Feedback  Displays some important implementation information corresponding to the current configuration FXP Square Root Computes the square root of input x. Terminals x in Input radicand. x must be unsigned. sqrt(x) out Computed square root. overflow out Indicates if the result exceeds the range sqrt(x) can represent. This terminal is optional. input valid in Handshaking terminals. These terminals are available when you configure output valid out the execution mode to be Inside singlecycle timed loop. Refer to ready for Execution mode and Handshaking terminals in the Common out input Characteristics section for more information. Page 29 of 50
30 FXP Square Root Details Execution This VI takes more than one cycle to complete a computation. Refer to Execution Mode in the Common Characteristics section for details. Configuration Dialog Box Options FixedPoint Configuration Page 30 of 50
31 x Type  Specifies the type of input x. If the VI adapts to wired input, x Type is dimmed. Refer to the Terminals section for more information on input x. sqrt(x) Type  Specifies the type of sqrt(x). When you select Default type, this control is dimmed and the VI applies the default sqrt(x) type according to x Type. Overflow mode  Specifies the overflow handling. Rounding mode  Specifies the rounding mode. Execution Mode Outside singlecycle timed loop  Select this option to return an output after every call to the VI. If you select this option and place the VI inside a singlecycle timed loop, the Code Generation Errors window reports an error when you compile the VI. Inside singlecycle timed loop  Select this option to guarantee that the VI executes in one cycle. If you select this option but do not place the VI inside a singlecycle timed loop, the Code Generation Errors window reports an error when you compile the VI. Cycles per sample  Only applicable when Execution Mode is Inside singlecycle timed loop. You can set this value to provide a new sqrt(x) every nth call to the VI where n equals Cycles per sample. Optional Terminals Overflow  Place a checkmark in the checkbox if you want to show the overflow terminal on the block diagram. Configuration Feedback  Displays some important implementation information corresponding to the current configuration CORDIC VIs FXP Sin & Cos Computes both the sine and the cosine of x, where x is in unit of radians. Terminals x in Input operands. x must be signed with integer word length fixed to 1. The word length must be greater than or equal to 4 bits. x is in unit of radians, i.e. if you want to calculate sin( /2) and cos( /2), you need to Page 31 of 50
32 input a x of 1/2. sin(x), cos(x) out sin(x) and cos(x) with integer word length fixed to 2. input valid in Terminals for handshaking signals. These terminals are available when output valid ready for input out out you configure the execution mode to be Inside singlecycle timed loop. Refer to Execution mode and Handshaking terminals in the Common Characteristics section for more information. FXP Sin & Cos Details Execution This VI takes more than one cycle to complete a computation. Refer to Execution Mode in the Common Characteristics section for details. Page 32 of 50
33 Configuration Dialog Box Options FixedPoint Configuration x Type  Specifies the type of input x. sin(x), cos(x) Type  Specifies the type of output sin(x) and cos(x). Rounding mode  Specifies how the VI coerces calculated sin(x) and cos(x) to a value with the precision of sin(x), cos(x) Type. Execution Mode Outside singlecycle timed loop  Select this option to return an output after every call to the VI. If you select this option and place the VI inside a singlecycle timed loop, the Code Generation Errors window reports an error when you compile the VI. Page 33 of 50
34 Inside singlecycle timed loop  Select this option to guarantee that the VI executes in one cycle. If you select this option but do not place the VI inside a singlecycle timed loop, the Code Generation Errors window reports an error when you compile the VI. Cycles per sample  Only applicable when Execution Mode is Inside singlecycle timed loop. You can set this value to provide a new pair of sin(x) and cos(x) every nth call to the VI, where n equals Cycles per sample. Input Phase Range  Specifies what range input x is in. You select [1/2, 1/2) if the input is always in phase range [ /2, /2). Otherwise, select [1, 1). This information can help the VI minimize the use of hardware resources. Configuration Feedback  Displays some important implementation information corresponding to the current configuration FXP atan2 Computes the arctangent of y/x. Terminals x, y in Input operands. x and y must be signed and of the same fixedpoint data type. The word length must be greater than or equal to 4 bits. atan2(y, x) out The arctangent of y and x in unit of radians. To get the corresponding phase value in radians, multiply atan2(y, x) by. input valid in Handshaking terminals. These terminals are available when you configure output valid out the execution mode to be Inside singlecycle timed loop. Refer to ready for Execution mode and Handshaking terminals in the Common out input Characteristics section for more information. FXP Atan2 Details Output of a special case If both input x and y are 0s, atan2(y, x) is unspecified. Output numeric error Page 34 of 50
35 Theoretically, arctangent of input (y, x) is identical to that of input (ky, kx) where k is positive. But the actual calculated results can be different due to numeric error. The greater the magnitude of input (y, x), the smaller the numeric error. Execution This VI takes more than one cycle to complete a computation. Refer to Execution Mode in the Common Characteristics section for details. Configuration Dialog Box Options FixedPoint Configuration Page 35 of 50
36 x, y Type  Specifies the type of input x and y. If the VI adapts to wired input, x, y Type is dimmed. Refer to the Terminals section for more information about inputs x and y. atan2(y, x) Type  Specifies the type of output atan2(y, x). Refer to the Terminals section for more information about output atan2(y, x). Rounding mode  Specifies how the VI coerces the calculated arctangent of y and x to a value with the precision of atan2(y, x) Type. Execution Mode Outside singlecycle timed loop Select this option to return an output after every call to the VI. If you select this option and place the VI inside a singlecycle timed loop, the Code Generation Errors window reports an error when you compile the VI. Inside singlecycle timed loop  Select this option to guarantee that the VI executes in one cycle. If you select this option but do not place the VI inside a singlecycle timed loop, the Code Generation Errors window reports an error when you compile the VI. Cycles per sample  Only applicable when Execution Mode is Inside singlecycle timed loop. You can set this value to provide a new atan2(y, x) every nth call to the VI, where n equals Cycles per sample. Input x Range Always x>= 0  Place a checkmark in this checkbox if you are sure that input x is always greater than or equal to 0. This information can help the VI minimize the use of hardware resources. Configuration Feedback  Displays some important implementation information corresponding to the current configuration FXP Polar To Rect Converts the polar coordinates into the rectangular coordinates. Terminals magnitude in The input magnitude of the polar coordinates. magnitude must be unsigned and the word length must be greater than or equal to 4 bits. phase in The input phase of a polar coordinate in unit of radians. Page 36 of 50
37 x, y out Output rectangular coordinates. x and y must be signed and of the same fixedpoint data type. input valid in Handshaking terminals. These terminals are available when you output valid ready for input out out configure the execution mode to be Inside singlecycle timed loop. Refer to Execution mode and Handshaking terminals in the Common Characteristics section for more details FXP Polar To Rect Details Execution This VI takes more than one cycle to complete a computation. Refer to Execution Mode in the Common Characteristics section for details. Page 37 of 50
38 Configuration Dialog Box Options FixedPoint Configuration magnitude type  Specifies the type of input magnitude. phase type  Specifies the type of input phase. x, y Type  Specifies the type of output x and y. Rounding mode  Specifies how the VI coerces the calculated magnitude or phase to a value with the precision of magnitude Type or phase Type respectively. Page 38 of 50
39 Execution Mode Outside singlecycle timed loop  Select this option to return an output after every call to the VI. If you select this option and place the VI inside a singlecycle timed loop, the Code Generation Errors window reports an error when you compile the VI. Inside singlecycle timed loop  Select this option to guarantee that the VI executes in one cycle. If you select this option but do not place the VI inside a singlecycle timed loop, the Code Generation Errors window reports an error when you compile the VI. Cycles per sample  Only applicable when Execution Mode is Inside singlecycle timed loop. You can set this value to provide a new pair of x and y every nth call to the VI, where n equals Cycles per sample. Input Phase Range  Specifies what range input x is in. Select [1/2, 1/2) if the input is always in phase range [ /2, /2), otherwise, select [1, 1). This information can help the VI minimize the use of hardware resources. Configuration Feedback  Displays some important implementation information corresponding to the current configuration FXP Rect To Polar Converts the rectangular coordinates into the polar coordinates. Terminals x, y in Input rectangular coordinates. x and y must be signed and of the same fixedpoint data type. The word length must be greater than or equal to 4 bits. magnitude out The output magnitude of the polar coordinates. magnitude must be unsigned and the same word length and integer word length as those of x, y. The output phase of the polar coordinates in unit of radians. phase out To get the corresponding phase value in radians, multiply phase by. input valid in Handshaking terminals. The VI shows these terminals when the output valid out execution mode is Inside singlecycle timed loop. Refer to Page 39 of 50
40 ready for input out Execution mode and Handshaking terminals in the Common Characteristics section for more details FXP Rect To Polar Details Output of a special case If both input x and y are 0s, the output phase is unspecified. Output Numeric Error Theoretically, the phase of input (x, y) is identical to that of input (kx, ky), where k is positive. But the actual calculated phase can be different due to numeric error. The greater the magnitude of input (x, y), the smaller this error. Execution This VI takes more than one cycle to complete a computation. Refer to Execution Mode in the Common Characteristics section for details. Page 40 of 50
41 Configuration Dialog Box Options FixedPoint Configuration x, y Type  Specifies the type of input x and y. If the VI adapts to wired input, x, y Type is dimmed. magnitude Type  Specifies the type of output magnitude. phase Type  Specifies the type of output phase. Page 41 of 50
42 Rounding mode  Specifies how the VI coerces the calculated magnitude or phase to a value with the precision of magnitude Type or phase Type respectively. Execution Mode Outside singlecycle timed loop  Select this option to return an output after every call to the VI. If you select this option and place the VI inside a singlecycle timed loop, the Code Generation Errors window reports an error when you compile the VI. Inside singlecycle timed loop  Select this option to guarantee that the VI executes in one cycle. If you select this option but do not place the VI inside a singlecycle timed loop, the Code Generation Errors window reports an error when you compile the VI. Cycles per sample  Only applicable when Execution Mode is Inside singlecycle timed loop. You can set this value to provide a new pair of magnitude and phase every nth call to the VI where n equals Cycles per sample. Input x Range Always x>= 0  Place a checkmark in this check box if you are sure that input x is always greater than or equal to 0. This information can help the VI minimize the usage of hardware resource. Configuration Feedback  Displays some important implementation information corresponding to the current configuration FXP Sinh & Cosh Computes the hyperbolic sine and cosine of x. Terminals x sinh(x) cosh(x) in out out Input operand that must be signed. The integer word length must be 1. The word length must be greater than or equal to 4 bits. x must be within [1, 1). If you need to input an x out of this range, you should perform preprocessing on x. Otherwise, the result will be unpredictable. Refer to Preprocessing the input section for details. The hyperbolic sine of x. sinh(x) must be signed. The integer word length must be 2. The word length must be greater than or equal to 4 bits. The hyperbolic cosine of x. cosh(x) must be unsigned. The integer word length must be 1. The word length must be greater than or equal to 3 bits. Page 42 of 50
43 input valid in Handshaking terminals. These terminals are available when you configure output valid out the execution mode to be Inside singlecycle timed loop. Refer to ready for Execution mode and Handshaking terminals in Common Characteristics out input section for more information. FixedPoint Sinh & Cosh Details Preprocessing the input The input value to x must be within the range [1, 1). If the input is out of this range, preprocess the input according to the following formula to convert the input into the range [1, 1). sinh(d)=sinh(qln2+x) = 2 Q1 [cosh x +sinh x 22Q (cosh x sinh x)] where x < ln2 = 0.69 cosh(d)=cosh(qln2+ x) = 2 Q1 [cosh x +sinh x +22Q (cosh x sinh x)] where x < ln2 = 0.69 Page 43 of 50
44 Configuration Dialog Box Options FixedPoint Configuration x Type  Specifies the type of input x. If the VI adapts to wired input, x Type is dimmed. sinh Type  Specifies the type of sinh(x). cosh Type  Specifies the type of cosh(x). Rounding mode  Specifies how the VI coerces the calculated sinh and cosh to a value with the precision of sinh Type and cosh Type respectively. Page 44 of 50
45 Execution Mode Outside singlecycle timed loop  Select this option to return an output after every call to the VI. If you select this option and place the VI inside a singlecycle timed loop, the Code Generation Errors window reports an error when you compile the VI. Inside singlecycle timed loop  Select this option to guarantee that the VI executes in one cycle. If you select this option but do not place the VI inside a singlecycle timed loop, the Code Generation Errors window reports an error when you compile the VI. Cycles per sample  Only applicable when Execution Mode is Inside singlecycle timed loop. You can set this value to provide a new pair of sinh and cosh every nth call to the VI where n equals Cycles per sample. Configuration feedback  Displays some important implementation information corresponding to the current configuration FXP Exponential Computes the exponential of x. Terminals x in Input operand that must be signed. The integer word length must be 1. The word length must be greater than or equal to 4 bits. x must be within [1, 1). If you need to input an x out of this range, you should perform preprocessing on x. Otherwise, the result will be unpredictable. Refer to Preprocessing the input section for details. exp(x) out The exponential of x. exp(x) must be unsigned. The integer word length must be 2. The word length must be greater than or equal to 4 bits. input valid in Handshaking terminals. These terminals are available when you configure output valid out the execution mode to be Inside singlecycle timed loop. Refer to ready for Execution mode and Handshaking terminals in the Common out input Characteristics section for more information. Page 45 of 50
46 FixedPoint Exponential Details Preprocessing the input The input value to x must be within the range [1, 1). If the input is out of this range, preprocess the input according to the following formula to convert the input into the range [1, 1). exp(d)=exp(qln2+x) = 2 Q exp(x) x < ln2 = 0.69 Configuration Dialog Box Options Page 46 of 50
Chapter 6 Digital Arithmetic: Operations & Circuits
Chapter 6 Digital Arithmetic: Operations & Circuits Chapter 6 Objectives Selected areas covered in this chapter: Binary addition, subtraction, multiplication, division. Differences between binary addition
More informationExpense Management. Configuration and Use of the Expense Management Module of Xpert.NET
Expense Management Configuration and Use of the Expense Management Module of Xpert.NET Table of Contents 1 Introduction 3 1.1 Purpose of the Document.............................. 3 1.2 Addressees of the
More informationEET 310 Programming Tools
Introduction EET 310 Programming Tools LabVIEW Part 1 (LabVIEW Environment) LabVIEW (short for Laboratory Virtual Instrumentation Engineering Workbench) is a graphical programming environment from National
More informationSimulation & Synthesis Using VHDL
Floating Point Multipliers: Simulation & Synthesis Using VHDL By: Raj Kumar Singh  B.E. (Hons.) Electrical & Electronics Shivananda Reddy  B.E. (Hons.) Electrical & Electronics BITS, PILANI Outline Introduction
More informationDivide: Paper & Pencil. Computer Architecture ALU Design : Division and Floating Point. Divide algorithm. DIVIDE HARDWARE Version 1
Divide: Paper & Pencil Computer Architecture ALU Design : Division and Floating Point 1001 Quotient Divisor 1000 1001010 Dividend 1000 10 101 1010 1000 10 (or Modulo result) See how big a number can be
More informationLab View with crio Tutorial. Control System Design Feb. 14, 2006
Lab View with crio Tutorial Control System Design Feb. 14, 2006 Pan and Tilt Mechanism Experimental Set up Power Supplies Ethernet cable crio Reconfigurable Embedded System Lab View + Additional Software
More informationControl Analog Out, Digital Out, and Pulse Out
Control Analog Out, Digital Out, and Pulse Out Exercise 8 Completed front panel and block diagram In this exercise, you will create a program to control the SensorDAQ s analog out terminal (this is pin
More informationLab 1: Full Adder 0.0
Lab 1: Full Adder 0.0 Introduction In this lab you will design a simple digital circuit called a full adder. You will then use logic gates to draw a schematic for the circuit. Finally, you will verify
More informationComputer Science 281 Binary and Hexadecimal Review
Computer Science 281 Binary and Hexadecimal Review 1 The Binary Number System Computers store everything, both instructions and data, by using many, many transistors, each of which can be in one of two
More informationCOMP 250 Fall 2012 lecture 2 binary representations Sept. 11, 2012
Binary numbers The reason humans represent numbers using decimal (the ten digits from 0,1,... 9) is that we have ten fingers. There is no other reason than that. There is nothing special otherwise about
More informationCS 16: Assembly Language Programming for the IBM PC and Compatibles
CS 16: Assembly Language Programming for the IBM PC and Compatibles First, a little about you Your name Have you ever worked with/used/played with assembly language? If so, talk about it Why are you taking
More informationLabVIEW Day 1 Basics. Vern Lindberg. 1 The Look of LabVIEW
LabVIEW Day 1 Basics Vern Lindberg LabVIEW first shipped in 1986, with very basic objects in place. As it has grown (currently to Version 10.0) higher level objects such as Express VIs have entered, additional
More informationDigital Image Processing
1 Introduction in IMAQ Vision. Structure of Digital Image Processing Applications Using IMAQ Vision 1.1 Introduction A grey level image is a function expressing the spatial variation of the light intensity
More informationDigital to Analog Conversion Using Pulse Width Modulation
Digital to Analog Conversion Using Pulse Width Modulation Samer ElHajMahmoud Electronics Engineering Technology Program Texas A&M University Instructor s Portion Summary The purpose of this lab is to
More information14.1. Basic Concepts of Integration. Introduction. Prerequisites. Learning Outcomes. Learning Style
Basic Concepts of Integration 14.1 Introduction When a function f(x) is known we can differentiate it to obtain its derivative df. The reverse dx process is to obtain the function f(x) from knowledge of
More informationLecture 8: Binary Multiplication & Division
Lecture 8: Binary Multiplication & Division Today s topics: Addition/Subtraction Multiplication Division Reminder: get started early on assignment 3 1 2 s Complement Signed Numbers two = 0 ten 0001 two
More informationFX 260 Training guide. FX 260 Solar Scientific Calculator Overhead OH 260. Applicable activities
Tools Handouts FX 260 Solar Scientific Calculator Overhead OH 260 Applicable activities Key Points/ Overview Basic scientific calculator Solar powered Ability to fix decimal places Backspace key to fix
More informationThe string of digits 101101 in the binary number system represents the quantity
Data Representation Section 3.1 Data Types Registers contain either data or control information Control information is a bit or group of bits used to specify the sequence of command signals needed for
More informationGetting Started with the LabVIEW Mobile Module Version 2009
Getting Started with the LabVIEW Mobile Module Version 2009 Contents The LabVIEW Mobile Module extends the LabVIEW graphical development environment to Mobile devices so you can create applications that
More informationTYPES OF NUMBERS. Example 2. Example 1. Problems. Answers
TYPES OF NUMBERS When two or more integers are multiplied together, each number is a factor of the product. Nonnegative integers that have exactly two factors, namely, one and itself, are called prime
More informationFixedPoint Arithmetic
FixedPoint Arithmetic FixedPoint Notation A Kbit fixedpoint number can be interpreted as either: an integer (i.e., 20645) a fractional number (i.e., 0.75) 2 1 Integer FixedPoint Representation Nbit
More informationLecture 2. Binary and Hexadecimal Numbers
Lecture 2 Binary and Hexadecimal Numbers Purpose: Review binary and hexadecimal number representations Convert directly from one base to another base Review addition and subtraction in binary representations
More informationInteger multiplication
Integer multiplication Suppose we have two unsigned integers, A and B, and we wish to compute their product. Let A be the multiplicand and B the multiplier: A n 1... A 1 A 0 multiplicand B n 1... B 1 B
More informationOct: 50 8 = 6 (r = 2) 6 8 = 0 (r = 6) Writing the remainders in reverse order we get: (50) 10 = (62) 8
ECE Department Summer LECTURE #5: Number Systems EEL : Digital Logic and Computer Systems Based on lecture notes by Dr. Eric M. Schwartz Decimal Number System: Our standard number system is base, also
More informationPREPARATION FOR MATH TESTING at CityLab Academy
PREPARATION FOR MATH TESTING at CityLab Academy compiled by Gloria Vachino, M.S. Refresh your math skills with a MATH REVIEW and find out if you are ready for the math entrance test by taking a PRETEST
More informationGraphing Calculator Scientific Calculator Version 2.0
Graphing Calculator Scientific Calculator Version 2.0 20061012 Infinity Softworks, Inc. www.infinitysw.com/ets August 7, 2012 1! Table of Contents Table of Contents 1 Overview! 3 2 Navigation! 4 3 Using
More informationCOMPUTER ARCHITECTURE. ALU (2)  Integer Arithmetic
HUMBOLDTUNIVERSITÄT ZU BERLIN INSTITUT FÜR INFORMATIK COMPUTER ARCHITECTURE Lecture 11 ALU (2)  Integer Arithmetic Sommersemester 21 Leitung: Prof. Dr. Miroslaw Malek www.informatik.huberlin.de/rok/ca
More informationThe 104 Duke_ACC Machine
The 104 Duke_ACC Machine The goal of the next two lessons is to design and simulate a simple accumulatorbased processor. The specifications for this processor and some of the QuartusII design components
More informationb) lower case always use lower case for all matlab commands. This is what matlab recognizes.
1 Matlab 1) Fundamentals a) Getting Help for more detailed help on any topic, typing help, then a space, and then the matlab command brings up a detailed page on the command or topic. For really difficult
More informationGetting Started with the LabVIEW Mobile Module
Getting Started with the LabVIEW Mobile Module Contents The LabVIEW Mobile Module extends the LabVIEW graphical development environment to Mobile devices so you can create applications that run on Windows
More informationLies My Calculator and Computer Told Me
Lies My Calculator and Computer Told Me 2 LIES MY CALCULATOR AND COMPUTER TOLD ME Lies My Calculator and Computer Told Me See Section.4 for a discussion of graphing calculators and computers with graphing
More informationModbus and ION Technology
70072010414 TECHNICAL 06/2009 Modbus and ION Technology Modicon Modbus is a communications protocol widely used in process control industries such as manufacturing. PowerLogic ION meters are compatible
More informationTwo's Complement Adder/Subtractor Lab L03
Two's Complement Adder/Subtractor Lab L03 Introduction Computers are usually designed to perform indirect subtraction instead of direct subtraction. Adding B to A is equivalent to subtracting B from A,
More informationThis representation is compared to a binary representation of a number with N bits.
Chapter 11 AnalogDigital Conversion One of the common functions that are performed on signals is to convert the voltage into a digital representation. The converse function, digitalanalog is also common.
More informationParamedic Program PreAdmission Mathematics Test Study Guide
Paramedic Program PreAdmission Mathematics Test Study Guide 05/13 1 Table of Contents Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7 Page 8 Page 9 Page 10 Page 11 Page 12 Page 13 Page 14 Page 15 Page
More informationDesign and FPGA Implementation of a Novel Square Root Evaluator based on Vedic Mathematics
International Journal of Information & Computation Technology. ISSN 09742239 Volume 4, Number 15 (2014), pp. 15311537 International Research Publications House http://www. irphouse.com Design and FPGA
More informationECE 3401 Lecture 9. VHDL for Arithmetic Functions and Circuits
ECE 3401 Lecture 9 VHDL for Arithmetic Functions and Circuits Outline Arithmetic Functions and Circuits: operate on binary vectors, use the same subfunction in each bit position Adders Multipliers Others
More informationEE 261 Introduction to Logic Circuits. Module #2 Number Systems
EE 261 Introduction to Logic Circuits Module #2 Number Systems Topics A. Number System Formation B. Base Conversions C. Binary Arithmetic D. Signed Numbers E. Signed Arithmetic F. Binary Codes Textbook
More informationSimple C++ Programs. Engineering Problem Solving with C++, Etter/Ingber. DevC++ DevC++ Windows Friendly Exit. The C++ Programming Language
Simple C++ Programs Engineering Problem Solving with C++, Etter/Ingber Chapter 2 Simple C++ Programs Program Structure Constants and Variables C++ Operators Standard Input and Output Basic Functions from
More informationCHAPTER 5 Roundoff errors
CHAPTER 5 Roundoff errors In the two previous chapters we have seen how numbers can be represented in the binary numeral system and how this is the basis for representing numbers in computers. Since any
More informationMathematical Procedures
CHAPTER 6 Mathematical Procedures 168 CHAPTER 6 Mathematical Procedures The multidisciplinary approach to medicine has incorporated a wide variety of mathematical procedures from the fields of physics,
More informationAccuplacer Arithmetic Study Guide
Testing Center Student Success Center Accuplacer Arithmetic Study Guide I. Terms Numerator: which tells how many parts you have (the number on top) Denominator: which tells how many parts in the whole
More informationLevent EREN levent.eren@ieu.edu.tr A306 Office Phone:4889882 INTRODUCTION TO DIGITAL LOGIC
Levent EREN levent.eren@ieu.edu.tr A306 Office Phone:4889882 1 Number Systems Representation Positive radix, positional number systems A number with radix r is represented by a string of digits: A n
More informationQuartus II Introduction for VHDL Users
Quartus II Introduction for VHDL Users This tutorial presents an introduction to the Quartus II software. It gives a general overview of a typical CAD flow for designing circuits that are implemented by
More informationLabVIEW programming I
FYS3240 PCbased instrumentation and microcontrollers LabVIEW programming I LabVIEW basics Spring 2013 Lecture #2 Bekkeng 8.1.2013 Virtual Instruments LabVIEW programs are called virtual instruments, or
More informationThe OptQuest Engine Java and.net Developer's Guilde
The OptQuest Engine Java and.net Developer's Guilde Table Of Contents Introduction to optimization... 1 What is optimization?... 1 How the OptQuest Engine works... 1 Using the documentation... 2 Platforms...
More informationDecimal Numbers: Base 10 Integer Numbers & Arithmetic
Decimal Numbers: Base 10 Integer Numbers & Arithmetic Digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 Example: 3271 = (3x10 3 ) + (2x10 2 ) + (7x10 1 )+(1x10 0 ) Ward 1 Ward 2 Numbers: positional notation Number
More informationLMS is a simple but powerful algorithm and can be implemented to take advantage of the Lattice FPGA architecture.
February 2012 Introduction Reference Design RD1031 Adaptive algorithms have become a mainstay in DSP. They are used in wide ranging applications including wireless channel estimation, radar guidance systems,
More information3.1. RATIONAL EXPRESSIONS
3.1. RATIONAL EXPRESSIONS RATIONAL NUMBERS In previous courses you have learned how to operate (do addition, subtraction, multiplication, and division) on rational numbers (fractions). Rational numbers
More informationGetting Started with the LabVIEW Embedded Module for ARM Microcontrollers 1.0 For the Keil MCB2300
Getting Started with the LabVIEW Embedded Module for ARM Microcontrollers 1.0 For the Keil MCB2300 Contents The LabVIEW Embedded Module for ARM Microcontrollers is a comprehensive graphical development
More informationSignalTap II with Verilog Designs. 1 Introduction
SignalTap II with Verilog Designs 1 Introduction This tutorial explains how to use the SignalTap II feature within Altera s Quartus II software. The SignalTap II Embedded Logic Analyzer is a systemlevel
More informationVISUAL ALGEBRA FOR COLLEGE STUDENTS. Laurie J. Burton Western Oregon University
VISUAL ALGEBRA FOR COLLEGE STUDENTS Laurie J. Burton Western Oregon University VISUAL ALGEBRA FOR COLLEGE STUDENTS TABLE OF CONTENTS Welcome and Introduction 1 Chapter 1: INTEGERS AND INTEGER OPERATIONS
More information16Tap, 8Bit FIR Filter Applications Guide
16Tap, 8Bit FIR Filter Applications Guide November 21, 1994 Application Note BY G GOSLIN & BRUCE NEWGARD Summary This application note describes the functionality and integration of a 16Tap, 8Bit Finite
More informationDRAFT. Further mathematics. GCE AS and A level subject content
Further mathematics GCE AS and A level subject content July 2014 s Introduction Purpose Aims and objectives Subject content Structure Background knowledge Overarching themes Use of technology Detailed
More informationCOMPASS Numerical Skills/PreAlgebra Preparation Guide. Introduction Operations with Integers Absolute Value of Numbers 13
COMPASS Numerical Skills/PreAlgebra Preparation Guide Please note that the guide is for reference only and that it does not represent an exact match with the assessment content. The Assessment Centre
More informationScripting with TCL, Part 1
Scripting with TCL, Part 1 Axel Kohlmeyer Center for Molecular Modeling University of Pennsylvania SBS 2007 @ JNCASR, Bangalore The VMD Execution Model GUI (FLTK) Internal State Visualization Python Interpreter
More informationLab 3: Introduction to Data Acquisition Cards
Lab 3: Introduction to Data Acquisition Cards INTRODUCTION: In this lab, you will be building a VI to display the input measured on a channel. However, within your own VI you will use LabVIEW supplied
More informationBinary Representation. Number Systems. Base 10, Base 2, Base 16. Positional Notation. Conversion of Any Base to Decimal.
Binary Representation The basis of all digital data is binary representation. Binary  means two 1, 0 True, False Hot, Cold On, Off We must be able to handle more than just values for real world problems
More informationGetting Started Manual
Getting Started Manual LabVIEW LEGO MINDSTORMS NXT Module The LabVIEW LEGO MINDSTORMS NXT Module enables you to perform the following tasks: Develop LabVIEW VIs that run on a host computer and communicate
More informationSignalTap II with Verilog Designs
SignalTap II with Verilog Designs This tutorial explains how to use the SignalTap II feature within Altera s Quartus R II software. The Signal Tap II Embedded Logic Analyzer is a systemlevel debugging
More informationVIDEO SCRIPT: 8.2.1 Data Management
VIDEO SCRIPT: 8.2.1 Data Management OUTLINE/ INTENT: Create and control a simple numeric list. Use numeric relationships to describe simple geometry. Control lists using node lacing settings. This video
More informationLabVIEW Report Generation Toolkit for Microsoft Office User Guide
LabVIEW Report Generation Toolkit for Microsoft Office User Guide Version 1.1 Contents The LabVIEW Report Generation Toolkit for Microsoft Office provides tools you can use to create and edit reports in
More informationEXPERIMENT 4. Parallel Adders, Subtractors, and Complementors
EXPERIMENT 4. Parallel Adders, Subtractors, and Complementors I. Introduction I.a. Objectives In this experiment, parallel adders, subtractors and complementors will be designed and investigated. In the
More informationDDS. 16bit Direct Digital Synthesizer / Periodic waveform generator Rev. 1.4. Key Design Features. Block Diagram. Generic Parameters.
Key Design Features Block Diagram Synthesizable, technology independent VHDL IP Core 16bit signed output samples 32bit phase accumulator (tuning word) 32bit phase shift feature Phase resolution of 2π/2
More informationIntroduction to Mathcad
CHAPTER 1 Introduction to Mathcad Mathcad is a product of MathSoft inc. The Mathcad can help us to calculate, graph, and communicate technical ideas. It lets us work with mathematical expressions using
More informationFinal Exam Review: VBA
Engineering Fundamentals ENG1100  Session 14B Final Exam Review: VBA 1 //coe/dfs/home/engclasses/eng1101/f03/ethics/en1.e05.finalcoursewrapup.sxi Final Programming Exam Topics Flowcharts Assigning Variables
More informationIntroduction to Xilinx System Generator Part II. Evan Everett and Michael Wu ELEC 433  Spring 2013
Introduction to Xilinx System Generator Part II Evan Everett and Michael Wu ELEC 433  Spring 2013 Outline Introduction to FPGAs and Xilinx System Generator System Generator basics Fixed point data representation
More informationExercise 10: Basic LabVIEW Programming
Exercise 10: Basic LabVIEW Programming In this exercise we will learn the basic principles in LabVIEW. LabVIEW will be used in later exercises and in the project part, as well in other courses later, so
More informationChapter # 5: Arithmetic Circuits
Chapter # 5: rithmetic Circuits Contemporary Logic Design 5 Number ystems Representation of Negative Numbers Representation of positive numbers same in most systems Major differences are in how negative
More informationCounters and Decoders
Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4bit ripplethrough decade counter with a decimal readout display. Such a counter
More informationLecture 8: Synchronous Digital Systems
Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered
More informationCOMPSCI 210. Binary Fractions. Agenda & Reading
COMPSCI 21 Binary Fractions Agenda & Reading Topics: Fractions Binary Octal Hexadecimal Binary > Octal, Hex Octal > Binary, Hex Decimal > Octal, Hex Hex > Binary, Octal Animation: BinFrac.htm Example
More informationThe Answer to the 14 Most Frequently Asked Modbus Questions
Modbus Frequently Asked Questions WP34REV006091/7 The Answer to the 14 Most Frequently Asked Modbus Questions Exactly what is Modbus? Modbus is an open serial communications protocol widely used in
More informationEnerVista TM Viewpoint Monitoring v7.10
EnerVista TM Viewpoint Monitoring v7.10 Guideform Specifications July 7, 2014 Page 1 of 14 1  Product Overview 1.1 Viewpoint Monitoring Scope EnerVista Viewpoint Monitoring is an easy to setup, powerful
More informationDEPLOYING A VISUAL BASIC.NET APPLICATION
C6109_AppendixD_CTP.qxd 18/7/06 02:34 PM Page 1 A P P E N D I X D D DEPLOYING A VISUAL BASIC.NET APPLICATION After completing this appendix, you will be able to: Understand how Visual Studio performs deployment
More informationModbus and ION Technology
Modbus and ION Technology Modicon Modbus is a communications protocol widely used in process control industries such as manufacturing. ACCESS meters are compatible with Modbus networks as both slaves and
More informationUsing MATLAB to Solve Differential Equations
ECE 350 Linear Systems I MATLAB Tutorial #3 Using MATLAB to Solve Differential Equations This tutorial describes the use of MATLAB to solve differential equations. Two methods are described. The first
More informationAlgorithm and Programming Considerations for Embedded Reconfigurable Computers
Algorithm and Programming Considerations for Embedded Reconfigurable Computers Russell Duren, Associate Professor Engineering And Computer Science Baylor University Waco, Texas Douglas Fouts, Professor
More information2 Programs: Instructions in the Computer
2 2 Programs: Instructions in the Computer Figure 2. illustrates the first few processing steps taken as a simple CPU executes a program. The CPU for this example is assumed to have a program counter (PC),
More informationIntroduction to Simulink
Telemark University College Department of Electrical Engineering, Information Technology and Cybernetics Introduction to Simulink HANSPETTER HALVORSEN, 2011.06.06 Faculty of Technology, Postboks 203,
More informationLab 4 Large Number Arithmetic. ECE 375 Oregon State University Page 29
Lab 4 Large Number Arithmetic ECE 375 Oregon State University Page 29 Objectives Understand and use arithmetic and ALU operations Manipulate and handle large numbers Create and handle functions and subroutines
More informationCORDIC: How Hand Calculators Calculate
Integre Technical Publishing Co., Inc. College Mathematics Journal 40: December 7, 008 :49 p.m. sultan.tex page 87 CORDIC: How Hand Calculators Calculate Alan Sultan Alan Sultan is a professor of mathematics
More informationNew parameters in Driver Sheet Copyright InduSoft Systems LLC 2006
Using the DIV & ADD and MAX & MIN Parameters in a Main or Standard Driver Category Software Equipment Software Demo Application Implementation Specifications or Requirements Item IWS Version: 6.0 and later
More informationThe equation for the 3input XOR gate is derived as follows
The equation for the 3input XOR gate is derived as follows The last four product terms in the above derivation are the four 1minterms in the 3input XOR truth table. For 3 or more inputs, the XOR gate
More informationUsing Casio Graphics Calculators
Using Casio Graphics Calculators (Some of this document is based on papers prepared by Donald Stover in January 2004.) This document summarizes calculation and programming operations with many contemporary
More informationPURSUITS IN MATHEMATICS often produce elementary functions as solutions that need to be
Fast Approximation of the Tangent, Hyperbolic Tangent, Exponential and Logarithmic Functions 2007 Ron Doerfler http://www.myreckonings.com June 27, 2007 Abstract There are some of us who enjoy using our
More informationGeneral Guide...3. Before Starting Calculation...4
General Guide...3 Turning on or off...3 Battery replacement...3 Auto poweroff function...3 Reset operation...3 Contrast adjustment...3 Display readout...4 Before Starting Calculation...4 Using " MODE
More informationDSP Laboratory: Analog to Digital and Digital to Analog Conversion
OpenStaxCNX module: m13035 1 DSP Laboratory: Analog to Digital and Digital to Analog Conversion Erik Luther This work is produced by OpenStaxCNX and licensed under the Creative Commons Attribution License
More informationIntroduction to LabVIEW
Telemark University College Department of Electrical Engineering, Information Technology and Cybernetics Introduction to LabVIEW HANS PETTER HALVORSEN, 2014.03.07 Faculty of Technology, Postboks 203,
More informationAn Introduction to Using Simulink
An Introduction to Using Simulink Eric Peasley, Department of Engineering Science, University of Oxford version 4.0, 2013 An Introduction To Using Simulink. Eric Peasley, Department of Engineering Science,
More informationCSI 333 Lecture 1 Number Systems
CSI 333 Lecture 1 Number Systems 1 1 / 23 Basics of Number Systems Ref: Appendix C of Deitel & Deitel. Weighted Positional Notation: 192 = 2 10 0 + 9 10 1 + 1 10 2 General: Digit sequence : d n 1 d n 2...
More informationThe Role of Distributed Arithmetic in FPGAbased Signal Processing
The Role of Distributed Arithmetic in FPGAbased Signal Processing Introduction Distributed Arithmetic (DA) plays a key role in embedding DSP functions in the Xilinx 4000 family of FPGA devices. In this
More informationMATH 10034 Fundamental Mathematics IV
MATH 0034 Fundamental Mathematics IV http://www.math.kent.edu/ebooks/0034/funmath4.pdf Department of Mathematical Sciences Kent State University January 2, 2009 ii Contents To the Instructor v Polynomials.
More informationFX 115 MS Training guide. FX 115 MS Calculator. Applicable activities. Quick Reference Guide (inside the calculator cover)
Tools FX 115 MS Calculator Handouts Other materials Applicable activities Quick Reference Guide (inside the calculator cover) Key Points/ Overview Advanced scientific calculator Two line display VPAM to
More informationLab 4 Multisim Evaluation of an RC Network
Lab 4 Multisim Evaluation of an RC Network Prelab Exercises All graphs must be fully labeled and drawn neatly! No answers are complete without the units! as always, show your work! 2 R 1 = 10kΩ 5V + V
More informationfx83gt PLUS fx85gt PLUS User s Guide
E fx83gt PLUS fx85gt PLUS User s Guide CASIO Worldwide Education Website http://edu.casio.com CASIO EDUCATIONAL FORUM http://edu.casio.com/forum/ Contents Important Information... 2 Sample Operations...
More informationDisplay Format To change the exponential display format, press the [MODE] key 3 times.
Tools FX 300 MS Calculator Overhead OH 300 MS Handouts Other materials Applicable activities Activities for the Classroom FX300 Scientific Calculator Quick Reference Guide (inside the calculator cover)
More information