An Improved Design of Optical LIFO Buffer with Switched Delay Lines

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1 2011 IEEE 12th International Conference on High Performance Switching and Routing An Improved Design of Optical LIFO Buffer with Switched Delay Lines Xiaoliang Wang, Xiaohong Jiang and Achille Pattavina State Key Laboratory of Novel Software Technology, Department of Computer Science and Technology, Nanjing University, China Future University Hakodate, Hokkaido, Japan Department of Electronics and Information, Politecnico di Milano, Milano, Italy Abstract The lack of optical buffer is still one of the main problems that hinder the development of all optical networks. One approach to this problem is to emulate the behavior of optical buffers by using optical switches and fiber delay lines (SDL). Current works on this topic have demonstrated the feasibility of constructing SDL-based First In First Out (FIFO) buffer, Priority buffer, etc. The Last In First Out (LIFO) buffer is another important network component for congestion control and QoS guarantee, and parallel and cascade architectures have been peoposed for the efficient design of such optical buffer [1], [2]. The recent work in [3] showed that it is possible to use M fiber delay lines (FDLs) to construct a LIFO buffer of size B = (3/2) 2 M/2 1 and B = 2 (M+1)/2 1 when M is even and odd, respectively. In this paper, we improve the work in [3] by providing a more efficient construction of SDL-based optical LIFO buffer. We first show that with a single stage feedback structure consisted of one (M + 1) (M + 1) crossbar switch and M FDLs connecting M outputs of the crossbar back to M its inputs, we are able to construct a LIFO buffer of size B = 2 2 M/2 2 and B = (3/2) 2 (M+1)/2 2 when M is even and odd, respectively. This is achieved through adopting a properly delay length setting for each FDL and a careful packets scheduling among FDLs, as well as exploiting the nice function of simultaneous packet reading and witting a FDL can support. We further show that if we adopt a cascade of smaller switches rather than a single (M+1) (M+1) big switch, the new LIFO design can be implemented with much lower complexity in terms of the total number of basic 2 2 switch elements. I. INTRODUCTION Buffering is the fundamental function for contention resolution in packet switching networks. Current practice for buffering optical packets is to use electronic memories, which involves the quite expensive optical-electronic-optical conversions and excessive power consumption in network nodes. All optical buffering is a promising approach for significantly reducing the buffering complexity and power consumption in future all optical and green networks. The fiber delay line This work is partially supported by the National Science Foundation of China under Grant Nos and , and JSPS grants (B) X. Jiang is also a visiting researcher of the State Key Laboratory for Novel Software Technology, Nanjing University, China. (FDL), which provides a certain amount of delay for optical signal, is by now the only feasible way to directly store optical packets. There has been an extensive attention on the construction of all-optical buffers by circulating packets through a combination of optical switches and fiber delay lines (SDL). To ensure the emulation of their electronic counterparts, in SDL-based optical buffer designs the length (thus delay) of each FDL and the related packets control among FDLs should be carefully designed such that each arrival packet can be delivered to the right output link at the right time. Recent progress on the SDL-based optical buffer designs indicates that it is possible to use SDL to emulate various kinds of optical buffers, like the First In First Out (FIFO) buffers [1], [4], [5], Push In First Out (PIFO) buffers (or Priority buffers) [6] [8] and Priority Shared buffers [9], etc. A typical recursive construction for a FIFO buffer of size B was proposed by C. S. Chang et al. in [4], which requires just 2log 2 B switches (as well as FDLs) by applying the joining-theshortest-queue and serving-the-longest-queue control rules in each step of the recursion. Later, N. Beheshti et al. [5] proposed an optical FIFO construction with also 2log 2 B optical switches but a much simple control algorithm. This construction introduces an aligner before feedback FDLs such that the arrival packets can be consecutively buffered in these feedback FDLs. The issue of exact emulation of priority buffers has been addressed in [6], [7], [10]. Recently, Kogan et al. [8] demonstrated that by using time-slot interchange (TSI) and a feedback FDL of length B, it is possible to design a PIFO buffer of size B with only O(log 2 B) 2 2 switches. The LIFO optical buffer, the focus of this paper, is another important network component widely used for maintaining the fairness and packet ordering. B. A. Small et al. [2] developed a cascade optical LIFO buffer architecture based on multiple building-block modules, where each module can independently perform its own reading and writing processes. Since each module in this cascade LIFO architecture contains only one FDL and can accommodate only one packet, the overall capacity of the LIFO design is highly limited. P. K. Huang et al. [1] introduced a recursive construction of parallel /11/$ IEEE 132

2 LIFO buffers based on the idea of two-level cashing. In such a design, the short FDLs act as the high speed storage device while the long FDLs work as the low speed but large size storage device, and arrival packets are properly directed to different FDL-cashes under specified thresholds. The results in [1] indicate that no less than 9log 2 B FDLs are required to build a LIFO buffer of size B. Our recent work in [11] shows that 3log 2 B FDLs are enough for us to construct a LIFO buffer of size B. The basic idea of such construction is to organize every 3 FDLs of same length as one FDL group, pack consecutive packets into frames and schedule packets among FDL groups frame by frame. Our further work in [3] indicates that by grouping every 2 FDLs (rather than 3 FDLs) as one FDL group and doing scheduling packet by packet among FDL groups, with M FDLs we are able to construct a LIFO of size B = (3/2) 2 M/2 1 and B = 2 (M+1)/2 1 when M is even and odd, respectively. In other words, only 2log 2 B FDLs is enough to construct a LIFO of size B. This paper improves the work in [3], [11] by providing a more efficient construction of SDL-based optical LIFO buffer. We will show that by adopting a FDL grouping technique as that of [3] and a frame-based packet scheduling as that of [11], a single stage feedback structure with one (M +1) (M +1) crossbar switch and M FDLs can work as a LIFO buffer of size B = 2 2 M/2 2 and B = (3/2) 2 (M+1)/2 2 when M is even and odd, respectively. We further demonstrate that the new LIFO design can be implemented by using a cascade of smaller switches rather than a single big switch, resulting a much lower implementation complexity in terms of the total number of basic 2 2 switch elements. The remainder of this paper is organized as follows. Section II introduces the assumptions and definitions related to the LIFO buffer design. In Section III, we present the new feedback design of LIFO buffer. We further introduce in Section IV a cascade implementation of the LIFO design with low complexity. Finally, Section V provides the comparisons between the proposed designs and the designs in [3], [11]. II. PRELIMINARIES To simplify the design and operation of SDL-based optical buffers, we adopt the following assumptions that have been widely used in previous works [4], [6], [8], [12]. The time of system is sliced and synchronized. The packet size is fixed such that one packet can be transmitted within one time slot. Each FDL provides an integer number of time slots delay (we call this number as the length of the FDL hereafter). Therefore, once a packet is inserted into a FDL of length l, it will be reachable again from the other side of this FDL l time slots later. In the following, we first give the definition of LIFO buffer and then introduce the principle of packet scheduling to emulate such a buffer. Definition 1: (Optical LIFO Buffer) As illustrated in Fig. 1, an optical LIFO buffer of size B is an optical component that has one arrival link (i 0 ), one departure link (d 0 ) and one lost Fig. 1. An optical LIFO buffer of buffer size B, which contains one arrival link (i 0 ), one departure link (d 0 ) and one lost link (l 0 ). link (l 0 ). Such a component can exactly emulate an electronic LIFO buffer with up to B packets, i.e., when a departure request comes, the departure packet is the one most recently stored in the buffer; once the number of buffered packets is equal to B, the buffer becomes full and any newly arrived packet will be dropped through the lost link l 0. To indicate the packet departure order, we assign each packet a priority. Definition 2: (Priority) Each packet is assigned with an unique priority value as follows: if a newly arrived packet is admitted to the LIFO buffer, it is assigned with the highest priority 1 and the priority of each previously buffered packet will be increased by 1; if a packet leaves the LIFO buffer, the priority of each remaining packet will be decreased by 1. Notice that once an optical packet enters a FDL of length d, it will come out d time slots later and can not be retrieved any time earlier. Thus, for the exact emulation of an electronic LIFO buffer, the packet scheduling should follow the following rule to avoid the possible extra delay that may occur when a packet s turn of departure comes. (R1) A packet of priority p can never be assigned to a FDL with length longer than p. III. CONSTRUCTION OF LIFO BUFFER To explore the effective LIFO buffer design, we adopt the feedback switch architecture shown in Fig. 2. The core of this architecture is an (M + 1) (M + 1) crossbar switch that supports all (M + 1)! permutations between its inputs and outputs. The M outputs of the crossbar are connected back to M its inputs through M FDLs, where the i th FDL has a length of r i. The remaining input port of the crossbar is connected with the arrival link i 0 and lost link l 0 via an 1 2 switch, while the remaining output port there is connected with the departure link d 0. If there are B packets being buffered in the system and the output is not enabled, any newly arrived packet from i 0 will be dropped directly through the lost link l 0. A. Fiber Delay Line Setting Similar to the delay line setting in [3], all the M FDLs are divided into M/2 FDL-groups, where the length of a FDL in the k th group G k is set as 2 k 1, k [1, M/2 ], as illustrated in Fig. 3. The length of all M FDLs can be expressed as r i = 2 (i 1)/2, i = 1,2,...,M (1) 133

3 first packet of the frame in this FDL departs from it, such that we can immediately begin to insert a new frame into this released FDL. This possible because packets reading and writing operations can be performed simultaneously in a fiber. Clearly, we need b consecutive time slots to move a frame of size b. Formally, the scheduling algorithm works as follows: Fig. 2. A feedback structure of optical LIFO buffer, which consists of an (M + 1) (M + 1) crossbar and M FDLs connecting M outputs back to M inputs of the crossbar. Fig. 3. The setting of FDLs in our LIFO buffer design. Every 2 FDLs are grouped and delay length of fiber grows exponentially among groups. The number indicates the priority of consecutively buffered packets. Scheduling Algorithm (S1) (1) arrival if buffer is full then drop the newly arrived packet. else increase the priority of all buffered packets by 1, assign priority 1 to the newly arrived packet and insert it into G 1. (2) departure deliver the packet with priority 1 to the output, and decrease the priority of all remaining packets by 1. (3) scheduling for each group for k = 1 to K 1 if a new frame comes then if G k is full then combine the two frames which contain lower priorities packets in G k together to form a new frame, send the newly formed frame to G k+1. accept arrival frame to free FDL. if G k is free then send a read request signal to G k+1. if a read request signal comes then send the frame containing the highest priority packet in G k to G k 1 B. Scheduling Algorithm Based on (1), the main idea of packet scheduling is to place packets consecutively in FDLs according their priorities, as shown in Fig. 3. To guarantee the above property, we take frame rather than packet as the basic scheduling granularity among FDL groups, where a frame in FDL-group G k consists of 2 k 1 consecutive packets. Thus, the frame size in each FDL group just equals to the length of a FDL in the same group. By doing so, a packet with priority p in G k+1 is always aligned with a packet with priority q in G k when p mod 2 k 1 = q mod 2 k 1, i.e., these two packets will emerge from FDLs at the left side of crossbar switch simultaneously. For the FDL-group G k, if it is full (i.e., all its FDLs are full) but a new frame is arriving from G k 1, then we combine together the two frames that contain the packets of lower priorities within group G k to form a new frame, and forward the newly formed frame to group G k+1. On the other hand, if the FDL-group G k becomes free (i.e., all its FDLs are free) after the departure of a frame from this group, then we deliver the frame in G k+1 that contains the packets of higher priorities within this group to the group G k. Here, a FDL is considered as a released FDL when the For the sake of comprehension, we introduce here an example to illustrate the packet scheduling process of (S1) for a system with M = 6. Example 1: Assume that at the end of time slot T, there are four packets in the system, see Fig. 4 (a). Then, at the beginning of time slot T + 1, packets with priority 1, 2 and 3 will emerge from FDLs, as shown in Fig. 4 (b). Suppose a new packet arrives at this time slot but there is no departure request, the priority of all the packets will be increased by one. Since G 1 is full and a new packet comes, the packets with lower priorities 2 and 3 in G 1 will be combined together to form a new frame and sent to G 2. As packets are consecutively placed in FDLs, the packet with priority 2 is first moved to the free FDL 4 in G 2, which is aligned with the packet with priority 4. Then, the packet with priority 3 will be inserted into FDL 2 and moved to FDL 4 at the next time slot T + 2, as shown in Fig. 4 (c). If a departure request comes at T + 3, the packet with the highest priority 1 departs from the system, see Fig. 4 (d). As G 1 becomes free, the packets with priority 1 and 2 in G 2 will be delivered to FDL 1 and FDL 2 at time slot T +3 and T + 4 in sequence. Based on the scheduling algorithm (S1) and the FDL setting 134

4 Fig. 4. An example of scheduling algorithm (S1). Within the dotted line, the left side of figure illustrates the scenario at the beginning of time slot t, the middle illustrates the revision of packet priority, and the right side illustrates the scenario at the end of time slot t. (1), we can establish the following theorem. Theorem 1: For the construction in Fig. 2 with FDL setting (1) and scheduling algorithm (S1), it can work as a LIFO buffer of size B, where B = M r i = i=1 { 2 2 M/2 2, M is even (3/2) 2 (M+1)/2 2, M is odd Proof: We use induction to prove the theorem. It is obvious that when M 2, the feedback construction in Fig. 2 can emulate a LIFO buffer of size B = M i=1 r i. Assume that the theorem 1 holds for G k 1, we just need to show that this theorem also holds for G k, i.e., for all packets storing in G 1,...,G k (up to k i=1 r i packets there), the rule (R1) is still guaranteed. For the sake of presentation, we set the priority of a frame as the highest priority of all packets within this frame. We first consider the scenario that a tagged frame is moving from G k 1 to G k at time slot t. Based on (S1), we can deduce that at this time G k 1 is full and a new frame arrives there. Thus, by recursively applying this deduction for all G i,i < k, we know that at time slot t: 1) a new packet with the highest priority comes to the system; 2) one FDL in G i is full. Since the frame being sent to G k is the one with the lowest priority among all frames in G 1,...,G k 1, so its priority is no less than the sum of FDL length for groups from G 1 to G k 1, i.e. (2) the following value, k 1 2 i = 2 k 1 (3) i=1 Notice that the FDL length in G k is 2 k 1, so each packet in the tagged frame is sent to a FDL whose length is no larger than the value of its priority. Thus, the rule (R1) is guaranteed for this scenario. Now we consider the scenario that a tagged frame in G k is forwarded to G k 1 when G k 1 becomes free. Based on the scheduling algorithm (R1), the tagged frame can be kept in G k 1 if none of G k with k < k 1 is free. Therefore, we can deduce that the priority of the tagged frame is larger than k 2 2 i 1 = 2 k 1 1 (4) i=1 which is equal to the length of a FDL in G k 1. Thus, the rule (R1) also holds for this scenario. The above conditions guarantee that in G k the (R1) always holds for both frames arrival and departure scenarios. Since the system with (k 1) groups can emulate a LIFO buffer of size k 1 i=1 r i, and a frame will be forwarded to G k only if all FDL groups G 1,...,G k 1 are full, the system can accommodate as large as k i=1 r i packets. By setting this value as buffer size, the proof follows. The above results indicate that with one (M +1) (M +1) switch and M FDLs we can construct a LIFO buffer of size (2), which improves the buffer capacity of designs in [3], [11]. In the next section, we further show that the new LIFO design can be actually implemented with much lower complexity by adopting a cascade of smaller switches rather than one big (M + 1) (M + 1) switch. IV. A CASCADE IMPLEMENTATION OF LIFO BUFFER The core of the construction in Fig. 2 is an (M+1) (M+1) crossbar switch, which is not scalable as the parameter (M+1) increases. Notice that in the proposed construction of LIFO buffer, all FDLs are organized into groups and each group follows the identical and independent scheduling procedure, which makes it possible for us to use a cascade of smaller switch blocks (one for a FDL group) to support the same scheduling function as that of using one large size switch. Fig. 5 (a) illustrates such a cascade implementation for the LIFO buffer design introduced in Section III. This construction consists of M/2 independent switch blocks, and one block is associated with one FDL-group. Here, we also denote these blocks by G k, 1 k M/2. Each switch block consists of a 4 4 non-blocking switch fabric (e.g., a Benes switch), where two inputs and two outputs are used to connect with adjacent blocks, and remaining outputs are connected back to remaining inputs through two FDLs (notice that in G 1, one input should be connected with the buffer input port and one output should be connected with the buffer output port). It is easy to prove in the same way as that of the Theorem 1 that by applying the FDL setting (1) and group-based scheduling 135

5 frame, send the newly formed frame to G k+1. accept arrival frame to free FDL. if G k is free then send a read request signal to G k+1. if a read request signal comes then send the frame containing the highest priority packet in G k to the newly released FDL in G k 1 Fig. 5. Cascade construction of LIFO buffer. (a) Cascade of independent switch blocks (one for each FDL group); (b) switch block for G 1, which consists of 2 feedback FDLs and a 4 4 Benes network; (c) switch block for G k, k > 1, which consists of 2 feedback FDLs and a 4 4 Banyan network. algorithm (S1), the cascade construction in Fig. 5 (a) also works as a LIFO buffer of size (2). Notice that in the above scheduling algorithm (S1), the arrival frame to a FDL group is forwarded to a randomly selected free FDLs. In what follows we will show that except the group G 1, if the arrival frame to any other FDL group accesses the free FDLs there in a predefined order (rather than in a random order), it possible for us to adopt a low cost Banyan network in such a group to provide the limited connection patterns required for packet scheduling there. We now show that with a 4 4 Benes network in G 1 (see Fig. 5 (b)) and a 4 4 Banyan network in any other switch block G k,k > 1 (see Fig. 5 (c)), the cascade construction in Fig. 5 can still work as a LIFO buffer of size (2) under the following new scheduling algorithm (S2). Scheduling Algorithm (S2) (1) arrival ( same as (S1) ) (2) departure ( same as (S1) ) (3) scheduling for each group for k = 1 to K 1 if a new frame comes then if G k is full then combine the two frames which contain lower priorities packets in G k together to form a new Proposition 1: For the construction in Fig. 5 with a 4 4 Benes network in G 1 and a 4 4 Banyan network in each group G k,k > 1, it can work as a LIFO buffer of size B = M i=1 r i under the FDL setting (1) and scheduling algorithm (S2). Proof: For the sake of presentation, we denote the 4 SEs adopted in each group G k, k > 1, as SE 1 SE 4, as that illustrated in Fig. 5 (c). The main idea of our proof is to show that packets will not conflict at the output ports of SE 1 and SE 3. Without loss of generality, we focus on switch block G k and regard it as the tagged block. First, we consider the output ports of SE 1 in G k. Suppose two packets arrive at SE 1, they are the packet a retrieved from G k+1 and the packet b emerged from FDL 2k. Let p(a) (resp. p(b)) denote the priority of packet a (resp. b). Based on (S2), we know p(a) > p(b). Assume these two packets conflict at the output port connecting to SE 2, i.e. the packet a is scheduled to FDL 2k and the packet b is scheduled to G k+1. Since p(a) > p(b), the above scenario is contrary to the fact that packets are consecutively placed in FDLs. On the other hand, suppose these two packets conflict at the output port of SE 1 connecting to SE 4, i.e. the packet a is scheduled to G k 1 and the packet b is scheduled to FDL 2k 1. This scenario can only happen when G k becomes empty after a read request signal comes. Since packet b just emerged from FDL 2k, the packet a from G k can be put into FDL 2k to avoid the possible conflict, as depicted in (S2). Second, we consider the output ports of SE 3 in G k. Suppose two packets arrive at SE 3, they are the packet a retrieved from G k 1 and the packet b emerged from FDL 2k 1. Based on (S2), we know p(a) < p(b). Assume these two packets conflict at the output port connecting to SE 4, i.e. the packet a is scheduled to FDL 2k 1 and the packet b is scheduled to G k 1. Since p(a) < p(b), this case is contrary to the fact that packets are consecutively placed in FDLs. On the other hand, suppose these two packets conflict at the output port of SE 3 connecting to SE 2, i.e., the packet a is scheduled to FDL 2k and the packet b is scheduled to G k+1, this case can only happen when G k becomes full after a new frame comes to G k. Since packet b is just emerged from FDL 2k, the packet a can be forward to FDL 2k 1 to avoid the possible conflict, as depicted in (S2). Notice that the above properties do not hold for the group G 1, where the arrival packet with the highest priority may be directly sent out to the output port via the switch fabric, so a nonblocking Benes switch is required to support such operation there. The above proposition indicates that by adopting the cascade construction in Fig. 5, a LIFO buffer of size (2) can be 136

6 Buffer Size, B Fig. 6. Fig. 7. Number of 2x2 SEs Buffer Size of LIFO in [10] Buffer Size of LIFO in [3] Buffer Size of LIFO (Improved) Number of Delay Lines, M Comparison of LIFO buffer designs in terms of the buffer size Single stage implementation Cascade implementation (M+1) Comparison of LIFO buffer designs in terms of required 2 2 SEs. implemented with just a number of (4 M/2 +2) basic 2 2 SEs. V. COMPARISON OF LIFO BUFFER CONSTRUCTIONS Here we compare the design of LIFO buffer proposed in this paper with that in [3], [11] in terms of both buffer size and implementation complexity. The Fig. 6 shows how the buffer size of above three designs varies with the number of FDLs M. We can see that in general the buffer size of the proposed LIFO buffer design is around 0.5 times larger than that of [3]. This is due to the reason that all FDLs in the proposed LIFO design serve as buffers while in the design of [3] only half of FDLs there serve as buffers. The Fig. 6 also indicates that for a given number of FDLs, the new design provides a much larger buffer size than that of [11] since the proposed LIFO buffer requires only 2 FDLs instead of 3 FDLs in each FDL group. We further compare the complexity in terms of 2 2 SEs between the single stage implementation and the cascade implementation of the proposed LIFO buffer. For the single stage implementation, we take the nonblocking Benes network as an example to build the (M + 1) (M + 1) switch fabric 64 there, which results in a requirement of (M + 1)log 2 (M + 1) (M + 1)/2 basic 2 2 switching elements (SEs) [13]. As illustrated in Fig. 7, we can see that the required switch elements of cascade construction is significantly less than that of single stage construction for different setting of the parameter (M + 1) (i.e., the switch size in single stage implementation). We can see from the Fig. 7 that as (M + 1) increases, the gap between the single stage construction and cascade implementation tends to increase sharply, so the cascade implementation provides a more scalable solution for the construction of a large size LIFO buffer. VI. CONCLUSION In this paper, we present a more efficient design of LIFO buffer by adopting M FDLs of setting (1) in the single stage feedback construction and applying the scheduling algorithm (S1). We further show that by applying the scheduling algorithm (S2) and adopting cascade of small switches (rather a single large switch), the new buffer design can be implemented with a much low complexity in terms of basic 2 2 switching elements. This work sheds light on the optimal constructions for LIFO optical buffer as well as the more powerful priority buffer. REFERENCES [1] P. K. Huang, C. S. Chang, J. Cheng, and D. S. Lee, Recursive constructions of parallel FIFO and LIFO queues with switched delay lines, IEEE Transactions on Information Theory, vol. 53, pp , [2] B. A. Small, A. Shacham, and K. Bergman, A modular, scalable, extensible, and transparent optical packet buffer, Journal of Lightwave Technology, vol. 25, no. 4, pp , April [3] X. Wang, X. Jiang, and S. Horiguchi, Packets scheduling for optical SDL LIFO buffers, in 15th Asia-Pacific Conference on Communications (APCC 2009)., 2009, pp [4] C. S. Chang, Y. T. Chen, and D.-S. Lee, Constructions of optical FIFO queues, IEEE Transactions on Information Theory, vol. 52, no. 6, pp , [5] N. Beheshti and Y. Ganjali, Packet scheduling in optical FIFO buffers, in High-Speed Networking Workshop, Anchorage, Alaska, May 2007, pp [6] A. D. Sarwate and V. Anantharam, Exact emulation of a priority queue with a switch and delay lines,, Queueing Systems: Theory and Applications, vol. 53, pp , July [7] H. C. Chiu, C. S. Chang, J. Cheng, and D. S. Lee, A simple proof for the constructions of optical priority queues, Queueing Systems: Theory and Applications, vol. 56, pp , [8] H. Kogan and I. Keslassy, Optimal-complexity optical router, in IEEE INFOCOM 2007, Alaska AK, May [9] X. Wang, X. Jiang, A. Pattavina, and S. Horiguchi, A construction of 1-to-2 shared optical buffer queue with switched delay lines, IEEE Transactions on Communications, vol. 57, no. 12, pp , Dec [10] D. S. Lee, C. S. Chang, J. Cheng, H. S. Chueh, and K. T. Wang, Emulation of an optical flexible delay line by parallel variable optical delay lines, IEEE Communications Letters, vol. 14, pp , [11] X. Wang, X. Jiang, and A. Pattavina, Constructing optical LIFO buffers of size B with 3log 2 B fiber delay lines, in Proceedings of the 14th conference on Optical network design and modeling, ONDM 10, 2010, pp [12] C. S. Chang, D. S. Lee, and C. K. Tu, Recursive construction of optical multiplexers with switched delay lines, IEEE Transactions on Information Theory, vol. 50, pp , Dec [13] A. Pattavina, Switching Theory, Architectures And Performance In Broadband ATM Networks. John Wiley & Sons, August,

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