Layout of Transmission Gate. 2-input Multiplexer Layout

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1 Layout of Transmission Gate S S -input Multiplexer Layout 1

2 Chapter 5 CMOS logic gate design Section 5. -To achieve correct operation of integrated logic gates, we need to satisfy 1. Functional specification. Temporal (timing) constraint. (1) In CMOS, incorrect functions are caused by 1. Incorrect or insufficient power supplies, or power supplies, or power supply noise.. Noise on gate input (so we need noise margin) 3. Faulty transistors 4. Faulty connections to transistors 5. Incorrect ratio in ratioed logic 6. Charge sharing or incorrect clocking dynamic gates -In general, CMOS is tolerable to noise ->safeness good choice for modern system - level Ic designs () A fair portion of the design cycle may be spent in optimizing the speed of the design. CLoad tf(tr, td) k β V eff DD where k is a constant β eff no. of e.g., in 3-input NAND gate - Cload : β transistors in parallel or serial β = n β = β 3 effp p effn, (1) Size of transistors in the gate (self-loading) () Size and number of transistors to which the gate is connected. (3) The routing capacitance own the gate and other the gates it drives

3 Also, speed of gate will be affected by tr/tf of input - Check speed -> Find the critical paths of your design We can use timing analyze to find the critical paths (1) Algorithm level ((Power-of-two coefficients instead of real multiplier) () Architecture level (e.g., carry look-ahead adder design) (3) RTL/logic gates (check pipelining, fan-in, fan-out, etc). (4) Circuit-level level approaches (5) Layout level design skills =>Most leveraged way is achieved by completing a good architecture Fan-in and Fan-out of Logic gates (a) Fan-in: Number of inputs e.g., 4-input NAND gate has a fan-in of 4, -input NAND gate has a fan-in of (it is known in advance.) (b) Fan-out: Total number of gate inputs that are driven by a gate output. Default gate size=minimum sized inverter as unity. Fan-in & Fan-out will be affected by stage ratio and transistors in parallel or serial 3

4 R tr = n p ( m n C + C + K C ) d r g Tr (rise time) for an m-input NAND gate: } (1) Rp: effective resistance of a p-device in a unit inverter. () n: width multiplier of PMOS (3) k: fan-out (4) m: fan-in (5) Cg: gate capacitance of an unit inverter. (6) Cd: drain capacitance (7) Cr: Routing capacitance. R p Tr = (m n C r C g + q(k) C g + k C g ) n { {{ Drain cap Routing cap Fan-out { where R: Cd/Cg: ratio of the intrinsic drain capacitance of an inverter to the gate Capacitance: q(k):represent routing cap interms of Cg 4

5 5.. Example: (SPICE simulation) Wn = 6µ, Ln = 1µ Wp = 1.3µ, Lp = 1µ - Tinput-rise/fall =0.1ns - Cl=0->1pF =>NAND gate is a better choice than NOR gate Example of an 8-input NAND gate construction Approach1:An 8-input NAND + an Inverter. Approach:Two 4-input NAND +-input NOR Approach3 : see Figure 5

6 Trade off between Area & speed (power?) Transistor sizing: stage ratio to drive large Cl (such as clock & global reset) Guideline: Start with minimum sized devices then optimize paths from a critical-path-timing analysis. Optimizing paths can be done at different levels - Use NAND structures where possible - Place (big) inverters at high fan-out nodes if possible - Avoid the use of NOR structures in high-speed circuits (fan-in > 4 or fan-out is large) - Use a fan-out below Use minimum-sized gate on high fan-out nodes to minimize Cl presented to the driving gate. - Keep rising and falling edges sharp 6

7 5.4 CMOS Logic structures CMOS complementary logic Two function determing blocks: N- block and P-block n transistors for an n-input logic gate Pseudo-NMOS logic Z = A ( B + C) + ( D E) 7

8 5.4.4 Dynamic CMOS Logic { Z= 0, n-block short 1, n-block open clk=0, Z=1(C L is charged to vdd) { clk=1, Z is conditionally evaluated { CLK is a single phase clock Pull-up time is improved. Pull-down time is increased due to the ground switch. Problems: (a) Inputs can only change during the precharge phase and must be stable during the precharge phase -> charge sharing may corrupt the o/p mode voltage. (b) Simple single-phase dynamic CMOS gates cannot be cascaded (some delay between N1&N) 8

9 precharge evaluat Old value = n-logic is short New vlaue = n-logic is open Clocked CMOS Logic C MOS Pass-Transistor Logic F = PV i i i P V V i i i = = Control _ signals Pass _ signals { 0,1, X, X, Z } i i F = P V ) + P ( V ) + L + ( P 1 1 ( V n n ) 9

10 Example1: Use pass-transistor logic to design a -input XNOR gate (a) Truth table (b) Pass-network Karnaugh map (c) Logic function Use A:control signal B:passed signal F = A ( B) + A ( B) (d) Implementation (a) Complementary (b) NMOS (c) Cross-coupled Example: Use pass-transistor logic to construct Boolean function (a).truth Table 10

11 (b) Implementation: The apparent advantages of pass-transistor networks in CMOS should be studied carefully (e.g, how to achieve good logic levels?) CMOS domino logic (1) During precharge (clk=0), PZ=1, and inverter o/p=0 () Transistors in subsequent logic blocks will be turned off during the precharge phase (3) Each gate in sequence can make at most one transistion (1 to 0)=>can be used in cascaded logic gates 11

12 Limitations: (1) Each gate must be buffered (an advantage, too) () Only non-inverting structures are possible (3) Common in dynamic CMOS- charge sharing Charging sharing in Dynamic CMOS C A 0 A = high 1 C7 = low = low 5 when clk = 1 Q in C Q in C 1 1 is dumpedinto C C 7 V n1 IF C = 1 ( C 7 i= 1 V C ) + C = 3 C i DD 1 & C = C 3 = C 4 = C 5 = C 6 = C 7 then V n1 = 3C 6C + 3C V DD = 0.33V DD = 1.65V turn onthe inverter Solution: (a) Place clocked NMOS at (a) the Place bottom clocked NMOS at the (b) bottom Provide immediate nodes (b) with Provide their immediate own nodes with precharging their own precharging transistors 1

13 5.4.8 NP domino logic(zipper CMOS) Will turn off next stages during pre-charging Advantage of D. CMOS (1) Smaller area () C, speed (3) Glitch free if design carefully 5.5 Clocking strategies (a) FSM (b) Pipelined system 13

14 (a) Stup time: the time before the clock edge that the D input has to be stable (b) Hold time: the time after tue clock edge that the Dinput has to main stable (c) Clock-to-Q delay (Tq) : the delay from the positive clock input to the new value of the Q output. Latches (a).negative levelsensitive latch (b)positivelevel-sensitive latch (c)positive edge-triggered register(master-slave) (d) Operation of the master-slave register (e) CMOS circuit implementation. Keep Q Keep D value 14

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