Optical switch fabric design for Gigabit Switching Router

Transcription

1 Optical switch fabric design for Gigabit Switching Router Wei Wei *, Qingji Zeng R&D Center for Broadband Optical etworking Technology Dept. of Electronic Engineering, Shanghai Jiaotong University, Shanghai ,China ABSTRACT One of the key issues of high performance IP Gigabit Switching Router (GSR) design is about switching fabrics. In the traditional bus-based router architectures, the data transfer rate of copper backplanes will soon reach the speed limit because of connector reflections and crosstalk. An alternative optical switching fabric technology is necessary in order to satisfy the demand for high switching bandwidth. In this paper we firstly present a novel all-optical broadcasting switch fabric design scheme based on broadcasting bus architecture. In this section we also illustrate the advantages and disadvantages of this kind of architecture and demonstrate that this kind of switching fabric architecture have no interior block as well as none I/O block. Second, we discuss such implementation scheme of all-optical broadcasting switch fabric architecture as queuing, scheduling and multicasting. Finally, we get a conclusion that all-optical broadcasting switch fabric is one of the cost-effective solutions to design high-speed, scalable and simple switch fabrics compared with those complicated electric crossbar switch fabrics in GSR design. Keywords: Gigabit Switching Router (GSR), switch fabric, queuing, scheduling, VCSEL 1. ITRODUCTIO Internet has caused the traffic on the Internet to grow drastically every year for the last several years. The explosive growth of Internet users, the increased user demand for bandwidth, and the declining cost of technology have all resulted in the emergence of new classes of high-speed distributed IP-router architectures with packet-forwarding rates on the order of gigabits per second. Driven by the insatiable demand for bandwidth by customers and by the decreasing cost of technology, new generations of switched routers that support service differentiation over gigabit links have started to emerge. This growth in IP traffic is beginning to stress the traditional processor-based design of current-day routers and as a result has created new challenges for router design. The first generation of IP router was based on software implementations on a single general-purpose central processing unit (CPU) 4. Routers have traditionally been implemented purely in software. Because of the software implementation, the performance of a router was limited by the performance of the processor executing the protocol code. For the second-generation IP routers, improvement in the shared-bus router architecture was introduced by distributing the packet forwarding operations 4. A major limitation of this architecture is that it has a traffic dependent throughput and also the shared bus is still a bottleneck. To alleviate the bottlenecks of the second generation of IP routers, the third generations of routers were designed with the shared bus replaced by a switch fabric 1, 2, 3, 9. This provides sufficient bandwidth for transmitting packets between interface cards and allows throughput to be increased by several orders of magnitude. Typical architecture of the third generation of routersisasfollows: * Correspondence: wwzb@263.net; Telephone: ; Fax: Optical Switching and Optical Interconnection, Lih-uan Lin, Shulian Zhang, Editors, Proceedings of SPIE Vol. 4582, APOC 2001, Beijing, China (2001) 2001 SPIE X/01/$

2 Figure 1: switch-based router architecture 9. As showed in Figure1, a generic switch-based router has four components: input ports, output ports, a switch fabric, and a control unit. An input port is the point of attachment for a physical link and is the point of entry for incoming packets. Ports are instantiated on line cards, which typically support 4, 8, or 16 ports. The switch fabric interconnects input ports with output ports. The main function of the control unit is to configure the switch fabric to pass packets queued in the input queues to the correct output queues based on some routing decision. Other queuing strategies are possible too, e.g., only at the input side or the output side, a larger shared queuing memory, or internally in the switch fabric. The switch fabric interconnects the line cards. For systems with an aggregate capacity of less than about 1 gigabits per second (Gbps). As bandwidth demand on the Internet continues to grow, new and faster switching fabrics are needed. Switching fabrics can be built using a variety of structures. Switching fabric architecture can in most cases be divided into two categories: shared memory 6 (e.g. Juniper M160) and crossbar 5 (e.g. Cisco series). For a switch fabric with an aggregate capacity of up to 20 Gbps a crossbar or a shared memory is currently popular. For an aggregate capacity in excess of 20 Gbps a crossbar or a multi-stage switch fabric is generally used 4. The crossbar is the most flexible switch fabric and can be compared with a fully connected topology, i.e., point-to-point connections between all possible combinations of two nodes. The drawback, however, is the increase by 2 in cost/complexity of the switch, where is the number of ports. Systems with a single true crossbar are therefore limited to small systems. For the shared memory architecture, the switch fabric must operate at the total throughput rate, at least equal to the aggregate of all the input links connected to the switch. However, increasing line rate (S)andincreasingswitchportsize() make it extremely difficult to significantly speedup the switch fabric, and also build memories with a bandwidth of order O(S). In engineering design, copper-based high-speed switch fabrics (electronic crossbar or shared memory) are usually difficult to implement for electrical reflections and crosstalk. To solve some of the above dilemmas faced in today's communication switch fabric architectures, some members of the design community have shifted their attention to optical domain techniques. The reason for this interest lies in three aspects: (i) easy to design (ii) good scalability and (iii) high performance (e.g. high-speed, non-blocking properties). We envision it s important trends in router switch fabric design. In this paper we firstly present a novel all-optical broadcasting switch fabric design scheme based on broadcasting bus architecture. This kind of switch fabric 252 Proc. SPIE Vol. 4582

3 architecture allows simple scaling of connections and bandwidth. Thus, as the amount of traffic increases on the network, system designers can continually grow their boxes to meet these demands. Another key benefit of this kind of switch fabric lies in its flexible routing capabilities including multicasting and broadcasting. We also outline some other design issues facing the GSR such as queuing, scheduling and multicasting. 2. OPTICAL SWITCH FABRIC ARCHITECTURE Switch fabric design is a very well studied area, especially in the context of ATM switches. The switch fabric in a router is responsible for transferring packets between the other functional blocks. In particular, it routes user packets from the input ports to the appropriate output ports. The design of the switch fabric is complicated by other requirements such as multicasting, fault tolerance, and loss and delay priorities. When these requirements are considered, it becomes apparent that the switch fabric should have additional functions, e.g., concentration, packet duplication for multicasting if required, packet scheduling, packet discarding, and congestion monitoring and control. Currently there is a shift from copper technologies to optical technologies because of electric limits and EMC in switch fabric design. ovel optical interconnection technologies 8, 9 result in the possibility of new solutions for the increasing bandwidth demands of high-speed switch fabric. In an all-optical network, the data stream remains in the optical form all the way from the transmitter to the receiver. Most research work 8,9 on optical networks have been focused on LAs or similar but they can be used as substitutes for switch fabrics in data- and telecommunication equipment too. It should be noted that if one of these networks is used in a router (or ATM switch) as a switch-fabric, the signal is converted to electrical and back to optical form at the entrance and the exit of the switch-fabric. We present a passive all-optical broadcasting switch fabric architecture that is shown in Figure 2. Three major kinds of components are included in this architecture: (i) 1: power splitter (ii) Address Filter and (iii) QoS issues control logic (i.e. queuing, scheduling and accessing control). Independent paths exist between all 2 possible pairs of inputs and outputs. In this design, arriving packets are broadcasted on separate buses to all outputs. Address filters at each output determine if the packets are destined for that output. Appropriate packets are passed through the address filters to the output queues (FIFO). Proc. SPIE Vol

4 1 1: power splitter 1: power splitter Ingress 1: power splitter AF AF AF AF AF AF QoS issues control Logic QoS issues control Logic 1 Figure 2: All-optical broadcasting switch fabric architecture. This architecture offers many attractive advantages. First, there is naturally no conflict among the 2 independent paths between inputs and outputs, and hence all queuing occurs at the outputs. Output queuing achieves the optimal normalized throughput compared to simple FIFO input queuing 2. Second, like the shared memory architecture 6,itis also broadcast-and-select in nature and, therefore, multicasting is natural. Third, this architecture reduces complexity of switch fabric, all the components of this switch fabric architecture are easy to implement. The 1: power splitters, address filters (AF), output buffers and QoS control logic circuits are simple to implement to use ASIC or FPGA technologies. Finally, unlike the shared memory architecture, the address filters and buffers need to operate only at the port speed. All of the hardware circuit can operate at the same speed. There is no speed-up factor to limit scalability in this architecture. For these reasons, this architecture has been taken in our commercial IP 40Gb/s router designs. Unfortunately, the quadratic 2 growth of buffers and transceivers means that the size must be limited for practical reasons (e.g. <=16). However, in principle, there is no severe limitation on S (line card speed). The port speed S can 254 Proc. SPIE Vol. 4582

5 be increased to the physical limits of the address filters and output buffers. Hence, this architecture might realize high total throughput S packets per second by scaling up the port speed S. In the article 7,Insteadof buffers at each output, it was proposed to use only a fixed number L buffersateachoutput(foratotalofl buffers which is linear in ), based on the observation that the simultaneous arrival of more than L packets (cells) to any output was improbable. It was argued that L = 8 is sufficient under uniform random traffic conditions to achieve a cell loss rate of 10-6 for large. 3. SCHEDULIG AD MULTICASTIG To achieve wire-speed routing and QoS, high-performance queuing policies (e.g. VOQ) together with high efficiency scheduling technologies were required. In our switch fabric architecture design, we adopt novel output queuing and scheduling technologies that is illustrated in Figure 3. AF firstly filter packets from each input ports from 1 to -1 and simply discard those packets which don t belong to current port ID. Then packets were buffered in a chip of FIFO to wait for scheduling of the scheduler. In Figure 3, Queues are required to store packets during the inevitable periods when the packet arrival rate exceeds the transmission rate of the output port. They are used to perform traffic shaping or rate limiting. In our switch fabric architecture design, each flow can be assigned a specific bandwidth. Packets will only leave the queue if the amount of bandwidth currently consumed by the class to which they belong is less than the predetermined limit. 1 O/E AF Congestion control FIFO O/E AF Congestion control FIFO O/E AF Congestion control FIFO O/E AF Congestion control FIFO Scheduler Figure 3:, scheduling and address filter 3.1 Scheduling The simplest scheduling algorithm is first-come-first-served (FCFS). FCFS service is trivial to implement, requiring the router or switch to store only a single head and tail pointer per output trunk. An alternative service method called round robin scheduling has better performance. In the round robin scheduling approach, each source sharing a bottleneck link is allocated an ideal rate of service at that link. Round robin scheduling and its variants are mechanisms that serve packets from the output queue to approximately partition the trunk service rate in this manner. All versions of round robin scheduling require packets to be served in an order different from the one in which they arrived. Consequently, round robin scheduling is more expensive to implement than FCFS. In our all-optical switch fabric architecture, we improve round robin scheduling algorithm to a new scheduling method. We divide each queue state into 2 kinds: (1) Busy when this queue reaches 50% capacity; (2) Free when this queue is not the state of Busy. As well we divide each arriving IP packet into 2 kinds: (1) Long packet when this packet lengths is greater than 64 bytes; (2) Short packet when this packet lengths is lesser than 64 bytes. The scheduler in Figure 3 is responsible for scheduling tasks. The scheduler consequently queries each queue (FIFO) and when it finds Proc. SPIE Vol

6 current queue is in the state of Busy, then it quickly output packets from this queue until the current queue reach the state of Free. When the scheduler find current queue is in the state of Free, then it check the first packets lengths in this queue, if it is Short packet, the scheduler will directly output packets from this queue, otherwise it computes the number M= L/64 (L: packet lengths), and then put M-1 to C (C: round robin times). For each query, C will be decreased 1 by the scheduler and when C=0,the scheduler will output the Long packet. The scheduling algorithm flow is illustrated as Figure 4. Start i=0(i: queue ID) T=1ms(T: query time cycle ) Query current queue i If i is busy? C=0 C=0 Compute L (packet lengths) Output C=C 1 C=1 C=[L/64] If i is busy? Delay T C=0 C=0 Output Delay T i=[i+1] mod T End Figure 4: scheduling algorithm logical flow 3.2 Multicasting ew applications or services are emerging that utilize multicast transport. These applications include distribution of news, financial data, software, video, audio and multi-person conferencing. These services or applications will require a router to multicast an incoming packet to a number of selected outputs or broadcast it to all outputs. Multicasting is 256 Proc. SPIE Vol. 4582

7 inherently natural in our switch fabric architecture. Our approach consists of broadcasting incoming packets and selecting the appropriate packets with address filters at the output buffers. For multicasting, an address filter can recognize a set of multicast addresses as well as output port addresses. Multicast addresses which are pasted on the head of each packet as a select tag have the same format as WORD: each bit from low to high represent for one outport from 1 to 32 and if the bit is 1,then the AF will select this packet, otherwise the AF will discard it directly. 4. COCLUSIOS Compared with the switch fabric design of Cisco or Juniper 5, 6, this paper discusses a new method to the construction of large switch fabrics. All-optical broadcasting switch fabric architecture design can achieve high performance of a full throughput and as well it has a good scalability of capacity. This approach has no special constraints on throughput or size; only physical factors do limit the maximum size in practice. Optical interconnection complexity and power dissipation will become more difficult issues with fabric size 8. In addition, reliability and repair ability become difficult with size. It is generally accepted that large router switch fabrics of 1 terabits per second (Tbps) throughput or more cannot be realized simply by scaling up a fabric design in size and speed. Instead, large fabrics must be constructed by interconnection of switch modules of limited throughput. Based on the above idea, we have designed a Terabit optical router prototype that has four switch fabrics. Each switch fabric has 320Gb/s switch capacity and is interconnected by Vertical Cavity Surface Emitting Laser (VCSEL) to the other. Each interconnection link between switch fabrics all works at 40Gb/s. Obviously, such Terabit switch fabrics can t achieve a full throughput because of internal block. But we believe that such a problem will be solved for the innovation of optical interconnections. ACKOWLEDGMETS The authors would like to express their gratitude to Prof. Q.jin Zeng for valuable comments. Financial support from ational atural Science Foundation of China (project O ) is gratefully acknowledged. REFERECES 1.. McKeown, M. Izzard, A. Mekkittikul The Tiny Tera: A Packet Switch Core IEEE Micro 1997(1-2), 26~33 2. Craig Partridge, Philip P. Carvey, Ed Burgess A 50-Gb/s IP Router IEEE/ACM Trans on etworking 1998(6), 237~ P. ewman, G. Minshall, L. Huston IP switching and gigabit routers IEEE Commun. Mag, 1997(1), 64~69 4. S. Keshav, R. Sharma "Issues and trends in router design." IEEE Communications Mag., May 1998, p Cisco Gigabit Switch Router, White Paper, Cisco Systems, Internet Backbone Routers and Evolving Internet Design, White Paper, Juniper etworks, Sept James Aweya IP Router Architectures: An Overview, White Paper ortel etworks. 8. A. F. J. Levi Optical Interconnects in Systems Proceedings of the IEEE 88, (2000). 9. Magnus Jonsson, Ulf Olin Optical interconnection technology in switches, routers and optical cross connects, White Paper, Ericsson, Oct Proc. SPIE Vol