Advanced Microprocessors RISC & DSP

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1 Advanced Microprocessors RISC & DSP RISC & DSP :: Slide 1 of 23

2 RISC Processors RISC stands for Reduced Instruction Set Computer Compared to CISC Simpler Faster RISC & DSP :: Slide 2 of 23

3 Why RISC? Complex instructions even a trend to adding direct support for HLL operations! Many addressing modes, microprogrammed Long (10-12 CPU cycles) and variable execution times e.g. Late 1970s VAX: 304 instructions, 16 addressing modes, 11 instruction lengths! RISC & DSP :: Slide 3 of 23

4 Why RISC? Found that 20% of instructions executed for 80% of the time Simplify Speed up Catalysts: Progress of optimising compiler technology Faster, cheaper memory ASIC technology instead of silicon fab equipment RISC & DSP :: Slide 4 of 23

5 RISC Properties Single word standard length of all instructions Usually 32 bit to allow sufficient addressing of 3-operand instructions Small number of instructions, perhaps 128 Small number of addressing modes, perhaps 4 All of these properties Simplify decoding and control logic Encourage hardwired ALUs - faster RISC & DSP :: Slide 5 of 23

6 RISC Properties Single cycle execution for all (or at least 80%) instructions Fast Facilitates pipelining Memory access by load & store instructions only Minimise number of instructions that must access memory during execution Encourages single cycle instructions RISC & DSP :: Slide 6 of 23

7 RISC Properties All operations except load and store are register-to-register Relatively large number (at least 32) of general-purpose CPU registers Sufficient for storing intermediate results Both properties minimise memory access Hardwired control unit Faster than microprogrammed RISC & DSP :: Slide 7 of 23

8 Current RISC Designs Most current high-performance processors are RISC Alpha ARM MIPS PowerPC SPARC not Intel Most are 32 bit Most have 64+ registers Most have dual primary cache (fetch both branches) Most use instruction pipelining Many are 2-issue superscalar (two execution units) RISC & DSP :: Slide 8 of 23

9 Are Intel Processors CISC or RISC? Both they are CISC with an underlying RISC core See processors-cisc-or-risc-or.html RISC & DSP :: Slide 9 of 23

10 DSP = Digital Signal Processor RISC & DSP :: Slide 10 of 23

11 Digital Signal Processing Digital Signal Processing Sample one or more physical signals (A/D) Operate on the digital representation of the signal(s) Output a physical representation of the result(s) (D/A) Do this repeatedly, rapidly, and to meet hard timing constraints RISC & DSP :: Slide 11 of 23

12 Typical Applications Low cost embedded systems Modem, mobile phone, HDD, automotive control Price sensitive, high volume High-performance applications Radar/sonar/seismic imaging, voice recognition Often (DSP) multiprocessor Computer-based multimedia Music synthesis, hi-fi audio, speech/audio/video compression and decompression RISC & DSP :: Slide 12 of 23

13 DSP vs. Analogue Circuits DSP implementations may have advantages: Predictable, repeatable behaviour Insensitive to environment temperature, etc. Insensitive to component tolerances Reprogrammability Component size advantages e.g. 100μF capacitor larger than 10pF RISC & DSP :: Slide 13 of 23

14 DSP Metrics Sample rate Sample rates required by applications range from < 1Hz to > 10 GHz Clock rate Typically 100 MHz or faster Numeric representation Floating point larger dynamic range, easier to program Fixed point faster, but more complicated programming RISC & DSP :: Slide 14 of 23

15 Common DSP Features Fast multiply & accumulate (MAC) operation Multiple-access (per cycle) memory architecture Specialized addressing modes Specialized execution control Instruction pipelining On-chip peripherals for I/O RISC & DSP :: Slide 15 of 23

16 Single-cycle MAC Multiply and accumulate (MAC) operation in one instruction cycle Most DSP algorithms (filtering, transforms, etc.) are multiplyintensive, involving sum-of-products terms DSPs provide multiplier and accumulator hardware in the processor data path Provide extra bits in the accumulator to guard against overflow of the accumulated result RISC & DSP :: Slide 16 of 23

17 Multiple-access Memory Architecture Ability to complete several memory accesses in a single cycle Needed for high performance numerically-intensive algorithms Multi-port on-chip memory Multiple on-chip busses Fetch instruction and operand simultaneously - Harvard architecture (separate instruction and data memory) RISC & DSP :: Slide 17 of 23

18 Specialized Addressing Dedicated address generators Once addressing registers loaded, address generation operates in the background Specialized addressing modes Register indirect with post-increment to support operations on sequential data Circular addressing to support operations on data buffers Bit-reversed addressing to support FFT algorithm RISC & DSP :: Slide 18 of 23

19 Specialized Execution Control Many DSP algorithms involve looping Supported by repeat instruction that allows looping without using cycles for testing the loop counter or jumping to the loop start May have fast context-switch, often using windowed registers May have low-latency interrupts RISC & DSP :: Slide 19 of 23

20 On-chip Peripherals All have on-chip serial and/or parallel interfaces May support off-chip A/D and D/A Fast synchronous serial (SPI) expansion is common All have a DMA mechanism Most have programmable timers Some have on-chip A/D and D/A e.g. DSPs designed for modems, mobile phones RISC & DSP :: Slide 20 of 23

21 DSP Embodiments Most are single-chip processors Package typically a QFP DSP cores DSP vendor licenses the DSP design DSP is fabricated on the same die as other circuitry to make a DSP-based ASIC Alternative: customizable DSP Expensive high volume only RISC & DSP :: Slide 21 of 23

22 DSP Embodiments Multi-chip modules MCMs comprise multiple dies in a single package e.g. TI has a MCM containing 2 DSPs and 128k SRAM Multi-processor ICs e.g. Zilog and Motorola both have parts containing a microcontroller and a DSP RISC & DSP :: Slide 22 of 23

23 References S.W. Smith. Digital Signal Processing: A Practical Guide for Engineers and Scientists. Newnes, Available online at Accessed 14/10/2015 To retrieve PDFs, edit the links as per the following example (case sensitive): > RISC & DSP :: Slide 23 of 23

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