Microprocessor Interfacing

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1 I 2 C Inter-Integrated Circuit Communication Microprocessor Interfacing Overview Specification Software Bit Banging Hardware Peripherals Typical System PIC SDA SCL INT 0 to 3.4 Mbps EEPROM Address Select Time-of-Day Thermometer Alarm Over Temperature Specification Multiple versions Version Up to 400 Kbps 10 bit addresses Version Up to 3.4 Mbps New signal levels for High-speed operation Version Some timing conditions relaxed SMBus Version 2.0 Relaxed version of I 2 C specification for power management (10 Kbps to 100 Kbps) Terminology Transmitter device that sends data to the bus Receiver device that accepts data from bus Master device which initiates a transfer, generates clock and terminates transfer with NAK Slave device addressed by master Multi-master more then one device attempts control of bus at one time without corrupting message Terminology Arbitration procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the winning message is not corrupted Synchronization procedure to synchronize the clock signals of two or more devices 1

2 Signals Levels Data Transfer on I 2 C-bus Float High (logic 1) Drive Low (logic 0) +5 V +5 V Float High Drive Low Start Data must be valid on SCL leading edge. stop Data Transfer on I 2 C-bus Signal Conditioning 10-bit Address 7-bit Address Pull-up Resistance Standard Mode Series Resistance Standard Mode 2

3 Other topics General call High-speed mode (Hs-mode) 0 to 3.4 Mbps Signal parameters Levels Timing Bit Banging Timing by cycle counting Use FSR and INDF so no RAM page swap overhead Delay macro helpful See code in text (section 17.6) Hardware Five hardware registers to support I 2 C SSP Control Register (SSPCON) SSP Status Register (SSPSTAT) SSP Receive/Transmit Buffer (SSPBUF) SSP Shift Register (not directly accessible) SSP Address Register (SSPADD) Hardware Modes Three mode of I 2 C supported (SSPM) 1000 I 2 C Master Mode 0111 I 2 C Slave Mode with 7-bit Address 0100 I 2 C Slave Mode with 10-bit Address Baud Rate Generator 100 Kbps 400 Kbps 1 Mbps SSP Master Mode Initialization Peripherals SSPSTAT=0; CKE=1; SSPCON=0x31 SSPIE=1; SSPIP=1; GIE=1; SSBUF=DataByte; //SMP = 0, CKE = 0, and clear status bits // Enable clock //Set up SPI port, Master mode, CLK/16, //Data xmit on falling edge (CKE=1 & CKP=1) //Data sampled in middle (SMP=0 & //Master mode) // Enable SSP interrupt //Enable as high-priority interrupt //interrupts in compatibility mode interrupts //Data to be Transmitted // Could move data from RAM location // Start Transmission Device Manufactures Microchip National Semiconductor XPS (Phillips) Seimens Xicor Zilog Devices Memory Clock / Calendar Bus Expanders LCD Controllers ADC Audio / Video Devices 3

4 24AA256 / 24LC256 / 24FC256 Characteristics 256 Kbit as 32 K by 8 Self timed 5 ms Erase / Write cycle 64-byte page write mode (5 ms cycle time) 100,000 Erase / Write cycles > 200 year data retention Transfer rates 400 Kbps for 24AA256 and 24LC256 1 Mbps 24FC256 Slave Address Byte Write S Start A Acknowledge P stop S Control In From Master A Address A Data A P From Slave Byte and Page Write Random and Sequential Read Write to Address Register Read Data Slave generates ACK Slave accepts data until stop. Give me more. That is enough.... More More More More Enough 4

5 ACLU #19 For XPS s PCF bit IO expander for I 2 C How many different PCF8574 devices can be on one I 2 C bus? How many clock cycles are required to read one byte? What is the purpose of the SDA line pull-up resistor? Homework Chapter 17 1 as written 3 as written 4 as written 5 as written 7 as written Summary Specification Software Bit Banging Hardware Peripherals 5

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