# Outline. Switched-Capacitor Circuits. Introduction (why and how) Integrators and filters Gain circuits Noise and charge injection INF4420

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1 INF4420 Switched-Capacitor Circuits Jørgen Andreas Michaelsen Spring / 42 Outline Introduction (why and how) Integrators and filters Gain circuits Noise and charge injection Spring 2013 Switched-Capacitor Circuits 2 2 / 42

2 Introduction Discrete time analog signal processing Why? Spring 2013 Switched-Capacitor Circuits 3 3 / 42 Introduction The arrangement of switches and the capacitor approximates a resistor. Spring 2013 Switched-Capacitor Circuits 4 4 / 42

3 Introduction Assuming steady-state, and arbitrarily assume V A > V B, T is one clock cycle. 1. At the beginning of φ 1, the capacitor voltage, V C, is at V B Volt 2. During φ 1, the capacitor is charged to V A. The charge transferred to the capacitor during φ 1 is ΔQ = C V A V B 3. During φ 2, ΔQ is transferred from the capacitor to B There is a net charge transfer, ΔQ, from A to B every period. This approximates a resistor, but the charge transfer is discrete. I = C V A V B T R eq = T C Spring 2013 Switched-Capacitor Circuits 5 5 / 42 Introduction RC accuracy (matching). Large time constants implies large passive components. With SC the time constant is set by capacitor ratio and clock frequency (both precisely controlled). Spring 2013 Switched-Capacitor Circuits 6 6 / 42

4 Introduction Resistive loading is undesirable in CMOS. Smallsignal gain: g m r o. When loaded with a resistor, r l, the gain is g m (r o r l ). I.e. the gain decreases. Spring 2013 Switched-Capacitor Circuits 7 7 / 42 Building blocks Spring 2013 Switched-Capacitor Circuits 8 8 / 42

5 Integrators Spring 2013 Switched-Capacitor Circuits 9 9 / 42 Discrete integrators Analyze each clock phase separately φ 1 φ 2 Spring 2013 Switched-Capacitor Circuits / 42

6 Discrete integrators Analyzing the charge transfer results in H z = C 1 z 1 C 2 1 z 1 = C 1 1 C 2 z 1 (Describes the output sampled at the end of φ 1 ) Delaying integrator (as we are multiplying with z 1 ) or equivalently from the time domain equation, the output now is given by the previous output and the previous input. Spring 2013 Switched-Capacitor Circuits / 42 Discrete integrators From the z-domain transfer function we find the frequency response. Assume the input frequency is T 1, we have H e jωt H 1 + jωt = C 1 C 2 1 jωt Compare to the continuous time case, Discrete time time constant H jω = 1 jωrc = 1 jωτ, gives discrete time, τ = C 1 C 2 1 T Spring 2013 Switched-Capacitor Circuits / 42

7 Discrete integrators The discrete time equivalent time constant is defined by the capacitor ratio and clock frequency. Allows precise time constant definition. Allows large time constants without excessively large passive components. Spring 2013 Switched-Capacitor Circuits / 42 Integrator parasitic capacitance Poorly controlled and non-linear H s = C 1 C 2 1 z 1 C 1 + C p1 C 2 1 z 1 Spring 2013 Switched-Capacitor Circuits / 42

8 Parasitic insensitive integrators Critical for performance Turn off first (bottom plate sampling) Again, we analyze the charge transfer from one clock phase to the next to find the transfer function. Spring 2013 Switched-Capacitor Circuits / 42 Parasitic insensitive integrators Almost the same as before (delaying integrator), but the added switches flips the capacitor positive gain. H z = C 1 C 2 1 z 1 Spring 2013 Switched-Capacitor Circuits / 42

9 Parasitic insensitive integrators The parasitic capacitors still affect settling, but not the signal charge transfer. Spring 2013 Switched-Capacitor Circuits / 42 Delay free integrator Same circuit as before, but modified clocking of the switches. C 2 v o nt = C 2 v o nt T 2 C 1v i nt = C 2 v o nt T C 1 v i nt v o n = v o n 1 C 1 C 2 v i n H z = V o z V i z = C 1 1 C 2 1 z 1 = C 1 z z 1 C 2 Spring 2013 Switched-Capacitor Circuits / 42

10 Signal flow graph analysis Now we have the fundamental building blocks (discrete time integrators), to realize filters. We need a more convenient tool to analyze large systems. Signal flow graph (SFG) analysis allows us to graphically analyze SC systems. Spring 2013 Switched-Capacitor Circuits / 42 Signal flow graph analysis H 1 z = V o z = C 1 V 1 z C A (inverting gain stage) H 2 (z) is the noninverting delaying integrator H 3 (z) is the inverting delay-free integrator Spring 2013 Switched-Capacitor Circuits / 42

11 SC filters A simple design strategy: Start with a continuous time prototype Replace resistors with SC resistor equivalents The resulting circuit is similar for input frequencies much lower than the sampling frequency Use SFG to determine the z-domain transfer function Accurate description of the transfer function Spring 2013 Switched-Capacitor Circuits / 42 First order filters Filter design example. Start with the continuous time circuit. In this case: Spring 2013 Switched-Capacitor Circuits / 42

12 First order filters Replace the resistors with SC elements Spring 2013 Switched-Capacitor Circuits / 42 First order filters Use Fig to find the SFG From this we find the z-domain transfer function H z = 1 C A C 2 +C 1 1 z 1 1+ C 3 C A z 1 Find pole and zero (stability) Frequency response, z = e jωt 1 + jωt Spring 2013 Switched-Capacitor Circuits / 42

13 Switch sharing Some switches are redundant, we use this to simplify the circuit: Spring 2013 Switched-Capacitor Circuits / 42 Biquad filters Ratio of two quadratic functions. In continuous time H s = k 2s 2 + k 1 s + k 0 s 2 + ω 0 Q s + ω 0 2 Spring 2013 Switched-Capacitor Circuits / 42

14 Low-Q biquad Spring 2013 Switched-Capacitor Circuits / 42 Low-Q biquad H z = K 2 + K 3 z 2 + K 1 K 5 K 2 2K 3 z + K K 6 z 2 + K 4 K 5 K 6 2 z + 1 Spring 2013 Switched-Capacitor Circuits / 42

15 Low-Q biquad A design strategy for determining capacitor sizing is outlined in the book High-Q transfer functions result in large capacitor spread (ratio of the smallest and largest capacitor) As before, we find the frequency response as H e jωt Spring 2013 Switched-Capacitor Circuits / 42 High-Q biquad Spring 2013 Switched-Capacitor Circuits / 42

16 High-Q biquad H z = K 3z 2 + K 1 K 5 + K 2 K 5 2K 3 z + K 3 K 2 K 5 z 2 + K 4 K 5 + K 5 K 6 2 z + 1 K 5 K 6 This transfer function turns out to be better suited for realizing high-q transfer functions (less spread). Spring 2013 Switched-Capacitor Circuits / 42 Gain Resettable gain circuit Samples offset voltage during reset (reduces flicker noise) Spring 2013 Switched-Capacitor Circuits / 42

17 Gain Amplifier slew-rate requirement is high. Spring 2013 Switched-Capacitor Circuits / 42 Capacitive-reset gain Include a capacitor to hold the output during the reset phase. Avoid excessive slewing. Configurable positive or negative gain. Spring 2013 Switched-Capacitor Circuits / 42

18 Noise Noise from the switch is sampled on the capacitor with the signal. Sampling the kt noise is like sampling any other C signal. The total noise power remains. Broadband noise alias back to the signal band. Spring 2013 Switched-Capacitor Circuits / 42 Noise In the delaying parasitic insensitive case, noise is sampled independently in φ 1 and φ 2, doubling the noise: 2kT C Spring 2013 Switched-Capacitor Circuits / 42

19 Correlated double sampling (CDS) We have already seen how opamp offset voltage can be sampled and canceled. Generally, this technique is known as correlated double sampling (CDS) Flicker noise is low frequency (assumed to be occurring at lower frequencies than the sampling frequency). Can model it as a randomly varying offset voltage also canceled Can be applied to different sampled systems Spring 2013 Switched-Capacitor Circuits / 42 Fully differential circuits Real circuits are almost always fully differential. Coupled noise, power supply noise, substrate noise will mostly affect the common mode, while our signal is in the differential mode. Also, cancels even order harmonics. Spring 2013 Switched-Capacitor Circuits / 42

20 Charge injection We discussed performance limitation of the switches in the context of sample and hold circuits. The same applies for SC. As we have seen, charge injection limits linearity. arrange the switching and clocking to minimize the signal dependent charge injection. Spring 2013 Switched-Capacitor Circuits / 42 Bootstrapped switch Generate a clock voltage such that V GS is constant (V in + V dd ). Better R on and alleviates charge injection problem. Increased complexity, and reliability can be problematic. Spring 2013 Switched-Capacitor Circuits / 42

21 SC amplifier design Unanswered questions (for now). How do we design amplifiers suitable for SC circuits? DC gain (static error) GBW (dynamic error) PM (stability) Slewing requirements C in (capacitive divider) Spring 2013 Switched-Capacitor Circuits / 42 Further reading Sansen, Analog Design Essentials, Springer, 2006, Ch. 17 Spring 2013 Switched-Capacitor Circuits / 42

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