Layout, Fabrication, and Elementary Logic Design

Transcription

1 Introduction to CMOS VLSI Design Layout, Fabrication, and Elementary Logic Design Adapted from Weste & Harris CMOS VLSI Design

2 Overview Implementing switches with CMOS transistors How to compute logic functions with switches Fabricating transistors on a silicon wafer and connecting them together Fabrication and Layout CMOS VLSI Design Slide 2

3 Silicon Lattice Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors Fabrication and Layout CMOS VLSI Design Slide 3

4 Dopants Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type) Fabrication and Layout CMOS VLSI Design Slide 4

5 p-n Junctions A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction Fabrication and Layout CMOS VLSI Design Slide 5

6 nmos Transistor Four terminals: gate, source, drain, body Gate oxide body stack looks like a capacitor Gate and body are conductors SiO 2 (oxide) is a very good insulator Fabrication and Layout CMOS VLSI Design Slide 6

7 nmos Operation Body is commonly tied to ground (0 V) When the gate is at a low voltage: Source-body and drain-body diodes are OFF No current flows, transistor is OFF Fabrication and Layout CMOS VLSI Design Slide 7

8 nmos Operation When the gate is at a high voltage: Positive charge on gate of MOS capacitor Negative charge attracted to body Inverts a channel under gate to n-type Now current can flow through n-type silicon from source through channel to drain, transistor is ON Fabrication and Layout CMOS VLSI Design Slide 8

9 pmos Transistor Similar, but doping and voltages reversed Body tied to high voltage (V DD ) Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior Fabrication and Layout CMOS VLSI Design Slide 9

10 Power Supply Voltage GND = 0 V In 1980 s, V DD = 5V V DD has decreased in modern processes High V DD would damage modern tiny transistors Lower V DD saves power V DD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, Fabrication and Layout CMOS VLSI Design Slide 10

11 Transistor Abstraction 3D structure formed by fabrication 2D planar layout view Schematic symbol Switch CMOS VLSI Design Slide 11

12 Transistors as Switches We can view MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain Fabrication and Layout CMOS VLSI Design Slide 12

13 Switching Logic conducts iff a b (0 only) a b a conducts iff a+b (0 only) s d s d a b b a s d s d conducts iff a' b' or (a+b)' (1 only) b conducts iff a'+b' or (a b)' (1 only) CMOS VLSI Design Slide 13

14 Implementation of Logic Gates OR gate a a b a + b 1 f(a,b) b Two problems 1) when a=b=0, f(a,b) is undefined (floating) 2) n- type switches do not conduct 1 well Two solutions when f=0, connect output to 0v using n-type switches when f=1, connect output to 1v using p-type switches CMOS VLSI Design Slide 14

15 Complementary CMOS Gates Pull-up network consisting of p-type devices Pull-down network consisting of n-type devices 1v (logic 1) P pull-up inputs output N pull-down Example: an inverter 0v (logic 0) a a' : a' : a a a' CMOS VLSI Design Slide 15

16 CMOS Inverter A Y 0 1 Fabrication and Layout CMOS VLSI Design Slide 16

17 CMOS Inverter A Y Fabrication and Layout CMOS VLSI Design Slide 17

18 CMOS Inverter A Y Fabrication and Layout CMOS VLSI Design Slide 18

19 CMOS NAND Gate A B Y Fabrication and Layout CMOS VLSI Design Slide 19

20 CMOS NAND Gate A B Y Fabrication and Layout CMOS VLSI Design Slide 20

21 CMOS NAND Gate A B Y Fabrication and Layout CMOS VLSI Design Slide 21

22 CMOS NAND Gate A B Y Fabrication and Layout CMOS VLSI Design Slide 22

23 CMOS NAND Gate A B Y Fabrication and Layout CMOS VLSI Design Slide 23

24 CMOS NOR Gate A B Y Fabrication and Layout CMOS VLSI Design Slide 24

25 3-input NAND Gate Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0 Fabrication and Layout CMOS VLSI Design Slide 25

26 3-input NAND Gate Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0 Fabrication and Layout CMOS VLSI Design Slide 26

27 Switch Logic vs. Gate Logic Example: two-input multiplexer a b 2:1 f f=a, when s=0 f=b, when s=1 f=s'a+sb s CMOS VLSI Design Slide 27

28 Switch Logic vs. Gate Logic Two-input mux with gate logic (14 transistors) Two-input mux with switch logic (6 transistors) complementary pass transistor CMOS VLSI Design Slide 28

29 Implementing LUTs Multiplexor logic simple switch network (a tree) inputs: programming bits controls: inputs to CLB output: function value However, series transistors are slow O(n 2 ) A' A B' Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 B C' C F CMOS VLSI Design Slide 29

30 Programmable Interconnect Switches connect wires at intersections Can also be used to segment wire Repeaters needed every so often simple non-inverting buffers (2 inverters) otherwise, too many switches in series slow down signal CMOS VLSI Design Slide 30

31 Master-Slave Register CMOS VLSI Design Slide 31

32 Dynamic Register CMOS VLSI Design Slide 32

33 Latch-Based Design Switches and/or gates compute new values to store on next clock cycle straightforward implementation CL φ 2 φ 1 this circuit can use the entire clock cycle no wasted time - a form of retiming CL CL φ 2 φ 1 CMOS VLSI Design Slide 33

34 Static Memory Cell 8-transistor cell N-transistor only: 6T cell bit bit' rd or wr (rd or wr)' CMOS VLSI Design Slide 34

35 Dynamic Memory Cell 1-transistor cell precharge to intermediate voltage level charge sharing with bus capacitance (C cell << C bus ) extra demands on sense amplifier to detect small changes in bus charge storage capacitor is one end of transistor destructive read (must immediately write back) CMOS VLSI Design Slide 35

36 Dynamic storage Capacitor implemented by gate capacitance of transistor No capacitor is perfect charge leaks away through imperfect switches Must be replenished or refreshed 'memory' lasts about 1ms Solution: periodically read the value and write it back CMOS VLSI Design Slide 36

37 Read-only Memory Cells To store constants or other invariant data Popular for control implementation read1 bit1 bit2 bit3 read2 programmable logic array structure (exploits distributed NOR gate structure) CMOS VLSI Design Slide 37

38 Multi-ported Register Cells Augment 6T cell for more I/O bus1 bus2' row-bus1 row-bus2 bus2 bus1' CMOS VLSI Design Slide 38

39 CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process Fabrication and Layout CMOS VLSI Design Slide 39

40 The wafer Czochralski process Melt silicon at 1425 C Add impurities (dopants) Spin and pull crystal Slice into wafers 0.25mm to 1.0mm thick Polish one side CMOS VLSI Design

41 CMOS VLSI Design

42 Crystal and wafer Wand (a finished 250lb crystal) A polished wafer CMOS VLSI Design

43 The mask Illuminate reticle on wafer Typically 4 reduction Typical image is 25 25mm Limited by focus Step-and repeat across wafer Limited by mechanical alignment 4X reticle Wafer CMOS VLSI Design

44 Lithography Patterning is done by exposing photoresist with light Requires many steps per layer Example: Implant layer CMOS VLSI Design Reference: FULLMAN KINETICS

45 Grow Oxide Layer CMOS VLSI Design Reference: FULLMAN KINETICS

46 Add Photoresist CMOS VLSI Design Reference: FULLMAN KINETICS

47 Mask CMOS VLSI Design Reference: FULLMAN KINETICS

48 Expose using UV Light CMOS VLSI Design Reference: FULLMAN KINETICS

49 Develop and Remove Resist CMOS VLSI Design Reference: FULLMAN KINETICS

50 Etch Silicon Dioxide CMOS VLSI Design Reference: FULLMAN KINETICS

51 Remove Resist CMOS VLSI Design Reference: FULLMAN KINETICS

52 Implant Dopant CMOS VLSI Design Reference: FULLMAN KINETICS

53 Inverter Cross-section Typically use p-type substrate for nmos transistor Requires n-well for body of pmos transistors Several alternatives: SOI, twin-tub, etc. Fabrication and Layout CMOS VLSI Design Slide 53

54 Inverter Layout Transistors and wires are defined by masks Cross-section taken along dashed line Fabrication and Layout CMOS VLSI Design Slide 54

55 Advanced Metallization - Copper CMOS VLSI Design Copper versus Aluminum ~ 40% lower resistivity ~ 10 less electromigration

56 A View of Interconnect Layers CMOS VLSI Design Slide 56

57 Package-to-Board Interconnect CMOS VLSI Design Digital Integrated Circuits 2nd

58 Flip-Chip Bonding CMOS VLSI Design Digital Integrated Circuits 2nd

59 Package Types CMOS VLSI Design Digital Integrated Circuits2nd

60 Multi-Chip Modules CMOS VLSI Design Digital Integrated Circuits 2nd