PERFORMANCE EVALUATION OF 4:1 MULTIPLEXER USING DIFFERENT DOMINO LOGIC STYLES

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1 International Journal of Electronics and Communication Engineering and Technology (IJECET) Volume 7, Issue 4, July-August 2016, pp , Article ID: IJECET_07_04_003 Available online at Journal Impact Factor (2016): (Calculated by GISI) ISSN Print: and ISSN Online: IAEME Publication PERFORMANCE EVALUATION OF 4:1 MULTIPLEXER USING DIFFERENT DOMINO LOGIC STYLES Mukherjee D. N. Department of Electronics and Communication Engineering, Bankura Unnayani Institute of Engineering, Bankura, India. Panda S. Department of Electronics and Communication Engineering, Narula Institute of Technology, Kolkata, India. Maji B. Department of Electronics and Communication Engineering, National Institute of Technology, Durgapur, India. ABSTRACT In the present scenario the low power and the speed play an important role in the field of digital VLSI circuits. The main objective of this paper is to design and implement of power consumption of 4:1 Multiplexer in various logic styles and compared in terms of power consumption and propagation delay. The results of this paper are simulated on the EDA tanner tools realized in 0.25-micrometer technology. Key words: Multiplexer, Low power, Speed, PE logic techniques, domino keeper technique, Inverter feedback technique. Cite this Article: Mukherjee D. N., Panda S and Maji B., Performance Evaluation of 4:1 Multiplexer using different Domino Logic Styles, International Journal of Electronics and Communication Engineering and Technology, 7(4), 2016, pp INTRODUCTION In the present scenario power consumption is an important aspect in digital VLSI circuits, where different techniques and technologies are used to design circuits for low power consumption with high speed interface applications are developed. The multiplexer is one of the most critical components of any arithmetic circuit. It has several applications including CPU, graphics controller, network switches, and 20

2 Performance Evaluation of 4:1 Multiplexer using different Domino Logic Styles DSP for shearing several signals to one device or resource within a certain amount of time and bandwidth. In this paper, a 4:1 multiplexer using different logic technique has been designed with low power consumption and higher packing densities and these implementations are compared based on power consumption and delay in 0.25-micrometer technology. 2. MULTIPLEXER The multiplexer is a combinational logic circuit, which has several inputs and one output. A multiplexer performs the function of selecting one of several inputs and transfer to the output by using a control bit word to its select lines. The multiplexer has 2 n number of data inputs with n number of selection inputs and a single output. The graphical symbol and switching operation of 4:1 multiplexer is shown in Figure 1. The multiplexer sometime is called date selector. The end result of 4:1 multiplexer appears in Table I for various facts situations. Figure 1.Graphical Symbol and Switching Operation of a 4:1 Multiplexer. Table I: Truth Table of 4:1 Multiplexer. Select lines Output S 0 S 1 Y 0 0 I I I I 3 Assume that we have four data inputs, I 0, I 1, I 2 and I 3, which are to be multiplexed on the output(y). One of the four inputs is direct to the output by using select lines S 0 and S 1 = (1) 21

3 Mukherjee D. N., Panda S and Maji B. Figure 2. Gate Implementation of a 4:1 Multiplexer The internal logic circuit of a 4:1 Multiplexer is shown in Figure.2. The output of the multiplexer is shown in Equation (1). 3. PRECHARGE AND EVALUATE LOGIC BASED 4:1 MULTIPLEXER Precharge and evaluate logic is working in two stages, one is precharge stage and another is evaluate stage. In the precharge stage the clock pulse is low, and during this stage the precharge PMOS is ON and the evaluate NMOS is OFF, so the output node is charged through the load capacitor. Hence it is impossible for the output to be driven low during this stage, so the output is independent on the driven inputs. In the evaluate stage the clock pulse is high. In this stage the output node may be discharged if inputs have configured a directing path to ground, otherwise the output node stays charged high. Inputs must be stable before the clock pulse goes high because once the output has been discharged it won t go high again until the next cycle. The 4:1 Multiplexer using Pre-charge and Evaluate logic technique appears in Figure 3. Figure 3.4:1 Multiplexer using the Pre-charge and Evaluate Logic Technique. 22

4 Performance Evaluation of 4:1 Multiplexer using different Domino Logic Styles 4. DESIGN OF 4:1 MULTIPLEXER USING KEEPER TECHNIQUE Possibly the easiest approach to improve the noise tolerance of dynamic CMOS logic gates is to utilize a weak transistor, known as keeper, at the dynamic node as appeared in Figure 4. The keeper transistor supplies a small amount of current from the power supply system to the dynamic node of a gate so that the charge put away in the dynamic node is maintained [1]. Dynamic circuit also suffers from charge leakage on the dynamic node. In the event that a dynamic node is pre-charged high and after that left floating the voltage on the dynamic node will drift over time due to sub threshold, gate and leakage junction. The time constant has a tendency to be in the millisecond to nanosecond range, contingent upon process and temperature. Also, dynamic circuits has poor input noise margin. On the off chance that the input increases above the threshold voltage while the gate is in evaluation, the input transistor will turn on weekly and can incorrectly discharge the output. Both leakage and noise margin issues can be tended to by including keeper circuit. At the point when the dynamic node X is high, the output Y is low and the keeper is ON to prevent X from floating. At the point when X falls, the keeper at first restricts the transition so it must be much weaker than the pull down network. In the end Y rises, turning the keeper OFF and avoiding the static power dissipation. The 4:1 multiplexer utilizing conventional week fixed keeper logic technique is appeared in Figure 4. Figure 4. 4:1 Multiplexer using Conventional week Fixed Keeper Logic Technique. 5. MULTIPLEXER USING INVERTER FEEDBACK TECHNIQUE To generate a feedback signal in inverter feedback technique a weak CMOS inverter is placed in such a way that the output of the weak CMOS inverter is connecting to the gate terminal of the PMOS keeper transistor instead of directly connecting gate output Y to the gate terminal of the PMOS keeper transistor. The 4:1 Multiplexer using the Inverter Feedback Technique is shown in Figure 5. In this technique the feedback keeper transistor becomes independent upon the output load. So the inverter feedback is optimizing freely without concerned about the gate output. In inverter feedback with diode footer technique an NMOS transistor with gate and drain 23

5 Mukherjee D. N., Panda S and Maji B. terminals connected together (diode footer) is connected in series with the pull-down NMOS network [2]. The 4:1 Multiplexer using inverter feedback with diode footer transistor is shown in Figure 6. Due to the stacking effect [3], the sub-threshold leakage of the pull-down path decreases to a great extent. The disadvantage associated with this is the diode footer makes the switching threshold voltage to increase, thereby affecting the performance of the domino circuit design. To overcome the problem mentioned above, we have designed a modified 4:1 multiplexer, which can improve the leakage and the speed of the circuit. In this modified circuit, M2 causes the stacking effect and makes gate-to source voltage of M1 smaller (M1 less conducting). Hence the circuit becomes less leakage power consuming. But performance degrades because of stacking effect in mirror current path. This can be increased by widening the M3 (high W/L) to make it more conducting [4]. The 4:1 Multiplexer using the modified inverter feedback technique is shown in Figure 7. Figure 5. 4:1 Multiplexer Design using the Inverter Feedback Technique. Figure 6. 4:1 Multiplexer using the Inverter Feedback with Diode Footer Transistor. 24

6 Performance Evaluation of 4:1 Multiplexer using different Domino Logic Styles Figure 7. 4:1 Multiplexer using the Modified Inverter Feedback Technique 6. SIMULATION RESULT The simulation result is measured by the EDA Tanner tool. We have examined our circuit for various inputs. The schematic circuit configuration of CMOS logic, proposed transmission gate logic based two-bit digital comparator and its output power waveform are appearing in Figure 8, 9, 10, 11,12, 13, 14, 15, 16 and 17 respectively. The simulated result is shown in Table II. Figure 8. Schematic of the 4:1 Multiplexer using the PE Logic Technique. 25

7 Mukherjee D. N., Panda S and Maji B. Figure 9. Simulation output Pattern of the 4:1 Multiplexer Design using the PE Logic Technique. Figure 10. Schematic of the 4:1 Multiplexer using the Conventional Weak Fixed Keeper. 26

8 Performance Evaluation of 4:1 Multiplexer using different Domino Logic Styles Figure 11.Simulation output Pattern of the 4:1 Multiplexer Design using the Conventional Weak Fixed Keeper Figure 12. Schematic of the 4:1 Multiplexer using the Inverter Feedback. 27

9 Mukherjee D. N., Panda S and Maji B. Figure 13. Simulation output Pattern of the 4:1 Multiplexer Design using the Inverter Feedback. Figure 14. Schematic of the 4:1 Multiplexer using the Inverter Feedback with Diode Footer Transistor. 28

10 Performance Evaluation of 4:1 Multiplexer using different Domino Logic Styles Figure 15. Simulation output Pattern of the 4:1 Multiplexer Design using the Inverter Feedback with Diode Footer Transistor. Figure 16. Schematic of the 4:1 Multiplexer using the Modified Inverter Feedback Technique. 29

11 Mukherjee D. N., Panda S and Maji B. Figure 17. Simulation output Pattern of the 4:1 Multiplexer Design using the Modified Inverter Feedback Technique. Table II: Performance Comparison of 4:1 Multiplexer. Parameters PE Logic Convention al Weak Fixed Keeper Inverter Feedback Inverter Feedback with Diode Footer Modified Inverter Feedback Power consumption (mw) Number of transistor Propagation Delay (n-sec) Power Delay Product (m-nj) CONCLUSIONS To enhance the performance of a 4:1 multiplexer we have designed a multiplexer using the modified inverter feedback technique. After simulation of all kinds of outline strategies, the last results are gotten for Power Consumption, Delay and Power Delay Product. Power consumption of the proposed 4:1 multiplexer is 0.032mW which is almost 45.67% less than existing inverter feedback technique based 4:1 multiplexer. It has been found that the power delay product is less in the modified circuit which is almost 45.76% less than existing inverter feedback technique based 4:1 multiplexer,. From the different analysis done on the basis of simulation result, we can conclude that the modified inverter feedback technique performs extremely well than other logic techniques. 30

12 Performance Evaluation of 4:1 Multiplexer using different Domino Logic Styles REFERENCES [1] Li Ding, Pinaki Mazumder On Circuit Techniques to Improve Noise Immunity of CMOS Dynamic Logic IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 9, SEPTEMBER 2004 [2] Hamid Mahmoodi-Meimand and Kaushik Roy, Diode-Footed Domino: A Leakage-Tolerant High Fan-in Dynamic Circuit Design Style, IEEE Transactions on Circuits and Systems-1, vol. 51, no. 3, pp , March [3] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, Leakage current mechanisms and leakage reduction techniques in deep-submicron CMOS circuits, Proc. IEEE, vol. 91, pp , Feb [4] Y. Varthamanan and V. Kannan, "Performance Evaluation of Reversible Logic Based CNTFET DeMultiplexer", International Journal of Electrical Engineering and Technology (IJEET), 4(3), 2013, pp [5] H.Mahmoodi -Meimand, Kauchic Roy, "A Leakage-Tolerant High Fan-in Dynamic circuit Design Style, IEEE Trans 2004 Y. Yorozu, M. Hirano, K. Oka, and Y. Tagawa, Electron spectroscopy studies on magneto-optical media and plastic substrate interface, IEEE Transl. J. Magn. Japan, vol. 2, pp , August 1987 [Digests 9th Annual Conf. Magnetics Japan, p. 301, 1982]. [6] Saradindu Panda, Supriyo Srimani, Prof. Bansibadan Maji and Prof. Asish Kumar Mukhopadhyay, High Performance Domino Full Adder Design under Different Body Biased Technology, International Journal of Advanced Research in Engineering and Technology (IJARET), 4(2), 2013, pp

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