Combinational Circuits #1
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1 ECE 322 Digital Design with VHDL Combinational Circuits # Lecture 8
2 Combinational Circuit Building Blocks n Commonly used combinational building blocks in design o larger circuits: Ø Multiplexers Ø Demultiplexers Ø Decoders Ø Encoders Ø Priority Encoders Ø Comparators Ø Arithmetic Circuits Caliornia State University
3 Register Transer Level (RTL) Design Today s Topic Combinational Logic Combinational Logic Registers The values o the outputs o a combinational circuit depend only on the values o the signals applied to the inputs Caliornia State University
4 Caliornia State University Multiplexers
5 Multiplexers log 2 n selection inputs n inputs output Ø n binary inputs (binary input = -bit input) Ø log 2 n binary selection inputs Ø binary output Ø Function: one o n inputs is placed onto output Called n-to- multiplexer Caliornia State University
6 2-to- Multiplexer s s w w w w (a) Graphical symbol (b) Truth table w w s s w w (c) Sum-o-products circuit (d) Circuit with transmission gates Caliornia State University
7 VHDL Code or 2-to- Multiplexer-Using when-else library ieee ; use ieee.std_logic_64.all; entity MUX2to is port(w, w, s : in std_logic; : out std_logic); end MUX2to; architecture behavior o MUX2to is begin <= w when s = '' else w; end behavior; Caliornia State University
8 VHDL Code or 2-to- Multiplexer-Using i-then-else library ieee ; use ieee.std_logic_64.all; entity MUX2to is port(w, w, s end MUX2to; : in std_logic; : out std_logic); architecture behavior o MUX2to is begin process(w, w, s) begin i s = then <= w; else <= w; end i end process; end behavior; Caliornia State University
9 Cascade o Two Multiplexers w 3 w 2 y w s2 s Caliornia State University
10 VHDL Code or Cascade o Two Multiplexers library ieee; use ieee.std_logic_64.all; entity mux_cascade is port ( w, w2, w3 : in std_logic; s, s2 : in std_logic; : out std_logic); end mux_cascade; architecture behavior o mux2to is begin <= w when s = ' else w2 when s2 = else w3; end behavior; Caliornia State University
11 4-to- Multiplexer s s w w (a) Graphic symbol s s w w (b) Truth table s s w w s s w w (d) 4-to- multiplexer implementation using 2-to- multiplexers (c) Circuit Caliornia State University
12 VHDL Code or 4-to- Multiplexer library ieee ; use ieee.std_logic_64.all; entity MUX4to is port(w, w, w2, w3 : in std_logic; s : in std_logic_vector( downto ); : out std_logic); end MUX4to; architecture behavior o MUX4to is begin with s select <= w when, w when, w2 when, w3 when others; end behavior; Caliornia State University
13 6-to- Multiplexer s s w w 4 s 2 s 3 w 7 w 8 w Caliornia State University w 5 Implementation using 4-to- Multiplexers
14 VHDL Code or 6-to- Multiplexer library ieee ; use ieee.std_logic_64.all; entity MUX6to is port(w : in std_logic_vector( to 5); s : in std_logic_vector(3 downto ); : out std_logic); end MUX6to; architecture structure o MUX6to is signal m : std_logic_vector( to 3); component MUX4to port(w, w, w2, w3: in std_logic; sel : in std_logic_vector( downto ); out : out std_logic); end component; begin MUX:MUX4to port map(w(), w(), w(2), w(3), s( downto ), m()); MUX2:MUX4to port map(w(4), w(5), w(6), w(7), s( downto ), m()); MUX3:MUX4to port map(w(8), w(9), w(), w(), s( downto ), m(2)); MUX4:MUX4to port map(w(2), w(3), w(4), w(5), s( downto ), m(3)); MUX5:MUX4to port map(m(), m(), m(2), m(3), s(3 downto 2), ); end structure; Caliornia State University
15 Synthesis o a Logic Function Using Multiplexers Caliornia State University
16 Two-Input XOR Function w w Two-input XOR unction implemented with a 4-to- multiplexer. w w w (b) Modiied truth table (c) Circuit Two-input XOR unction implemented with a 2-to- multiplexer. Caliornia State University
17 Three-Input Majority Function w w w (a) Modiied truth table (b) Circuit Implementation o the three-input majority unction using a 4-to- multiplexer. Caliornia State University
18 Three-Input XOR Function w w (a) Truth table (b) Circuit Three-input XOR unction implemented with a 4-to- multiplexer. Caliornia State University
19 Three-Input XOR Function w w (a) Truth table (b) Circuit Three-input XOR implemented with 2-to- multiplexers. Caliornia State University
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