Fundamentals of Computer Systems
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1 Fundamentals of Computer Systems Combinational Logic Martha A. Kim Columbia University Fall 23 /
2 Combinational Circuits Combinational circuits are stateless. Their output is a function only of the current input. Inputs Combinational Circuit Outputs 2 /
3 3 /
4 4 /
5 Overview: Enabler An enabler has two inputs: data: can be several bits, but bit examples for now enable/disable: bit on/off switch When enabled, the circuit s output is its input data. When disabled, the output is. ENABLE ENABLE X DATA OUTPUT X X DATA OUTPUT When enabled When disabled 5 /
6 Enabler Implementation Note abbreviated truth table: input, A, listed in output column EN F A EN F A A EN F EN A F In both cases, output is enabled when EN =, but they handle the disabled (EN = ) cases differently. 6 /
7 Encod 7 /
8 Overview: Decoder A decoder takes a k bit input and produces 2 k single-bit outputs. The input determines which output will be, all others. This representation is called one-hot encoding. O 3 I O 2 I O O 8 /
9 :2 Decoder The smallest decoder: one bit input, two bit outputs A A A 9 /
10 2:4 Decoder Decoder outputs are simply minterms. Those values can be constructed as a flat schematic (manageable at small sizes) or hierarchically, as below. B B :2 DEC B AB AB A A :2 DEC A AB A B /
11 3:8 Decoder Applying hierarchical design again, the 2:4 DEC helps construct a 3:8 DEC. A A :2 DEC A ABC ABC ABC B C BC BC 2:4 DEC BC B C AB C ABC ABC A BC A B C /
12 Implementing a function with a decoder E.g., F = AC + BC C B A F C B A F Warning: Easy, but not a minimal circuit. 2 /
13 Encoders and Decoders k bits 3:8 DEC 2 k bits BCD One-Hot k bits 3:8 ENC 2 k bits 3 /
14 Priority Encoder An encoder designed to accept any input bit pattern. I 3 I 2 I I V O O X X X X X X X X V = I 3 + I 2 + I + I O = I 3 + I 3 I 2 O = I 3 + I 3 I 2 I 4 /
15 5 /
16 Overview: Multiplexer (or Mux) A mux has a k bit selector input and 2 k data inputs (multi or single bit). It outputs a single data output, which has the value of one of the data inputs, according to the selector. D IN 3 C B IN 2 IN OUT B A IN S S 6 /
17 2: Mux Circuit There are a handful of implementation strategies. E.g., a truth table and k-map are feasible for a design of this size. S I I 7 /
18 2: Mux Circuit There are a handful of implementation strategies. E.g., a truth table and k-map are feasible for a design of this size. S I I I S I O
19 2: Mux Circuit There are a handful of implementation strategies. E.g., a truth table and k-map are feasible for a design of this size. S I I I S I :2 Decoder! Enabler! Enabler! O 7 /
20 4: Mux Circuit I 3 I 2 O I I EN 3 EN 2 EN EN 2:4 DEC S S 8 /
21 Muxing Wider Values (Overview) I 3 I 2 O I I EN 3 EN 2 EN EN 2:4 DEC S S 9 /
22 Muxing Wider Values (Components) X 3 X 2 X X Y 3 Y 2 Y Y EN X 3 X 2 X X Z 3 Z 2 Z Z Y 3 Y 2 Y Y 2 /
23 Using a Mux to Implement an Arbitrary Function Version Think of a function as using k input bits to choose from 2 k outputs. E.g., F = BC + AC A B C F F A B C
24 Using a Mux to Implement an Arbitrary Function Version Think of a function as using k input bits to choose from 2 k outputs. E.g., F = BC + AC A B C F F A B C 2 /
25 Using a Mux to Implement an Arbitrary Function Version 2 Can we use a smaller MUX? A B C F
26 Using a Mux to Implement an Arbitrary Function Version 2 Can we use a smaller MUX? A B C F
27 Using a Mux to Implement an Arbitrary Function Version 2 Can we use a smaller MUX? A B C F
28 Using a Mux to Implement an Arbitrary Function Version 2 Can we use a smaller MUX? A B C F A B F C C
29 Using a Mux to Implement an Arbitrary Function Version 2 Can we use a smaller MUX? A B C F A B F C C C 2 3 A B F Instead of feeding just or into the mux, as in Version, one can remove a bit from the select, and feed it into the data ports along with the constant. 22 /
30 23 /
31 Overview: Shifters A shifter shifts the inputs bits to the left or to the right. IN n SHIFTER k CNTL n OUT There are various types of shifters. Barrel: Selector bits indicate (in binary) how far to the left to shift the input. L/R with enable: Two control bits (upper enables, lower indicates direction). In either case, bits may roll out or wraparound 24 /
32 Example: Barrel Shifter with Wraparound 8 SHIFTER /
33 Implementation of Barrel Shifter with Wraparound (Part 2) Main idea: wire up all possible shift amounts and use muxes to select correct one. IN 3 IN 2 IN IN OUT 3 OUT 2 OUT OUT
34 Implementation of Barrel Shifter with Wraparound (Part 2) Main idea: wire up all possible shift amounts and use muxes to select correct one. IN 3 IN 2 IN IN CNTL, CNTL OUT 3 OUT 2 OUT OUT
35 Implementation of Barrel Shifter with Wraparound (Part 2) Main idea: wire up all possible shift amounts and use muxes to select correct one. IN 3 IN 2 IN IN CNTL, CNTL OUT 3 OUT 2 OUT OUT
36 Implementation of Barrel Shifter with Wraparound (Part 2) Main idea: wire up all possible shift amounts and use muxes to select correct one. IN 3 IN 2 IN IN CNTL, CNTL OUT 3 OUT 2 OUT OUT
37 Implementation of Barrel Shifter with Wraparound (Part 2) Main idea: wire up all possible shift amounts and use muxes to select correct one. IN 3 IN 2 IN IN CNTL, CNTL OUT 3 OUT 2 OUT OUT
38 Implementation of Barrel Shifter with Wraparound (Part 2) Main idea: wire up all possible shift amounts and use muxes to select correct one. IN 3 IN 2 IN IN CNTL, CNTL OUT 3 OUT 2 OUT OUT 26 /
39 27 /
40 Computation Always Takes Time 74LS There is a delay between inputs and outputs, due to: Limited currents charging capacitance The speed of light 28 /
41 The Simplest Timing Model In Out t p Each gate has its own propagation delay t p. When an input changes, any changing outputs do so after t p. Wire delay is zero. 29 /
42 A More Realistic Timing Model In Out t p(max) t p(min) It is difficult to manufacture two gates with the same delay; better to treat delay as a range. Each gate has a minimum and maximum propagation delay t p(min) and t p(max). Outputs may start changing after t p(min) and stablize no later than t p(min). 3 /
43 Critical Paths and Short Paths A B C D Y How slow can this be? 3 /
44 Critical Paths and Short Paths A B C D Y How slow can this be? The critical path has the longest possible delay. t p(max) = t p(max, AND) + t p(max, OR) + t p(max, AND) 3 /
45 Critical Paths and Short Paths A B C D Y How fast can this be? The shortest path has the least possible delay. t p(min) = t p(min, AND) 3 /
46 Glitches A glitch is when a single change in input values can cause multiple output changes. A B F C Glitches may occur when there are multiple paths of different length from input I to output O.
47 Glitches A glitch is when a single change in input values can cause multiple output changes. A B F C Glitches may occur when there are multiple paths of different length from input I to output O.
48 Glitches A glitch is when a single change in input values can cause multiple output changes. A B F C Glitches may occur when there are multiple paths of different length from input I to output O.
49 Glitches A glitch is when a single change in input values can cause multiple output changes. A B F C Glitches may occur when there are multiple paths of different length from input I to output O. 32 /
50 Preventing Single Input Glitches Additional terms can prevent single input glitches (at a cost of a few extra gates). B C A A B F C 33 /
51 Preventing Single Input Glitches Additional terms can prevent single input glitches (at a cost of a few extra gates). B C A A B F C 33 /
52 Ari 34 /
53 Arithmetic: Addition Adding two one-bit numbers: A and B Produces a two-bit result: C and S (carry and sum) A B C S A B Half Adder C S 35 /
54 Full Adder In general, due to a possible carry in, you need to add three bits: C o C i A B C o S C i A B C o S C i A B S 36 /
55 A Four-Bit Ripple-Carry Adder A B A 3 B 3 A 2 B 2 A B A B C o FA C i FA FA FA FA S S 4 S 3 S 2 S S 37 /
56 A Two s Complement Adder/Subtractor To subtract B from A, add A and B. Neat trick: carry in takes care of the + operation. A 3 B 3 A 2 B 2 A B A B SUBTRACT/ADD FA FA FA FA S 4 S 3 S 2 S S 38 /
57 Overflow in Two s-complement Representation When is the result too positive or too negative? /
58 Overflow in Two s-complement Representation When is the result too positive or too negative? % + % + The result does not fit when the top two carry bits differ. A n Bn A n Bn S n S n % Overflow 39 /
59 Ripple-Carry Adders are Slow A3 B3 A2 B2 A B A B C C4 S3 S2 S S The depth of a circuit is the number of gates on a critical path. This four-bit adder has a depth of 8. n-bit ripple-carry adders have a depth of 2n. 4 /
60 Carry Generate and Propagate The carry chain is the slow part of an adder; carry-lookahead adders reduce its depth using the following trick: C A B K-map for the carry-out function of a full adder For bit i, C i+ = A i B i + A i C i + B i C i = A i B i + C i (A i + B i ) = G i + C i P i Generate G i = A i B i sets carry-out regardless of carry-in. Propagate P i = A i + B i copies carry-in to carry-out. 4 /
61 Carry Lookahead Adder Expand the carry functions into sum-of-products form: C i+ = G i + C i P i C = G + C P C 2 = G + C P = G + (G + C P )P = G + G P + C P P C 3 = G 2 + C 2 P 2 = G 2 + (G + G P + C P P )P 2 = G 2 + G P 2 + G P P 2 + C P P P 2 C 4 = G 3 + C 3 P 3 = G 3 + (G 2 + G P 2 + G P P 2 + C P P P 2 )P 3 = G 3 + G 2 P 3 + G P 2 P 3 + G P P 2 P 3 + C P P P 2 P 3 42 /
62 The Binary Carry-Lookahead Adder (From National Semiconductor) B4 A4 2 9 C4 Σ4 Carry out i has i + product terms, largest of which has i + literals. 5 B3 4 A3 3 Σ3 If wide gates don t slow down, delay is independent of number of bits. 2 B2 3 A2 6 B 5 A 7 C Σ2 4 Σ More realistic: if limited to two-input gates, depth is O(log 2 n). 43 /
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