# 3. Implementing Logic in CMOS

Save this PDF as:

Size: px
Start display at page:

## Transcription

1 3. Implementing Logic in CMOS Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2016 August 31, 2016 ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

2 Static CMOS Circuits N- and P-channel Networks N- and P-channel networks implement logic functions Each network connected between Output and V DD or V SS Function defines path between the terminals ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

3 Duality in CMOS Networks Straightforward way of constructing static CMOS circuits is to implement dual N- and P- networks N- and P- networks must implement complementary functions Duality sufficient for correct operation (but not necessary) ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

4 Constructing Complex Gates Example: F = (A B) + (C D) 1 Take uninverted function F = (A B) + (C D) and derive N-network 2 Identify AND, OR components: F is OR of AB, CD 3 Make connections of transistors ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

5 Construction of Complex Gates, Cont d 4 Construct P-network by taking complement of N-expression (AB + CD), which gives the expression, (A + B) (C + D) 5 Combine P and N circuits ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

6 Layout of Complex Gate AND-OR-INVERT (AOI) gate Note: Arbitrary shapes are not allowed in some nanoscale design rules CE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

7 Example of Compound Gate F = (A + B + C) D) Note: N- and P- graphs are duals of each other In this case, the function is the complement of the switching function between F and GND Question: Does it make any difference to the function if the transistor with input D is connected between the parallel A, B, C, transistors and GND? What about the electrical behavior? ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

8 Example of More Complex Gate OUT = (A + B) (C + D) (E + F + (G H)) ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

9 Example of More Complex Gate OUT = (A + B) (C + D) (E + F + (G H)) ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

10 Exclusive-NOR Gate in CMOS Note: designs such as these should be checked very carefully for correct behavior using circuit simulation ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

11 Pseudo nmos Logic Based on the old NMOS technology where a depletion transistor was used as a pullup resistor What happens when there is no path from Z to ground (i.e., Z = 1)? What happens when there is a path from Z to ground (i.e., Z = 0)? ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

12 Duality is Not Necessary for a CMOS Structure Functions realized by N and P networks must be complementary, and one of them must conduct for every input combination F = a b+a b+a c+c d+c d The N and P networks are NOT duals, but the switching functions they implement are complementary CE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

13 Example of Another Complex CMOS Gate This circuit does not have a pmos network just one transistor for each function; it will work only if F and G are complements of each other. Why? Can evaluate the voltages at F and G ({0,V DD }) for each value of x, y, and z F = x y z+x y z+x y z+x y z G = x y z+x y z+x y z+x y z ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

14 Example of Another Complex CMOS Gate This circuit does not have a pmos network just one transistor for each function; it will work only if F and G are complements of each other. Why? Can evaluate the voltages at F and G ({0,V DD }) for each value of x, y, and z F = x y z+x y z+x y z+x y z G = x y z+x y z+x y z+x y z ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

15 Example of Another Complex CMOS Gate, Cont d Can also follow every path from F and G to GND and identify values of x, y, and z which will enable the path to be enabled. F = x y + x y z + x y z F = (x + y) (x + y + z) (x + y + z) = (y + x z) (x + y + z) = x y + y z + x z G = x y z + x y z + x y = x y + x z + y z Can you describe the functions in simple terms? (Hint: look at the number of input variables which are true (or false) when the output is 1.) CE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

16 Example of Another Complex CMOS Gate, Cont d Can also follow every path from F and G to GND and identify values of x, y, and z which will enable the path to be enabled. F = x y + x y z + x y z F = (x + y) (x + y + z) (x + y + z) = (y + x z) (x + y + z) = x y + y z + x z G = x y z + x y z + x y = x y + x z + y z Can you describe the functions in simple terms? (Hint: look at the number of input variables which are true (or false) when the output is 1.) CE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

17 Example of Another Complex CMOS Gate, Cont d Can also follow every path from F and G to GND and identify values of x, y, and z which will enable the path to be enabled. F = x y + x y z + x y z F = (x + y) (x + y + z) (x + y + z) = (y + x z) (x + y + z) = x y + y z + x z G = x y z + x y z + x y = x y + x z + y z Can you describe the functions in simple terms? (Hint: look at the number of input variables which are true (or false) when the output is 1.) CE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

18 Signal Strength Voltages represent digital logic values Strength of signal: How close it approximates ideal voltage V DD and GND rails are strongest 1 and 0 nmos transistors pass a strong 0 But degraded or weak 1 pmos transistors pass a strong 1 But degraded or weak 0 Therefore, nmos transistors are best for the pull-down network ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

19 Pass Transistors and Transmission Gates Transistors can be used as switches; however, they could produce degraded outputs Transmission gates pass both 0 and 1 well ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

20 Pass Transistor Logic Pull-Up Circuit Used to restore degraded logic 1 from output of nmos pass transistor ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

21 Pass Transistor Logic Better Layout Group similar transistors, so they can be in the same well ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

22 Tristates Tristate Buffer produces Z (high impedance) when not enabled EN A Y 0 0 Z 0 1 Z Non-Restoring Tristate Transmission gate acts as a tristate buffer Only two transistors, but nonrestoring Noise on A is passed to Y ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

23 Tristate Inverter Tristate inverter produces restored output, but complements signal A A A EN EN Y Y Y EN = 0 Y = 'Z' EN = 1 Y = A ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

24 Multiplexers S D1 D0 Y 0 X X X X 1 How many transistors are needed? (The better design uses 3 NAND gates and 1 inverter) CE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

25 Transmission Gate MUX Nonrestoring MUX Uses two transmission gates = only 4 transistors Inverting MUX adds an inverter Uses compound gate AOI22 Alternatively, a pair of tristate inverters (same thing) ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

26 4:1 Multiplexer A 4:1 MUX chooses one of 4 inputs using two selects Two levels of 2:1 MUXes Alternatively, four tristates ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

27 D Latch Basic Memory Element When CLK = 1, latch is transparent D flows through to Q like a buffer When CLK = 0, the latch is opaque Q holds its old value independent of D a.k.a., transparent latch or level-sensitive latch ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

28 D Latch, Cont d D Latch Design: MUX chooses between D and old Q D Latch Operation ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

29 D Flip-Flop (D-Flop) Another common storage element When CLK rises, D is copied to Q At all other times, Q holds its value positive edge-triggered flip-flop or master-slave flip-flop Built from master and slave D latches ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

30 D Flip-Flop Operation ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

31 Race Condition Hold Time Failure Back-to-back flops can malfunction from clock skew Second flip-flop fires late Sees first flip-flop change and captures its result Called hold-time failure or race condition ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

32 Non-Overlapping Clocks A simple way to prevent races This works as long as non-overlap exceeds clock skew Used in safe (conservative) designs Industry does not generally use this approach managing skew more carefully instead CE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

33 Gate Layout Building a library of standard cells Layout can be time consuming One solution is to have layouts of commonly used functions (Inverter, NAND, OR, MUX, etc.), designed to fit together very well Standard cell design methodology V DD and GND should abut (standard height) Adjacent gates should satisfy design rules nmos at bottom and pmos at top All gates include well and substrate contacts One of the large industry suppliers is ARM (which purchased ARTISAN) ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

34 Examples of Standard Cell Layout Inverter NAND3 Horizontal N-diffusion and P-diffusion strips Vertical Polysilicon gates Metal1 V DD rail at top, Metal1 GND rail at bottom 32λ by 40λ CE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

35 Wiring Tracks and Well Spacing Wiring Track is the space required for a wire Example, 4λ width, 4λ spacing from neighbor = 8λ pitch Transistors also consume one wiring track Example, well spacing: wells must surround transistors by 6λ Implies 12λ between opposite transistor flavors Leaves room for one wire track CE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

36 Example of Area Estimation Estimate area by counting wiring tracks Multiply by 8 to express in λ Estimating area of O3AI Sketch a stick diagram and estimate area ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

37 Example Circuit 1 Fill in the Karnaugh map to represent the Boolean function implemented by the pass-transistor circuit. ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

38 Example Circuit 1 a F(a,b,c,d,e): e c e b d ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, /

39 Example Circuit 2 Find the function, F, implemented by the following circuit A + BC + B C ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

40 Example Circuit 2 Find the function, F, implemented by the following circuit A + BC + B C ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

41 Example Circuit 3 Find the functions X and Y implemented by the following circuit ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

42 Example Circuit 3 Find the functions X and Y implemented by the following circuit ECE Department, University of Texas at Austin Lecture 3. Implementing Logic in CMOS Jacob Abraham, August 31, / 1

### CMOS Digital Circuits

CMOS Digital Circuits Types of Digital Circuits Combinational The value of the outputs at any time t depends only on the combination of the values applied at the inputs at time t (the system has no memory)

### Introduction to CMOS VLSI Design

Introduction to CMOS VLSI esign Slides adapted from: N. Weste,. Harris, CMOS VLSI esign, Addison-Wesley, 3/e, 24 Introduction Integrated Circuits: many transistors on one chip Very Large Scale Integration

### EEC 116 Lecture #6: Sequential Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 116 Lecture #6: Sequential Logic Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 3 extended, same due date as Lab 4 HW4 issued today Amirtharajah/Parkhurst,

### Lecture 10: Sequential Circuits

Introduction to CMOS VLSI esign Lecture 10: Sequential Circuits avid Harris Harvey Mudd College Spring 2004 Outline q Sequencing q Sequencing Element esign q Max and Min-elay q Clock Skew q Time Borrowing

### Lecture 11: Sequential Circuit Design

Lecture 11: Sequential Circuit esign Outline Sequencing Sequencing Element esign Max and Min-elay Clock Skew Time Borrowing Two-Phase Clocking 2 Sequencing Combinational logic output depends on current

### Lecture 10 Sequential Circuit Design Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010

EE4800 CMOS igital IC esign & Analysis Lecture 10 Sequential Circuit esign Zhuo Feng 10.1 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010 Sequencing Outline Sequencing Element esign Max and Min-elay

### Sequential Circuits. Combinational Circuits Outputs depend on the current inputs

Principles of VLSI esign Sequential Circuits Sequential Circuits Combinational Circuits Outputs depend on the current inputs Sequential Circuits Outputs depend on current and previous inputs Requires separating

### ECE124 Digital Circuits and Systems Page 1

ECE124 Digital Circuits and Systems Page 1 Chip level timing Have discussed some issues related to timing analysis. Talked briefly about longest combinational path for a combinational circuit. Talked briefly

### Sequential Logic. References:

Sequential Logic References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey, Prentice Hall UCB Principles of CMOS VLSI Design: A Systems Perspective, N. H. E. Weste, K. Eshraghian,

### 5. Sequential CMOS Logic Circuits

5. Sequential CMOS Logic Circuits In sequential logic circuits the output signals is determined by the current inputs as well as the previously applied input variables. Fig. 5.1a shows a sequential circuit

### Sequential 4-bit Adder Design Report

UNIVERSITY OF WATERLOO Faculty of Engineering E&CE 438: Digital Integrated Circuits Sequential 4-bit Adder Design Report Prepared by: Ian Hung (ixxxxxx), 99XXXXXX Annette Lo (axxxxxx), 99XXXXXX Pamela

### Sequential Logic: Clocks, Registers, etc.

ENEE 245: igital Circuits & Systems Lab Lab 2 : Clocks, Registers, etc. ENEE 245: igital Circuits and Systems Laboratory Lab 2 Objectives The objectives of this laboratory are the following: To design

### Lecture 5: Gate Logic Logic Optimization

Lecture 5: Gate Logic Logic Optimization MAH, AEN EE271 Lecture 5 1 Overview Reading McCluskey, Logic Design Principles- or any text in boolean algebra Introduction We could design at the level of irsim

### Sequential Circuits. Prof. MacDonald

Sequential Circuits Prof. MacDonald Sequential Element Review l Sequential elements provide memory for circuits heart of a state machine saving current state used to hold or pipe data data registers, shift

### Chapter 10 Advanced CMOS Circuits

Transmission Gates Chapter 10 Advanced CMOS Circuits NMOS Transmission Gate The active pull-up inverter circuit leads one to thinking about alternate uses of NMOS devices. Consider the circuit shown in

### Sequential Circuit Design

Sequential Circuit Design Lan-Da Van ( 倫 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2009 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines

### Topics of Chapter 5 Sequential Machines. Memory elements. Memory element terminology. Clock terminology

Topics of Chapter 5 Sequential Machines Memory elements Memory elements. Basics of sequential machines. Clocking issues. Two-phase clocking. Testing of combinational (Chapter 4) and sequential (Chapter

### DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 5. LECTURE: SEQUENTIAL CIRCUITS BASICS AND FLIP-FLOPS

DIGITAL TECHNICS Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 5. LECTURE: SEQUENTIAL CIRCUITS BASICS AND FLIP-FLOPS 1st (Autumn) term 2014/2015 5. LECTURE 1. Sequential

### NEW adder cells are useful for designing larger circuits despite increase in transistor count by four per cell.

CHAPTER 4 THE ADDER The adder is one of the most critical components of a processor, as it is used in the Arithmetic Logic Unit (ALU), in the floating-point unit and for address generation in case of cache

### Lecture 12: MOS Decoders, Gate Sizing

Lecture 12: MOS Decoders, Gate Sizing MAH, AEN EE271 Lecture 12 1 Memory Reading W&E 8.3.1-8.3.2 - Memory Design Introduction Memories are one of the most useful VLSI building blocks. One reason for their

### 9. Memory Elements and Dynamic Logic

9. Memory Elements and RS Flipflop The RS-flipflop is a bistable element with two inputs: Reset (R), resets the output Q to 0 Set (S), sets the output Q to 1 2 RS-Flipflops There are two ways to implement

### Latches, the D Flip-Flop & Counter Design. ECE 152A Winter 2012

Latches, the D Flip-Flop & Counter Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR

### Lecture 10. Latches and Flip-Flops

Logic Design Lecture. Latches and Flip-Flops Prof. Hyung Chul Park & Seung Eun Lee Sequential Logic Outputs of sequential logic depend on current inputs and prior input values Sequential logic might explicitly

### Fabrication and Manufacturing (Basics) Batch processes

Fabrication and Manufacturing (Basics) Batch processes Fabrication time independent of design complexity Standard process Customization by masks Each mask defines geometry on one layer Lower-level masks

### Layout and Cross-section of an inverter. Lecture 5. Layout Design. Electric Handles Objects. Layout & Fabrication. A V i

Layout and Cross-section of an inverter Lecture 5 A Layout Design Peter Cheung Department of Electrical & Electronic Engineering Imperial College London V DD Q p A V i V o URL: www.ee.ic.ac.uk/pcheung/

### Standard cell libraries are required by almost all CAD tools for chip design

Standard Cell Libraries Standard cell libraries are required by almost all CAD tools for chip design Standard cell libraries contain primitive cells required for digital design However, more complex cells

### Flip-Flops. Outline: 2. Timing noise

Outline: 2. Timing noise Flip-Flops Signal races, glitches FPGA example ( assign bad) Synchronous circuits and memory Logic gate example 4. Flip-Flop memory RS-latch example D and JK flip-flops Flip-flops

### Module-3 SEQUENTIAL LOGIC CIRCUITS

Module-3 SEQUENTIAL LOGIC CIRCUITS Till now we studied the logic circuits whose outputs at any instant of time depend only on the input signals present at that time are known as combinational circuits.

### Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.

Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. describe how such a flip-flop can be SET and RESET. describe the disadvantage

### EE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad

A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/20 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,

### ECE410 Design Project Spring 2008 Design and Characterization of a CMOS 8-bit Microprocessor Data Path

ECE410 Design Project Spring 2008 Design and Characterization of a CMOS 8-bit Microprocessor Data Path Project Summary This project involves the schematic and layout design of an 8-bit microprocessor data

### 1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1.

File: chap04, Chapter 04 1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1. 2. True or False? A gate is a device that accepts a single input signal and produces one

### Low Power VLSI Circuits and Systems Prof. Pro. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur

Low Power VLSI Circuits and Systems Prof. Pro. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture No. # 14 Pass Transistor Logic Circuits - I Hello

### Outline. Introduction Interconnect Modeling Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters. 4th Ed.

Lecture 14: Wires Outline Introduction Interconnect Modeling Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters 2 Introduction Chips are mostly made of wires called interconnect

### Module 4 : Propagation Delays in MOS Lecture 20 : Analyzing Delay in few Sequential Circuits

Module 4 : Propagation Delays in MOS Lecture 20 : Analyzing Delay in few Sequential Circuits Objectives In this lecture you will learn the delays in following circuits Motivation Negative D-Latch S-R Latch

### Clocking. Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 Clocks 1

ing Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 s 1 Why s and Storage Elements? Inputs Combinational Logic Outputs Want to reuse combinational logic from cycle to cycle 6.884 - Spring 2005 2/18/05

### Enhancement Mode MOSFET Circuits

Engineering Sciences 154 Laboratory Assignment 4 Enhancement Mode MOSFET Circuits Note: This is quite a long, but very important laboratory assignment. Take enough time - at least two laboratory sessions

### Unit 4 Session - 15 Flip-Flops

Objectives Unit 4 Session - 15 Flip-Flops Usage of D flip-flop IC Show the truth table for the edge-triggered D flip-flop and edge-triggered JK flip-flop Discuss some of the timing problems related to

### Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng

Digital Logic Design Basics Combinational Circuits Sequential Circuits Pu-Jen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction

### Sequential Circuits: Latches & Flip-Flops

Sequential Circuits: Latches & Flip-Flops Sequential Circuits Combinational Logic: Output depends only on current input Able to perform useful operations (add/subtract/multiply/encode/decode/ select[mux]/etc

### ECE380 Digital Logic

ECE38 igital Logic Flip-Flops, Registers and Counters: Flip-Flops r.. J. Jackson Lecture 25- Flip-flops The gated latch circuits presented are level sensitive and can change states more than once during

### An astable multivibrator acts as an oscillator (clock generator) while a monostable multivibrator can be used as a pulse generator.

Concepts In sequential logic, the outputs depend not only on the inputs, but also on the preceding input values... it has memory. Memory can be implemented in 2 ways: Positive feedback or regeneration

### Introduction to CMOS VLSI Design Lecture 6: Wires

Introduction to CMOS VLSI Design Lecture 6: Wires David Harris Harvey Mudd College Spring 2004 1 Outline Introduction Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters

### Introduction to CMOS VLSI Design (E158) Lecture 8: Clocking of VLSI Systems

Harris Introduction to CMOS VLSI Design (E158) Lecture 8: Clocking of VLSI Systems David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University MAH

### DIGITAL SYSTEM DESIGN LAB

EXPERIMENT NO: 7 STUDY OF FLIP FLOPS USING GATES AND IC S AIM: To verify various flip-flops like D, T, and JK. APPARATUS REQUIRED: Power supply, Digital Trainer kit, Connecting wires, Patch Chords, IC

Module 7 : I/O PADs Lecture 33 : I/O PADs Objectives In this lecture you will learn the following Introduction Electrostatic Discharge Output Buffer Tri-state Output Circuit Latch-Up Prevention of Latch-Up

### Gates, Circuits, and Boolean Algebra

Gates, Circuits, and Boolean Algebra Computers and Electricity A gate is a device that performs a basic operation on electrical signals Gates are combined into circuits to perform more complicated tasks

### 3 Flip-Flops. The latch is a logic block that has 2 stable states (0) or (1). The RS latch can be forced to hold a 1 when the Set line is asserted.

3 Flip-Flops Flip-flops and latches are digital memory circuits that can remain in the state in which they were set even after the input signals have been removed. This means that the circuits have a memory

### CHAPTER 16 Memory Circuits

CHAPTER 16 Memory Circuits Introduction! The 2 major logic classifications are! Combinational circuits: Their output depends only on the present value of the input. These circuits do not have memory.!

### Logic Gates & Operational Characteristics

Logic Gates & Operational Characteristics NOR Gate as a Universal Gate The NOR gate is also used as a Universal Gate as the NOR Gate can be used in a combination to perform the function of a AND, OR and

### Memory Elements. Combinational logic cannot remember

Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic

Digital design of Low power CMOS D-Latch basic K.Prasad Babu 1, S.Ahmed Basha 2, H.Devanna 3, K.Suvarna 4 1,2,3,4 Assistant Professor, St.Jonhs College of Engineering & Technology, Yemmiganur Abstract:

### Figure 2.1(a) Bistable element circuit.

3.1 Bistable Element Let us look at the inverter. If you provide the inverter input with a 1, the inverter will output a 0. If you do not provide the inverter with an input (that is neither a 0 nor a 1),

### Here we introduced (1) basic circuit for logic and (2)recent nano-devices, and presented (3) some practical issues on nano-devices.

Outline Here we introduced () basic circuit for logic and (2)recent nano-devices, and presented (3) some practical issues on nano-devices. Circuit Logic Gate A logic gate is an elemantary building block

### Digital Integrated Circuits EECS 312

14 12 10 8 6 Fujitsu VP2000 IBM 3090S Pulsar 4 IBM 3090 IBM RY6 CDC Cyber 205 IBM 4381 IBM RY4 2 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium II(DSIP) 0 1950 1960 1970 1980

### Chapter 7. Digital IC-Design. Overview. Sequential Logic. Latch versus Register. Clocking. Dynamic Latches Registers -C 2 MOS -NORA -TSPC.

igital IC-esign Overview Chapter 7 Sequential Logic Static es Registers Clocking ynamic es Registers -C 2 MOS -ORA -TSPC Sequential Logic versus Register Logic Registers es Flip-flops : Level Sensitive

### DC Noise Immunity of CMOS Logic Gates

DC Noise Immunity of CMOS Logic Gates Introduction The immunity of a CMOS logic gate to noise signals is a function of many variables, such as individual chip differences, fan-in and fan-out, stray inductance

### ENGIN 112 Intro to Electrical and Computer Engineering

ENGIN 112 Intro to Electrical and Computer Engineering Lecture 19 Sequential Circuits: Latches Overview Circuits require memory to store intermediate data Sequential circuits use a periodic signal to determine

### Combinatorial and Sequential CMOS Circuits Dr. Lynn Fuller Webpage:

ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Combinatorial and Sequential CMOS Circuits Webpage: http://people.rit.edu/lffeee 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585)

### Lecture 7: Clocking of VLSI Systems

Lecture 7: Clocking of VLSI Systems MAH, AEN EE271 Lecture 7 1 Overview Reading Wolf 5.3 Two-Phase Clocking (good description) W&E 5.5.1, 5.5.2, 5.5.3, 5.5.4, 5.5.9, 5.5.10 - Clocking Note: The analysis

### Latches and Flip-Flops

Latches and Flip-Flops Introduction to sequential logic Latches SR Latch Gated SR Latch Gated Latch Flip-Flops JK Flip-flop Flip-flop T Flip-flop JK Master-Slave Flip-flop Preset and Clear functions 7474

### ENGN3213. Digital Systems & Microprocessors. CLAB 2: Sequential Circuits, ICARUS Verilog

Department of Engineering Australian National University ENGN3213 Digital Systems & Microprocessors CLAB 2: Sequential Circuits, ICARUS Verilog V3.0 Copyright 2010 G.G. Borg ANU Engineering 1 Contents

### CSE140: Components and Design Techniques for Digital Systems

CE4: Components and esign Techniques for igital ystems Tajana imunic osing ources: Where we are now What we ve covered so far (Chap -5, App. A& B) Number representations Boolean algebra OP and PO Logic

VIDYARTHIPLUS - Anna University Students Online Community CS-6201-DIGITAL PRINCIPLE AND SYSTEM DESIGN TWO MARKS II-SEMESTER ANNA UNIVERSITY REGULATIONS 2013 UNIT I BOOLEAN ALGEBRA AND LOGIC GATES 1. Define

### CDA 3200 Digital Systems. Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012

CDA 3200 Digital Systems Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012 Outline SR Latch D Latch Edge-Triggered D Flip-Flop (FF) S-R Flip-Flop (FF) J-K Flip-Flop (FF) T Flip-Flop

### Chapter 4. Gates and Circuits. Chapter Goals. Chapter Goals. Computers and Electricity. Computers and Electricity. Gates

Chapter Goals Chapter 4 Gates and Circuits Identify the basic gates and describe the behavior of each Describe how gates are implemented using transistors Combine basic gates into circuits Describe the

### Sequential Logic. (Materials taken from: Principles of Computer Hardware by Alan Clements )

Sequential Logic (Materials taken from: Principles of Computer Hardware by Alan Clements ) Sequential vs. Combinational Circuits Combinatorial circuits: their outputs are computed entirely from their present

### Latch Timing Parameters. Flip-flop Timing Parameters. Typical Clock System. Clocking Overhead

Clock - key to synchronous systems Topic 7 Clocking Strategies in VLSI Systems Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Clocks help the design of FSM where

### l What have discussed up until now & why: l C Programming language l More low-level then Java. l Better idea about what s really going on.

CS211 Computer Architecture l Topics Digital Logic l Transistors (Design & Types) l Logic Gates l Combinational Circuits l K-Maps Class Checkpoint l What have discussed up until now & why: l C Programming

### Module 4 : Propagation Delays in MOS Lecture 22 : Logical Effort Calculation of few Basic Logic Circuits

Module 4 : Propagation Delays in MOS Lecture 22 : Logical Effort Calculation of few Basic Logic Circuits Objectives In this lecture you will learn the following Introduction Logical Effort of an Inverter

### Pass Gate Logic An alternative to implementing complex logic is to realize it using a logic network of pass transistors (switches).

Pass Gate Logic n alternative to implementing complex logic is to realize it using a logic network of pass transistors (switches). Switch Network Regeneration is performed via a buffer. We have already

### CSEE 3827: Fundamentals of Computer Systems. Latches and Flip Flops

EE 3827: Fundamentals of omputer ystems Latches and Flip Flops ombinational v. sequential logic Inputs ombinational circuit Outputs Inputs ombinational circuit next state Outputs current state torage elements

### Class 11: Transmission Gates, Latches

Topics: 1. Intro 2. Transmission Gate Logic Design 3. X-Gate 2-to-1 MUX 4. X-Gate XOR 5. X-Gate 8-to-1 MUX 6. X-Gate Logic Latch 7. Voltage Drop of n-ch X-Gates 8. n-ch Pass Transistors vs. CMOS X-Gates

CMOS Binary Full Adder A Survey of Possible Implementations Group : Eren Turgay Aaron Daniels Michael Bacelieri William Berry - - Table of Contents Key Terminology...- - Introduction...- 3 - Design Architectures...-

### 7. Latches and Flip-Flops

Chapter 7 Latches and Flip-Flops Page 1 of 18 7. Latches and Flip-Flops Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can store one bit of information. The

### Design of Digital Systems II Sequential Logic Design Principles (1)

Design of Digital Systems II Sequential Logic Design Principles (1) Moslem Amiri, Václav Přenosil Masaryk University Resource: Digital Design: Principles & Practices by John F. Wakerly Introduction Logic

### So far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs.

equential Logic o far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs. In sequential logic the output of the

### Gates & Boolean Algebra. Boolean Operators. Combinational Logic. Introduction

Introduction Gates & Boolean lgebra Boolean algebra: named after mathematician George Boole (85 864). 2-valued algebra. digital circuit can have one of 2 values. Signal between and volt =, between 4 and

### Sequential Circuits: Latches & Flip-Flops

ESD I Lecture 3.b Sequential Circuits: Latches & Flip-Flops 1 Outline Memory elements Latch SR latch D latch Flip-Flop SR flip-flop D flip-flop JK flip-flop T flip-flop 2 Introduction A sequential circuit

### Lecture 10: Latch and Flip-Flop Design. Outline

Lecture 1: Latch and Flip-Flop esign Slides orginally from: Vladimir Stojanovic Computer Systems Laboratory Stanford University horowitz@stanford.edu 1 Outline Recent interest in latches and flip-flops

### The components. E3: Digital electronics. Goals:

E3: Digital electronics Goals: Basic understanding of logic circuits. Become familiar with the most common digital components and their use. Equipment: 1 st. LED bridge 1 st. 7-segment display. 2 st. IC

### Design and Analysis of D Flip Flop Using Different Technologies

Design and Analysis of D Flip Flop Using Different Technologies Hardeep Kaur, Er.Swarnjeet Singh, Sukhdeep Kaur M.Tech Student, Dept. of ECE, Baba Farid College of Engineering &Technology, Bathinda, Punjab,

### 14:332:231 DIGITAL LOGIC DESIGN. Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 2013

4:332:23 DIGITAL LOGIC DEIGN Ivan Marsic, utgers University Electrical & Computer Engineering Fall 23 Lecture #5: equential Circuits: Latches equential Circuits Combinational circuits: current input output

### True Single Phase Clocking Flip-Flop Design using Multi Threshold CMOS Technique

True Single Phase Clocking Flip-Flop Design using Multi Threshold CMOS Technique Priyanka Sharma ME (ECE) Student NITTTR Chandigarh Rajesh Mehra Associate Professor Department of ECE NITTTR Chandigarh

### CHAPTER 11 LATCHES AND FLIP-FLOPS

CHAPTER 11 LATCHES AND FLIP-FLOPS This chapter in the book includes: Objectives Study Guide 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop

### Chapter 2 Logic Gates and Introduction to Computer Architecture

Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are

### Introduction. Logic. Most Difficult Reading Topics. Basic Logic Gates Truth Tables Logical Functions. COMP370 Introduction to Computer Architecture

Introduction LOGIC GATES COMP370 Introduction to Computer Architecture Basic Logic Gates Truth Tables Logical Functions Truth Tables Logical Expression Graphical l Form Most Difficult Reading Topics Logic

### Digital Logic Design

Digital Logic Design: An Embedded Systems Approach Using VHDL Chapter 1 Introduction and Methodology Portions of this work are from the book, Digital Logic Design: An Embedded Systems Approach Using VHDL,

### ANALOG & DIGITAL ELECTRONICS

ANALOG & DIGITAL ELECTRONICS Course Instructor: Course No: PH-218 3-1-0-8 Dr. A.P. Vajpeyi E-mail: apvajpeyi@iitg.ernet.in Room No: #305 Department of Physics, Indian Institute of Technology Guwahati,

### Unit # 3 BASICS OF DIGITAL CMOS DESIGN 1 COMBINATIONAL MOS LOGIC CIRCUITS

Unit # 3 BASICS OF DIGITAL CMOS DESIGN 1 COMBINATIONAL MOS LOGIC CIRCUITS 1.1 INTRODUCTION The Combinational logic circuits, or gates, perform Boolean operations on multiple input variables and determine

### NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter

NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter Description: The NTE2053 is a CMOS 8 bit successive approximation Analog to Digital converter in a 20 Lead DIP type package which uses a differential

### Synchronous Sequential Logic. Logic and Digital System Design - CS 303 Erkay Savaş Sabanci University

Synchronous Sequential Logic Logic and Digital System Design - S 33 Erkay Savaş Sabanci University Sequential Logic Digital circuits we have learned, so far, have been combinational no memory, outputs

### Register File, Finite State Machines & Hardware Control Language

Register File, Finite State Machines & Hardware Control Language Avin R. Lebeck Some slides based on those developed by Gershon Kedem, and by Randy Bryant and ave O Hallaron Compsci 04 Administrivia Homework

### 2 : BISTABLES. In this Chapter, you will find out about bistables which are the fundamental building blocks of electronic counting circuits.

2 : BITABLE In this Chapter, you will find out about bistables which are the fundamental building blos of electronic counting circuits. et-reset bistable A bistable circuit, also called a latch, or flip-flop,

### Alpha CPU and Clock Design Evolution

Alpha CPU and Clock Design Evolution This lecture uses two papers that discuss the evolution of the Alpha CPU and clocking strategy over three CPU generations Gronowski, Paul E., et.al., High Performance

### International Journal of Electronics and Computer Science Engineering 1482

International Journal of Electronics and Computer Science Engineering 1482 Available Online at www.ijecse.org ISSN- 2277-1956 Behavioral Analysis of Different ALU Architectures G.V.V.S.R.Krishna Assistant

### Experiment 5. Arithmetic Logic Unit (ALU)

Experiment 5 Arithmetic Logic Unit (ALU) Objectives: To implement and test the circuits which constitute the arithmetic logic circuit (ALU). Background Information: The basic blocks of a computer are central