ENEE244 (sec ) Spring Time alloted: 50 minutes. Student ID: Maximum score: 50 points


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1 ENEE244 (sec 4) Spring 26 Midterm Examination II Pages: 7 printed sides Name: Answer key Time alloted: 5 minutes. Student ID: Maximum score: 5 points University rules dictate strict penalties for any form of academic dishonesty. Looking sideways will be penalized. Look at only your own exam at all times. There are 6 questions, some with subparts. Read them carefully to avoid throwing away points!! Write your answer in the space provided. Closed book, closed notes, no calculators. Partial credit rule: Must show your intermediate steps clearly for partial credit!. For each subpart (i) to (v) below, circle all correct answers from among the four given  note that more than one answer may be correct! (2 points * 5 = points) (i) Regarding the minimum form of a combinational circuit, (a) the minimum in sumofproducts always has the same number of literals as the minimum in productofsums. (b) it may be the same size as the canonical form of the circuit. (c) the minimum form in sumofproducts is always unique. (d) it can only be smaller if some minterms in the canonical form are converted to don t cares and the rest are retained as in the original function. (ii) A gated SR latch (a) has only one combination of inputs that remembers the previous state. (b) can be built using NAND gates alone. (c) has no input combinations that result in unpredictable operation. (d) changes state only on the negative edge of the clock pulse.
2 (iii) A masterslave JK flipflop (a) stores inputs to the master only when the clock input is one. (b) changes output only on a particular edge of the clock pulse. (c) has no input combinations that result in unpredictable operation. (d) can have its operation completely specified by a truth table. (iv) A Dlatch provides the following functionality: (a) Set (make output=). (b) Reset (make output=). (c) Retain state. (d) Toggle (complement) state. (v) A ninput decoder with enable input (a) can be used to implement any Boolean function of n inputs. (b) is identical to a demultiplexer of a certain size. (c) is a combinational circuit. (d) is a good fit for building the keyboard interface circuit for a cell phone to convert buttonpress events into binary numbers. 2
3 2. Minimize the 3input function Σm(3,4,7) + dc(,5,6) using a Kmap. (a) Express the answer in sumofproducts form. (4 + 3 = 7 points). Since this function is in canonical form, we can directly fill the Kmap instead of going through the truth table. Kmap: x yz X X X F min = x + z. (b) Recompute the minimum form in productofsums form. For product of sums we combine the s on the Kmap. x yz X X X F min = x z (F min ) = (x z ) F min = x + z. x + z is unusual in that it is an expression in both productofsums and sumofproducts. 3
4 3. Draw the Kmap for the 4input function F(a,b,c,d) = Σm(5,6,7,8,9,,3,4,5). List all the essential prime implicants, as well as the nonessential prime implicants. Write all the minimum sumofproducts forms of the function. ( points) cd ab Prime implicants: m5,m7,m3,m5 : m6,m7,m4,m5: m8,m9: m8,m: m9,m3: m,m4: Essential (induced by m5) // term is bd Essential (induced by m6). // term is bc Nonessential (all minterms included in other PIs). // term is ab c Nonessential (all minterms included in other PIs). // term is ab d Nonessential (all minterms included in other PIs). // term is ac d Nonessential (all minterms included in other PIs). // term is acd Minimum functions contain all essential PIs and only those nonessential PIs needed to cover minterms not covered by essentials. Minterms not covered by essential PIs: m2,m3 and m4. These three minterms can be covered by three combinations of two nonessential PIs, resulting in three possible minimum functions. (i) bc + bd + ab c + ab d (ii) bc + bd + ab c + acd (iii) bc + bd + ac d + ab d All the above forms are equivalent and any one can be used to implement the function. 4
5 4. Design a circuit that takes a fourbit input A = a 4 a 3 a 2 a which checks if A is a prime number. Use a 6to in your design. Recall that a number A is prime if the only numbers that divide it with no remainder are and A itself. ( and are defined as not prime). (6 points) Among the fourbit number to 5, the prime numbers are 2,3,5,7,,3. The prime number checker is therefore simply Σm(2,3,5,7,,3). This is implemented as with a by connecting the included minterms to, rest to : to selects f a 4 a 3 a 2 a In this circuit, f= when A is prime; otherwise f=. 5
6 5. Construct an 8to using any number of 4to and 2to s as building blocks. Use the smallest number of component s that you can. (8 points) In the circuit below for the 8to, I I 7 are the data inputs; S 2, S, S are the selects. I I I 2 I 3 4 to S S 2 to Output I 4 I 5 I 6 I 7 4 to S 2 S S There is another correct solution which uses four 2to s at the first level selected by S, and one 4to at the second level, selected by S 2 and S. This solution uses more s than the above solution, but the s are of smaller size, so it may be just as good. Both solutions get full credit. 6
7 6. We wish to design a prefix detector circuit that takes two 6bit inputs A=a 5 a and B= b 5 b. The output should be a 6bit number C= c 5 c which has a at the first position from the right at which A and B are unequal. For example: A = B = Therefore: C= Here A and B are identical for bits  but not a bit ; hence c =. All the other outputs are zero. Design a prefixdetector (PD) cell such that 6 PDcells linked together compose the entire circuit. Show how the PD cells should be linked. You do not need to formally minimize your outputs using Kmaps, just use your intuition and, if necessary, Boolean simplification. (8 points) Let A i = a i a. Similarly define B i and C i. PDcell inputs: a i, b i and e i, where e i (A i = B i ). PDcell outputs: c i and e i+. We express the outputs in terms of the inputs: c i is true if a i b i and e i is true. c i = (a i b i ). e i. //XOR is inequality checker. e i+ is true if (a i = b i ) and e i. e i+ = (a i b i ). e i. //XNOR is equality checker. The 6 PDcells are linked such that the output e of stage i is linked to the input e of stage i+. Moreover e= (vacuously true), and e7 is discarded. a 6 b 6 a i b i a b e i+ (discarded) e 7 PD i e 6 PD i e i e 2 PD c 6 c i c 7
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