Theory of Logic Circuits. Laboratory manual. Exercise 11

Transcription

1 Zakła Mikroinformatyki i Teorii Automatów Cyfrowych Theory of Logic Circuits Laboratory manual Exercise mplementing Logic Functions Using M Multiplexers an emultiplexers 8 Tomasz Poeszwa, Piotr Czekalski (et.)

2 Ex.. mplementing Logic Functions Using M Multiplexers an emultiplexers. Multiplexer an emultiplexer Overview.. Multiplexer A Multiplexer (MUX) is a circuit that is use to irect one out of n inputs to a single output. t is also calle ata elector because n-input select lines are use to select one of the input signals an irect it to the output. A block iagram of 4-to- line Multiplexer with enable input is shown in Fig. an truth table for it in Fig.. MUX OUT O Fig.. Block iagram of a 4-to- line Multiplexer O X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Fig.. Truth table of a 4-to- line Multiplexer ince the enable input has negation symbol at its input in the block iagram, enables evice an isables the evice. ince the output line has no negation symbol, when the evice is isable, the output signal O is. When the evice is enable, the evice output signal O follows the ata input signal selecte by select lines an. Fig. shows the functional logic iagram for 4-to- MUX with enable input. Page of

3 Ex.. mplementing Logic Functions Using M Multiplexers an emultiplexers Fig.. Functional logic iagram for a 4-to- MUX with an enable input O maller Multiplexers can be connecte together to obtain larger configuration. Fig. 4 illustrates in block iagram form how five 4-to- Multiplexers can be connecte to obtain 6-to- Multiplexer O 4 5 Fig. 4. A 6-to- line Multiplexer constructe from five 4-to- line Multiplexers Page of

4 Ex.. mplementing Logic Functions Using M Multiplexers an emultiplexers.. emultiplexer A emultiplexer (MUX) is a circuit that receives a signal on a single input line an irects that signal to one of n possible output lines. f the enable input is active, we can also call this circuit a n-to n ecoer. A block iagram of -to-4 line emultiplexer is shown in Fig. 5a. A functional logic iagram for the evice is shown in Fig. 5b an truth table for it is shown in Fig. 6. MUX (a) O (b) Fig. 5. Block iagram for a -to-4 line emultiplexer (a) an its functional logic iagram (b) X X Fig. 6. Truth table of a -to-4 line emultiplexer Page 4 of

5 Ex.. mplementing Logic Functions Using M Multiplexers an emultiplexers ABLE O O O O Fig. 7. A -to-6 line emultiplexer constructe from five -to-4 line emultiplexers Like Multiplexers, smaller emultiplexers can also be connecte together to obtain larger configuration. Fig. 7 illustrates in block iagram form how five -to-4 line emultiplexers can be connecte to obtain a -to-6 line emultiplexer. Observe that ABLE signal is activate when input line is high (instea of emultiplexer shown in Fig. 5).. mplementing Logic Functions Using M Multiplexers When a Multiplexer is use to implement a logic function, that function oes not nee to be minimize in the normal manner; however, a minimize function consisting of only a single literal or a single prouct term woul be more cost-effective using a gate-lever esign. Usually logic esigners use truth tables to implement logic functions with Multiplexers. To illustrate the process, the following function will be implemente using a Multiplexer: F(a,b,c,)=Σ(4,5,6,7,,4) abc.. mplementing for Type. A type MUX esign require no signal in the truth table representing the function to be partitione off. This means, that all signals are applie to the select inputs. Also the characteristic numbers of the function are applie to the ata inputs. For the specifie function liste above, the characteristic numbers are f =, f =, f =, f =, f 4 =, f 5 =, f 6 =, f 7 =, f 8 =, f 9 =, f =, f =, f =, f =, f 4 =, f 5 = (see Fig. 9a). Page 5 of

6 Ex.. mplementing Logic Functions Using M Multiplexers an emultiplexers MUX OUT F MUX OUT F a b c a b c (a) (b) Fig. 9. mplementation for type 6-to- Multiplexer esign for function F f a Multiplexer has negation on the output an nvertor must be inclue on the output of the Multiplexer or characteristic numbers applie to ata inputs must be complemente (see Fig. 9b). Page 6 of

7 Ex.. mplementing Logic Functions Using M Multiplexers an emultiplexers.. mplementing for Type. A type MUX esign requires one signal to be partitione off. Continuing with the same function F, the truth table is now rawn an partitione as shown in Fig..The select inputs are inepenent signals a,b,c, an the ata inputs are the values (the subfunctions) in the truth table. The reuce output column in Fig. represents the output states as function of the partitioneoff input signal. The reuce outputs in the truth table consist of a set of subfunctions of the signal that is partitione off in the truth table. n this case, eight subfunctions are require where each subfunction is written as function of, that is, F(). The implementation for type Multiplexer esign is shown in Fig.. a b c F F Fig.. Truth table partitione for a type MUX esign MUX OUT F a b c Fig.. mplementation for a type MUX esign. Page 7 of

8 Ex.. mplementing Logic Functions Using M Multiplexers an emultiplexers.. mplementing for Type an. Fig. a an b illustrate truth table partitioning for a type an Multiplexer esign respectively. The two signals c an are partitione off for a type MUX esign, while the three signals b, c, an are partitione off for a type MUX esign. Fig. a an b show the implementation for a type an type MUX esign. a b c F F c c (a) a b c F F b c (b) Fig.. Truth table partitione for a type (a) an a type (b) MUX esign. MUX MUX b c c c OUT F c OUT c a b a (a) (b) Fig.. mplementation for a type (a) an type (b) MUX esign. F. mplementing Logic Functions Using M emultiplexers ince emultiplexers o not suffer from a lack of outputs like Multiplexers o, emultiplexer implementations are normally carrie out for Boolean functions with multiple outputs. Using a emultiplexer with n select inputs with an external OR elements connecte to the appropriate outputs of a emultiplexer any Boolean function of n variables can be implemente. f k Boolean functions are to be implemente using a emultiplexer, k external OR elements can be require. Page 8 of

9 Ex.. mplementing Logic Functions Using M Multiplexers an emultiplexers.. Example esign a 4-bit binary-to-gray coe converter with the truth table shown in Fig. 4. b b b b g g g g Fig. 4. The truth table a 4-bit binary-to-gray coe converter. We can write the Boolean functions for the outputs of the coe converter in terms of the inputs as follows. g=σ(8,9,,,,,4,5) bbbb g=σ(4,5,6,7,8,9,,) bbbb g=σ(,,4,5,,,,) bbbb g=σ(,,5,6,9,,,4) bbbb ince there are four bits of input information require to etermine the minterms, a -to-6 line emultiplexer is utilize as shown in Fig. 5 (note that OR element symbols shown in the figure are the emorgan equivalent symbol for NAN gates). Page 9 of

10 Ex.. mplementing Logic Functions Using M Multiplexers an emultiplexers b b b b M U X E N g g g g Fig. 5. esign a 4-bit binary-to-gray coe converter using -to-6 emultiplexer an three NAN elements. Notice in the esign in example above that there are the same number of s in each gray coe function as there are s. When esigning with emultiplexers, it is important to count the number of s an s in function. f there are fewer s, the function is best implemente using the miniterm compact form for the s of the function; however, if there are fewer s, the function is best implemente using miniterm compact form for the s. A circuit implemente with fewer minterms requires gates with less input lines an takes less wiring... Example Obtain the functional logic iagram for the following functions using one -to-6 emultiplexer without output inverters. F = Σ(,,5,8,) abc F = Π(,7,8,,4,5) abc F = Σ(,,4,5,7,8,,,,4,5) abc F 4 = Π (,,,6,7,8,,,,5) abc olution Because functions F an F 4 are presente in maxterm compact form, we must convert them to miniterm form. F = Σ (,,,4,5,6,9,,,) abc F 4 = Σ (,4,5,9,,4) abc n the secon step we count s an s in each function: functions F an F have less s than s, so for this functions are better implemente using miniterm compact form for the s (see Fig. 6). Page of

11 Ex.. mplementing Logic Functions Using M Multiplexers an emultiplexers c b a M U X E N F 4 F F F Fig. 6. esign functions F, F, F, an F 4 using -to-6 emultiplexer. 4. mplementing Logic Functions Using emultiplexers an Multiplexers A type (an higher) MUX esign requires two or more signal to be partitione off. Using this signals are create set of functions which are connecte to input lines of Multiplexer. Example below presents this problem an its solution. Page of

12 Ex.. mplementing Logic Functions Using M Multiplexers an emultiplexers 4.. Example Obtain the functional logic iagram for the following function using one -to-4 emultiplexer an 8-to- Multiplexer. F= Σ(,,4,6,9,,,6,7,8,9,,,5,6,,) abce olution Karnaugh table for function F is shown in Fig. 7 (signals an e are partitione off in the Karnaugh map) an implementation for this function in Fig. 8. e abc F ~e ~~e e 6 e 7 5 e 4 Fig. 7. Karnaugh table for example e MUX MUX OUT F a b c Fig. 8. mplementation for function F Where ~ sign stans for complementary operator. Page of

13 Ex.. mplementing Logic Functions Using M Multiplexers an emultiplexers 5. Tasks to be performe uring laboratory. Obtain function F, F, F, F 4 using one -to-6 emultiplexer (with invertors on output lines) an NAN elements. F = Π (,5,6,9,) abc F = Σ (,6,9,,,) abc F = Σ(,,,5,6,8,9,,,4,5) abc F 4 = Π (,,5,6,7,9,,,4,5) abc. Obtain function Z=ab(c+(~c))+~((~a)(~c)+bc)+(~b)c(~) using: a. one 6-to- line Multiplexer (using a type esign) b. one 8-to- line Multiplexer an inverter element (using a type esign) c. one 4-to- line Multiplexer an NAN or nverter elements (using a type esign). one -to- line Multiplexer an NAN or nverter elements (using a type esign) e. one 4-to- line Multiplexer an -to-4 line emultiplexer an NAN or nverter elements (using a type esign with emultiplexer) 6. nstructions to follow. olve all tasks before the exercise.. mplement the circuits specifie by your supervisor (using given elements).. Present working circuits to your supervisor for acceptance. Page of