Chapter 4 Combinational Logic
|
|
|
- Alexis Dennis
- 7 years ago
- Views:
Transcription
1 Chapter 4 Combinational Logic Chih-Tsun Huang ( 黃稚存 ) Department of Computer Science National Tsing Hua University Outline Introduction Combinational Circuits Analysis Procedure Design Procedure Binary Adder-Subtractor Binary Multiplier Magnitude Comparator Decoder and Encoder Multiplexer Fall 2010 CS2102 Chih-Tsun Huang 2
2 Logic Circuits for the Digital System Combinational circuits Logic circuits whose outputs at any time are determined directly and only from the present input combination Sequential circuits (Chapter 5) Circuits that employ memory elements + (combinational) logic gates Outputs are determined from the present input combination as well as the state of the memory cells Fall 2010 CS2102 Chih-Tsun Huang 3 Analysis Procedure Analysis for an available logic diagram Make sure the given circuit is combinational No feedback path or memory element Derive the corresponding Boolean functions Derive the corresponding truth table Verify and analyze the design Logic simulation (waveforms) Explain the function Fall 2010 CS2102 Chih-Tsun Huang 4
3 Derivation of Boolean Functions (1/2) Label all gate outputs that are functions of the input variables only. Determine the functions. Label all gate outputs that are functions of the input variables and previously labeled gate outputs, and find the functions. Repeat previous step until all the primary outputs are obtained. Fall 2010 CS2102 Chih-Tsun Huang 5 Derivation of Boolean Functions (2/2) Full adder example: Fall 2010 CS2102 Chih-Tsun Huang 6
4 Derivation of Truth Table (1/2) For n input variables List all the 2 n input combinations from 0 to 2 n-1 Partition the circuit into small single-output blocks and label the output of each block Obtain the truth table of the blocks depending on the input variables only Proceed to obtain the truth tables for other blocks that depend on previously defined truth tables Fall 2010 CS2102 Chih-Tsun Huang 7 Derivation of Truth Table (2/2) Example Fall 2010 CS2102 Chih-Tsun Huang 8
5 Design Procedure From the specifications, determine the inputs, outputs, and their symbols Derive the truth table (functions) from the relationship between the inputs and outputs Derive the simplified Boolean functions for each output function Under certain constraints: # of literals, # of gates, # of inputs to a gate (fan-in), propagation delay, # of interconnections, fan-out, power,, etc. Draw the logic diagram Verify the design Fall 2010 CS2102 Chih-Tsun Huang 9 Code Conversion Example (1/3) BCD-to-excess-3 code converter Fall 2010 CS2102 Chih-Tsun Huang 10
6 Code Conversion Example (2/3) Fall 2010 CS2102 Chih-Tsun Huang 11 Code Conversion Example (3/3) Fall 2010 CS2102 Chih-Tsun Huang 12
7 Binary Half Adder IOs Input: x, y Outputs: C (carry), S (sum) Truth table and functions Logic diagram Fall 2010 CS2102 Chih-Tsun Huang 13 Binary Full Adder (1/4) IOs Input: x, y, z (carry from previous lower significant bit) Outputs: C (carry), S (sum) Truth table Fall 2010 CS2102 Chih-Tsun Huang 14
8 Binary Full Adder (2/4) Functions and logic diagrams Fall 2010 CS2102 Chih-Tsun Huang 15 Binary Full Adder (3/4) Logic diagram Fall 2010 CS2102 Chih-Tsun Huang 16
9 Binary Full Adder (4/4) Full adder implemented with half adders Two half adders and one OR gate Fall 2010 CS2102 Chih-Tsun Huang 17 Binary (Ripple-Carry) Adder Produces arithmetic sum of two binary numbers Fall 2010 CS2102 Chih-Tsun Huang 18
10 Carry Propagation (1/4) For ripple carry adder Longest propagation delay: C 0 C 1 C 2 C 3 C 4 8 gate levels 2n gate levels for the carry to propagate from input to output for an n-bit adder Fall 2010 CS2102 Chih-Tsun Huang 19 Carry Propagation (2/4) Reduce the carry propagation delay Using faster gates Parallel adders, e.g., the carry lookahead adder Carry Lookahead Adder (CLA) Carry propagate: Carry generate: Sum: Carry: Fall 2010 CS2102 Chih-Tsun Huang 20
11 Carry Propagation (3/4) Logic diagram of carry lookahead generator Fall 2010 CS2102 Chih-Tsun Huang 21 Carry Propagation (4/4) 4-bit adder with carry lookahead Fall 2010 CS2102 Chih-Tsun Huang 22
12 Binary Subtractor Binary subtraction normally is performed by adding the minuend to the 2 s complement of the subtrahend 4-bit adder-subtractor M = 0: A + B M = 1: A B = A + (2 s complement of B) = A + B + 1 Fall 2010 CS2102 Chih-Tsun Huang 23 Overflow Adding two positive numbers and obtaining a negative number; or Adding two negative numbers and obtaining a positive number Overflow can be detected If the carry into the sign bit position and the carry out of the sign bit position are not equal V = 1 when the overflow occurs Fall 2010 CS2102 Chih-Tsun Huang 24
13 Decimal Adder (1/3) Addition of 2 decimal digits in BCD 9 inputs: 2 BCD s and one carry-in 5 outputs: 1 BCD and one carry-out Design approaches Truth table with 2 9 entries Using binary adders A digit in BCD cannot exceed 9 The max sum = 19 Binary to BCD (adding 6 for correction) Fall 2010 CS2102 Chih-Tsun Huang 25 Decimal Adder (2/3) Fall 2010 CS2102 Chih-Tsun Huang 26
14 Decimal Adder (3/3) Fall 2010 CS2102 Chih-Tsun Huang 27 Multiplication Multiplication consists of Generation of partial products Accumulation of shifted partial products Fall 2010 CS2102 Chih-Tsun Huang 28
15 2-bit by 2-bit Binary Multiplier Fall 2010 CS2102 Chih-Tsun Huang 29 4-bit by 3-bit Binary Multiplier Fall 2010 CS2102 Chih-Tsun Huang 30
16 Magnitude Comparator (1/3) Comparison of two numbers, three possible results A > B, A = B, A < B Design approaches (for n-bit numbers) By the truth table: 2 2n rows => not practicable By algorithm to build a regular circuit,, if,,, Fall 2010 CS2102 Chih-Tsun Huang 31 Magnitude Comparator (2/3) Fall 2010 CS2102 Chih-Tsun Huang 32
17 Magnitude Comparator (3/3) Another magnitude comparator Compute B A If C = 1, B < A If C = 0, B > A If Z = 1, A = B Fall 2010 CS2102 Chih-Tsun Huang 33 Decoders A decoder is a combinational circuit that converts binary information from n input lines to an m (maximum of 2 n ) unique output lines n-to-m-line decoder Output variables are mutually exclusive because only one output can be equal to 1 at any time (the vary 1- minterm) Can be implemented with AND gates Fall 2010 CS2102 Chih-Tsun Huang 34
18 3-to-8-line Decoder (1/2) Fall 2010 CS2102 Chih-Tsun Huang 35 3-to-8-line Decoder (2/2) Fall 2010 CS2102 Chih-Tsun Huang 36
19 Decoders with Enable Input (1/3) Line decoder with enable control (E) Also called demultiplexer (DMUX, DEMUX) Fall 2010 CS2102 Chih-Tsun Huang 37 Decoders with Enable Input (2/3) Constructed with NAND gates Decode minterms in their complemented form Fall 2010 CS2102 Chih-Tsun Huang 38
20 Decoder Expansion Larger decoders can be implemented with smaller decoders 4x16 decoder with two 3x8 decoders Fall 2010 CS2102 Chih-Tsun Huang 39 Combinational Logic Implementation (1/2) Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2 n decoder in conjunction with m external OR gates A full-adder,, 1,2,4,7,, 3,5,6,7 Fall 2010 CS2102 Chih-Tsun Huang 40
21 Combinational Logic Implementation (2/2) A function with minterms can be expressed in its complement form with minterms NOR gates are used instead of OR gates If NAND gates are used for the decoder, the output OR gates are replaced by NAND gates AND-OR => NAND-NAND Fall 2010 CS2102 Chih-Tsun Huang 41 Encoders (1/2) A combinational logic that performs the inverse operation of a decoder Only one input has value 1 at any given time Can be implemented with OR gates Fall 2010 CS2102 Chih-Tsun Huang 42
22 Encoders (2/2) Limitations Fall 2010 CS2102 Chih-Tsun Huang 43 Priority Encoders (1/2) Ensure only one of the input is encoded D 3 has the highest priority, while D 0 has the lowest priority X is the don t care conditions V is the valid output indicator Fall 2010 CS2102 Chih-Tsun Huang 44
23 Priority Encoders (2/2) Fall 2010 CS2102 Chih-Tsun Huang 45 Multiplexers A multiplexer (or MUX) selects (usually by n select lines) binary information from one of many (usually 2 n ) input lines and directs it to a single output line Fall 2010 CS2102 Chih-Tsun Huang 46
24 4-to-1-line MUX Fall 2010 CS2102 Chih-Tsun Huang 47 Quadruple 2-to-1-line MUX Fall 2010 CS2102 Chih-Tsun Huang 48
25 Boolean Function Implementation (1/4) MUX: one decoder + an OR gate 2 n -to-1 MUX can implement any Boolean function of n input variable Fall 2010 CS2102 Chih-Tsun Huang 49 Boolean Function Implementation (2/4) Example:,, 1,2,6,7 Fall 2010 CS2102 Chih-Tsun Huang 50
26 Boolean Function Implementation (3/4) Assign an ordering sequence of the n 1 input variables to the selection input of MUX The last (rightmost) variable will be used for the input lines Construct the truth table Consider a pair of consecutive minterms starting from m 0 Determine the input lines according to the last variable and output signals in the truth table Fall 2010 CS2102 Chih-Tsun Huang 51 Boolean Function Implementation (4/4) Example:,,, 1, 3, 4, 11, 12, 13, 14, 15 Fall 2010 CS2102 Chih-Tsun Huang 52
27 Three-State Gates (1/2) A multiplexer can be constructed with three-state gates Output states: 0, 1, and Z (high-impedance, or open circuits) Three-state gates can be used to build up a bus A communication channel among different modules in a digital system Fall 2010 CS2102 Chih-Tsun Huang 53 Three-State Gates (2/2) Examples: multiplexers with three-state gates Fall 2010 CS2102 Chih-Tsun Huang 54
COMBINATIONAL CIRCUITS
COMBINATIONAL CIRCUITS http://www.tutorialspoint.com/computer_logical_organization/combinational_circuits.htm Copyright tutorialspoint.com Combinational circuit is a circuit in which we combine the different
Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng
Digital Logic Design Basics Combinational Circuits Sequential Circuits Pu-Jen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction
Combinational Logic Design
Chapter 4 Combinational Logic Design The foundations for the design of digital logic circuits were established in the preceding chapters. The elements of Boolean algebra (two-element switching algebra
Chapter 4 Register Transfer and Microoperations. Section 4.1 Register Transfer Language
Chapter 4 Register Transfer and Microoperations Section 4.1 Register Transfer Language Digital systems are composed of modules that are constructed from digital components, such as registers, decoders,
Binary Adders: Half Adders and Full Adders
Binary Adders: Half Adders and Full Adders In this set of slides, we present the two basic types of adders: 1. Half adders, and 2. Full adders. Each type of adder functions to add two binary bits. In order
5 Combinatorial Components. 5.0 Full adder. Full subtractor
5 Combatorial Components Use for data transformation, manipulation, terconnection, and for control: arithmetic operations - addition, subtraction, multiplication and division. logic operations - AND, OR,
Sistemas Digitais I LESI - 2º ano
Sistemas Digitais I LESI - 2º ano Lesson 6 - Combinational Design Practices Prof. João Miguel Fernandes (miguel@di.uminho.pt) Dept. Informática UNIVERSIDADE DO MINHO ESCOLA DE ENGENHARIA - PLDs (1) - The
Binary full adder. 2-bit ripple-carry adder. CSE 370 Spring 2006 Introduction to Digital Design Lecture 12: Adders
SE 370 Spring 2006 Introduction to Digital Design Lecture 12: dders Last Lecture Ls and Ls Today dders inary full 1-bit full omputes sum, carry-out arry-in allows cascaded s = xor xor = + + 32 ND2 11 ND2
DEPARTMENT OF INFORMATION TECHNLOGY
DRONACHARYA GROUP OF INSTITUTIONS, GREATER NOIDA Affiliated to Mahamaya Technical University, Noida Approved by AICTE DEPARTMENT OF INFORMATION TECHNLOGY Lab Manual for Computer Organization Lab ECS-453
Understanding Logic Design
Understanding Logic Design ppendix of your Textbook does not have the needed background information. This document supplements it. When you write add DD R0, R1, R2, you imagine something like this: R1
Combinational circuits
Combinational circuits Combinational circuits are stateless The outputs are functions only of the inputs Inputs Combinational circuit Outputs 3 Thursday, September 2, 3 Enabler Circuit (High-level view)
exclusive-or and Binary Adder R eouven Elbaz reouven@uwaterloo.ca Office room: DC3576
exclusive-or and Binary Adder R eouven Elbaz reouven@uwaterloo.ca Office room: DC3576 Outline exclusive OR gate (XOR) Definition Properties Examples of Applications Odd Function Parity Generation and Checking
Gates, Circuits, and Boolean Algebra
Gates, Circuits, and Boolean Algebra Computers and Electricity A gate is a device that performs a basic operation on electrical signals Gates are combined into circuits to perform more complicated tasks
Counters and Decoders
Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4-bit ripple-through decade counter with a decimal read-out display. Such a counter
Systems I: Computer Organization and Architecture
Systems I: Computer Organization and Architecture Lecture 9 - Register Transfer and Microoperations Microoperations Digital systems are modular in nature, with modules containing registers, decoders, arithmetic
CHAPTER 3 Boolean Algebra and Digital Logic
CHAPTER 3 Boolean Algebra and Digital Logic 3.1 Introduction 121 3.2 Boolean Algebra 122 3.2.1 Boolean Expressions 123 3.2.2 Boolean Identities 124 3.2.3 Simplification of Boolean Expressions 126 3.2.4
Using Logic to Design Computer Components
CHAPTER 13 Using Logic to Design Computer Components Parallel and sequential operation In this chapter we shall see that the propositional logic studied in the previous chapter can be used to design digital
List of Experiment. 8. To study and verify the BCD to Seven Segments DECODER.(IC-7447).
G. H. RAISONI COLLEGE OF ENGINEERING, NAGPUR Department of Electronics & Communication Engineering Branch:-4 th Semester[Electronics] Subject: - Digital Circuits List of Experiment Sr. Name Of Experiment
3.Basic Gate Combinations
3.Basic Gate Combinations 3.1 TTL NAND Gate In logic circuits transistors play the role of switches. For those in the TTL gate the conducting state (on) occurs when the baseemmiter signal is high, and
CSE140: Components and Design Techniques for Digital Systems
CSE4: Components and Design Techniques for Digital Systems Tajana Simunic Rosing What we covered thus far: Number representations Logic gates Boolean algebra Introduction to CMOS HW#2 due, HW#3 assigned
BINARY CODED DECIMAL: B.C.D.
BINARY CODED DECIMAL: B.C.D. ANOTHER METHOD TO REPRESENT DECIMAL NUMBERS USEFUL BECAUSE MANY DIGITAL DEVICES PROCESS + DISPLAY NUMBERS IN TENS IN BCD EACH NUMBER IS DEFINED BY A BINARY CODE OF 4 BITS.
FORDHAM UNIVERSITY CISC 3593. Dept. of Computer and Info. Science Spring, 2011. The Binary Adder
FORDHAM UNIVERITY CIC 3593 Fordham College Lincoln Center Computer Organization Dept. of Computer and Info. cience pring, 2011 1 Introduction The Binar Adder The binar adder circuit is an important building
Karnaugh Maps & Combinational Logic Design. ECE 152A Winter 2012
Karnaugh Maps & Combinational Logic Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 4 Optimized Implementation of Logic Functions 4. Karnaugh Map 4.2 Strategy for Minimization 4.2. Terminology
FORDHAM UNIVERSITY CISC 3593. Dept. of Computer and Info. Science Spring, 2011. Lab 2. The Full-Adder
FORDHAM UNIVERSITY CISC 3593 Fordham College Lincoln Center Computer Organization Dept. of Computer and Info. Science Spring, 2011 Lab 2 The Full-Adder 1 Introduction In this lab, the student will construct
United States Naval Academy Electrical and Computer Engineering Department. EC262 Exam 1
United States Naval Academy Electrical and Computer Engineering Department EC262 Exam 29 September 2. Do a page check now. You should have pages (cover & questions). 2. Read all problems in their entirety.
Two's Complement Adder/Subtractor Lab L03
Two's Complement Adder/Subtractor Lab L03 Introduction Computers are usually designed to perform indirect subtraction instead of direct subtraction. Adding -B to A is equivalent to subtracting B from A,
EXPERIMENT 4. Parallel Adders, Subtractors, and Complementors
EXPERIMENT 4. Parallel Adders, Subtractors, and Complementors I. Introduction I.a. Objectives In this experiment, parallel adders, subtractors and complementors will be designed and investigated. In the
Asynchronous counters, except for the first block, work independently from a system clock.
Counters Some digital circuits are designed for the purpose of counting and this is when counters become useful. Counters are made with flip-flops, they can be asynchronous or synchronous and they can
DESIGN OF GATE NETWORKS
DESIGN OF GATE NETWORKS DESIGN OF TWO-LEVEL NETWORKS: and-or and or-and NETWORKS MINIMAL TWO-LEVEL NETWORKS KARNAUGH MAPS MINIMIZATION PROCEDURE AND TOOLS LIMITATIONS OF TWO-LEVEL NETWORKS DESIGN OF TWO-LEVEL
Digital Electronics Detailed Outline
Digital Electronics Detailed Outline Unit 1: Fundamentals of Analog and Digital Electronics (32 Total Days) Lesson 1.1: Foundations and the Board Game Counter (9 days) 1. Safety is an important concept
Adder.PPT(10/1/2009) 5.1. Lecture 13. Adder Circuits
Adder.T(//29) 5. Lecture 3 Adder ircuits Objectives Understand how to add both signed and unsigned numbers Appreciate how the delay of an adder circuit depends on the data values that are being added together
1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1.
File: chap04, Chapter 04 1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1. 2. True or False? A gate is a device that accepts a single input signal and produces one
Design Example: Counters. Design Example: Counters. 3-Bit Binary Counter. 3-Bit Binary Counter. Other useful counters:
Design Eample: ers er: a sequential circuit that repeats a specified sequence of output upon clock pulses. A,B,C,, Z. G, O, T, E, R, P, S,!.,,,,,,,7. 7,,,,,,,.,,,,,,,,,,,. Binary counter: follows the binary
The string of digits 101101 in the binary number system represents the quantity
Data Representation Section 3.1 Data Types Registers contain either data or control information Control information is a bit or group of bits used to specify the sequence of command signals needed for
Flip-Flops, Registers, Counters, and a Simple Processor
June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 Flip-Flops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number
Course Requirements & Evaluation Methods
Course Title: Logic Circuits Course Prefix: ELEG Course No.: 3063 Sections: 01 & 02 Department of Electrical and Computer Engineering College of Engineering Instructor Name: Justin Foreman Office Location:
ECE410 Design Project Spring 2008 Design and Characterization of a CMOS 8-bit Microprocessor Data Path
ECE410 Design Project Spring 2008 Design and Characterization of a CMOS 8-bit Microprocessor Data Path Project Summary This project involves the schematic and layout design of an 8-bit microprocessor data
Digital Design. Assoc. Prof. Dr. Berna Örs Yalçın
Digital Design Assoc. Prof. Dr. Berna Örs Yalçın Istanbul Technical University Faculty of Electrical and Electronics Engineering Office Number: 2318 E-mail: siddika.ors@itu.edu.tr Grading 1st Midterm -
Two-level logic using NAND gates
CSE140: Components and Design Techniques for Digital Systems Two and Multilevel logic implementation Tajana Simunic Rosing 1 Two-level logic using NND gates Replace minterm ND gates with NND gates Place
CSE140 Homework #7 - Solution
CSE140 Spring2013 CSE140 Homework #7 - Solution You must SHOW ALL STEPS for obtaining the solution. Reporting the correct answer, without showing the work performed at each step will result in getting
BOOLEAN ALGEBRA & LOGIC GATES
BOOLEAN ALGEBRA & LOGIC GATES Logic gates are electronic circuits that can be used to implement the most elementary logic expressions, also known as Boolean expressions. The logic gate is the most basic
earlier in the semester: The Full adder above adds two bits and the output is at the end. So if we do this eight times, we would have an 8-bit adder.
The circuit created is an 8-bit adder. The 8-bit adder adds two 8-bit binary inputs and the result is produced in the output. In order to create a Full 8-bit adder, I could use eight Full -bit adders and
Chapter 7. Registers & Register Transfers. J.J. Shann. J. J. Shann
Chapter 7 Registers & Register Transfers J. J. Shann J.J. Shann Chapter Overview 7- Registers and Load Enable 7-2 Register Transfers 7-3 Register Transfer Operations 7-4 A Note for VHDL and Verilog Users
ASYNCHRONOUS COUNTERS
LB no.. SYNCHONOUS COUNTES. Introduction Counters are sequential logic circuits that counts the pulses applied at their clock input. They usually have 4 bits, delivering at the outputs the corresponding
Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa
Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation
Chapter 1: Digital Systems and Binary Numbers
Chapter 1: Digital Systems and Binary Numbers Digital age and information age Digital computers general purposes many scientific, industrial and commercial applications Digital systems telephone switching
Figure 8-1 Four Possible Results of Adding Two Bits
CHPTER EIGHT Combinational Logic pplications Thus far, our discussion has focused on the theoretical design issues of computer systems. We have not yet addressed any of the actual hardware you might find
Lab 1: Study of Gates & Flip-flops
1.1 Aim Lab 1: Study of Gates & Flip-flops To familiarize with circuit implementations using ICs and test the behavior of different logic gates and Flip-flops. 1.2 Hardware Requirement a. Equipments -
2011, The McGraw-Hill Companies, Inc. Chapter 3
Chapter 3 3.1 Decimal System The radix or base of a number system determines the total number of different symbols or digits used by that system. The decimal system has a base of 10 with the digits 0 through
Modeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit
Modeling Sequential Elements with Verilog Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 4-1 Sequential Circuit Outputs are functions of inputs and present states of storage elements
EE 261 Introduction to Logic Circuits. Module #2 Number Systems
EE 261 Introduction to Logic Circuits Module #2 Number Systems Topics A. Number System Formation B. Base Conversions C. Binary Arithmetic D. Signed Numbers E. Signed Arithmetic F. Binary Codes Textbook
Counters are sequential circuits which "count" through a specific state sequence.
Counters Counters are sequential circuits which "count" through a specific state sequence. They can count up, count down, or count through other fixed sequences. Two distinct types are in common usage:
Module 3: Floyd, Digital Fundamental
Module 3: Lecturer : Yongsheng Gao Room : Tech - 3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental
Lab 1: Full Adder 0.0
Lab 1: Full Adder 0.0 Introduction In this lab you will design a simple digital circuit called a full adder. You will then use logic gates to draw a schematic for the circuit. Finally, you will verify
Operating Manual Ver.1.1
4 Bit Binary Ripple Counter (Up-Down Counter) Operating Manual Ver.1.1 An ISO 9001 : 2000 company 94-101, Electronic Complex Pardesipura, Indore- 452010, India Tel : 91-731- 2570301/02, 4211100 Fax: 91-731-
A single register, called the accumulator, stores the. operand before the operation, and stores the result. Add y # add y from memory to the acc
Other architectures Example. Accumulator-based machines A single register, called the accumulator, stores the operand before the operation, and stores the result after the operation. Load x # into acc
ECE232: Hardware Organization and Design. Part 3: Verilog Tutorial. http://www.ecs.umass.edu/ece/ece232/ Basic Verilog
ECE232: Hardware Organization and Design Part 3: Verilog Tutorial http://www.ecs.umass.edu/ece/ece232/ Basic Verilog module ();
RUTGERS UNIVERSITY Department of Electrical and Computer Engineering 14:332:233 DIGITAL LOGIC DESIGN LABORATORY
RUTGERS UNIVERSITY Department of Electrical and Computer Engineering 14:332:233 DIGITAL LOGIC DESIGN LABORATORY Fall 2012 Contents 1 LABORATORY No 1 3 11 Equipment 3 12 Protoboard 4 13 The Input-Control/Output-Display
C H A P T E R. Logic Circuits
C H A P T E R Logic Circuits Many important functions are naturally computed with straight-line programs, programs without loops or branches. Such computations are conveniently described with circuits,
CS 61C: Great Ideas in Computer Architecture Finite State Machines. Machine Interpreta4on
CS 61C: Great Ideas in Computer Architecture Finite State Machines Instructors: Krste Asanovic & Vladimir Stojanovic hbp://inst.eecs.berkeley.edu/~cs61c/sp15 1 Levels of RepresentaKon/ InterpretaKon High
Systems I: Computer Organization and Architecture
Systems I: omputer Organization and Architecture Lecture 8: Registers and ounters Registers A register is a group of flip-flops. Each flip-flop stores one bit of data; n flip-flops are required to store
Contents COUNTER. Unit III- Counters
COUNTER Contents COUNTER...1 Frequency Division...2 Divide-by-2 Counter... 3 Toggle Flip-Flop...3 Frequency Division using Toggle Flip-flops...5 Truth Table for a 3-bit Asynchronous Up Counter...6 Modulo
CMOS Binary Full Adder
CMOS Binary Full Adder A Survey of Possible Implementations Group : Eren Turgay Aaron Daniels Michael Bacelieri William Berry - - Table of Contents Key Terminology...- - Introduction...- 3 - Design Architectures...-
(Refer Slide Time: 00:01:16 min)
Digital Computer Organization Prof. P. K. Biswas Department of Electronic & Electrical Communication Engineering Indian Institute of Technology, Kharagpur Lecture No. # 04 CPU Design: Tirning & Control
Digital Electronics Part I Combinational and Sequential Logic. Dr. I. J. Wassell
Digital Electronics Part I Combinational and Sequential Logic Dr. I. J. Wassell Introduction Aims To familiarise students with Combinational logic circuits Sequential logic circuits How digital logic gates
SECTION C [short essay] [Not to exceed 120 words, Answer any SIX questions. Each question carries FOUR marks] 6 x 4=24 marks
![SECTION C [short essay] [Not to exceed 120 words, Answer any SIX questions. Each question carries FOUR marks] 6 x 4=24 marks](/thumbs/35/17285180.jpg "SECTION C [short essay] [Not to exceed 120 words, Answer any SIX questions. Each question carries FOUR marks] 6 x 4=24 marks")
UNIVERSITY OF KERALA First Degree Programme in Computer Applications Model Question Paper Semester I Course Code- CP 1121 Introduction to Computer Science TIME : 3 hrs Maximum Mark: 80 SECTION A [Very
Chapter 2 Logic Gates and Introduction to Computer Architecture
Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are
7CS-A(CD_lab) Actual date of covering the. Reason for not covering the topic in due time. Month in which the topic will be covered
7CS-A(CD_lab) Write grammar for a fictitious language and create a lexical analyzer for the same Develop a lexical analyzer to recognize a few patterns in PASCAL and C (ex: identifiers, constants, comments,
Let s put together a Manual Processor
Lecture 14 Let s put together a Manual Processor Hardware Lecture 14 Slide 1 The processor Inside every computer there is at least one processor which can take an instruction, some operands and produce
EE360: Digital Design I Course Syllabus
: Course Syllabus Dr. Mohammad H. Awedh Fall 2008 Course Description This course introduces students to the basic concepts of digital systems, including analysis and design. Both combinational and sequential
INTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS
Logic in Computer Science: Logic Gates
Logic in Computer Science: Logic Gates Lila Kari The University of Western Ontario Logic in Computer Science: Logic Gates CS2209, Applied Logic for Computer Science 1 / 49 Logic and bit operations Computers
ANALOG & DIGITAL ELECTRONICS
ANALOG & DIGITAL ELECTRONICS Course Instructor: Course No: PH-218 3-1-0-8 Dr. A.P. Vajpeyi E-mail: apvajpeyi@iitg.ernet.in Room No: #305 Department of Physics, Indian Institute of Technology Guwahati,
Building Blocks for Digital Design
Building Blocks for Digital Design The construction of most digital systems is a large task. Disciplined designers in any field will subdivide the original task into manageable subunits building blocks
ETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies
ETEC 2301 Programmable Logic Devices Chapter 10 Counters Shawnee State University Department of Industrial and Engineering Technologies Copyright 2007 by Janna B. Gallaher Asynchronous Counter Operation
WEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1
WEEK 8.1 egisters and Counters ECE124 igital Circuits and Systems Page 1 Additional schematic FF symbols Active low set and reset signals. S Active high set and reset signals. S ECE124 igital Circuits
Today. Binary addition Representing negative numbers. Andrew H. Fagg: Embedded Real- Time Systems: Binary Arithmetic
Today Binary addition Representing negative numbers 2 Binary Addition Consider the following binary numbers: 0 0 1 0 0 1 1 0 0 0 1 0 1 0 1 1 How do we add these numbers? 3 Binary Addition 0 0 1 0 0 1 1
DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute. 2nd (Spring) term 2012/2013
DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 4. LECTURE: COUNTERS AND RELATED 2nd (Spring) term 2012/2013 1 4. LECTURE: COUNTERS AND RELATED 1. Counters,
2.0 Chapter Overview. 2.1 Boolean Algebra
Thi d t t d ith F M k 4 0 2 Boolean Algebra Chapter Two Logic circuits are the basis for modern digital computer systems. To appreciate how computer systems operate you will need to understand digital
Take-Home Exercise. z y x. Erik Jonsson School of Engineering and Computer Science. The University of Texas at Dallas
Take-Home Exercise Assume you want the counter below to count mod-6 backward. That is, it would count 0-5-4-3-2-1-0, etc. Assume it is reset on startup, and design the wiring to make the counter count
Binary Division. Decimal Division. Hardware for Binary Division. Simple 16-bit Divider Circuit
Decimal Division Remember 4th grade long division? 43 // quotient 12 521 // divisor dividend -480 41-36 5 // remainder Shift divisor left (multiply by 10) until MSB lines up with dividend s Repeat until
Read-only memory Implementing logic with ROM Programmable logic devices Implementing logic with PLDs Static hazards
Points ddressed in this Lecture Lecture 8: ROM Programmable Logic Devices Professor Peter Cheung Department of EEE, Imperial College London Read-only memory Implementing logic with ROM Programmable logic
CONTENTS PREFACE 1 INTRODUCTION 1 2 NUMBER SYSTEMS AND CODES 25. vii
2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is CONTENTS PREFACE xv 1 INTRODUCTION 1 1.1 About Digital Design 1 1.2 Analog versus Digital 3 1.3 Digital Devices
Lecture #21 April 2, 2004 Relays and Adder/Subtractors
Lecture #21 April 2, 2004 Relays and Adder/Subtractors In this lecture we look at a real technology for implementing gate circuits, as well as a more-or-less complete design for a general purpose adder/subtractor
Implementation of Modified Booth Algorithm (Radix 4) and its Comparison with Booth Algorithm (Radix-2)
Advance in Electronic and Electric Engineering. ISSN 2231-1297, Volume 3, Number 6 (2013), pp. 683-690 Research India Publications http://www.ripublication.com/aeee.htm Implementation of Modified Booth
Lecture 5: Gate Logic Logic Optimization
Lecture 5: Gate Logic Logic Optimization MAH, AEN EE271 Lecture 5 1 Overview Reading McCluskey, Logic Design Principles- or any text in boolean algebra Introduction We could design at the level of irsim
CDA 3200 Digital Systems. Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012
CDA 3200 Digital Systems Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012 Outline Data Representation Binary Codes Why 6-3-1-1 and Excess-3? Data Representation (1/2) Each numbering
(1) /30 (2) /30 (3) /40 TOTAL /100
Your Name: SI Number: UNIVERSITY OF CALIFORNIA AT BERKELEY BERKELEY AVIS IRVINE LOS ANGELES RIVERSIE SAN IEGO SAN FRANCISCO epartment of Electrical Engineering and Computer Sciences SANTA BARBARA SANTA
University of St. Thomas ENGR 230 ---- Digital Design 4 Credit Course Monday, Wednesday, Friday from 1:35 p.m. to 2:40 p.m. Lecture: Room OWS LL54
Fall 2005 Instructor Texts University of St. Thomas ENGR 230 ---- Digital Design 4 Credit Course Monday, Wednesday, Friday from 1:35 p.m. to 2:40 p.m. Lecture: Room OWS LL54 Lab: Section 1: OSS LL14 Tuesday
NEW adder cells are useful for designing larger circuits despite increase in transistor count by four per cell.
CHAPTER 4 THE ADDER The adder is one of the most critical components of a processor, as it is used in the Arithmetic Logic Unit (ALU), in the floating-point unit and for address generation in case of cache
ENGI 241 Experiment 5 Basic Logic Gates
ENGI 24 Experiment 5 Basic Logic Gates OBJECTIVE This experiment will examine the operation of the AND, NAND, OR, and NOR logic gates and compare the expected outputs to the truth tables for these devices.
Fault Modeling. Why model faults? Some real defects in VLSI and PCB Common fault models Stuck-at faults. Transistor faults Summary
Fault Modeling Why model faults? Some real defects in VLSI and PCB Common fault models Stuck-at faults Single stuck-at faults Fault equivalence Fault dominance and checkpoint theorem Classes of stuck-at
CHAPTER IX REGISTER BLOCKS COUNTERS, SHIFT, AND ROTATE REGISTERS
CHAPTER IX-1 CHAPTER IX CHAPTER IX COUNTERS, SHIFT, AN ROTATE REGISTERS REA PAGES 249-275 FROM MANO AN KIME CHAPTER IX-2 INTROUCTION -INTROUCTION Like combinational building blocks, we can also develop
150127-Microprocessor & Assembly Language
Chapter 3 Z80 Microprocessor Architecture The Z 80 is one of the most talented 8 bit microprocessors, and many microprocessor-based systems are designed around the Z80. The Z80 microprocessor needs an
Digital Fundamentals. Lab 8 Asynchronous Counter Applications
Richland College Engineering Technology Rev. 0 B. Donham Rev. 1 (7/2003). Horne Rev. 2 (1/2008). Bradbury Digital Fundamentals CETT 1425 Lab 8 Asynchronous Counter Applications Name: Date: Objectives:
Digital Systems Laboratory
Eskişehir Osmangazi University Digital Systems Laboratory Rev 3.01 February 2011 LIST OF EXPERIMENTS 1. BINARY AND DECIMAL NUMBERS 2. DIGITAL LOGIC GATES 3. INTRODUCTION TO LOGICWORKS 4. BOOLEAN ALGEBRA
DB19. 4-Bit Parallel Adder/ Subtractor. Digital Lab Experiment Board Ver. 1.0
4-Bit Parallel Adder/ Subtractor Digital Lab Experiment Board Ver. 1.0 QUALITY POLICY To be a Global Leader of Innovative, Competitive and Eco friendly Electronic Equipment, Software Products and Turn-key
CS101 Lecture 26: Low Level Programming. John Magee 30 July 2013 Some material copyright Jones and Bartlett. Overview/Questions
CS101 Lecture 26: Low Level Programming John Magee 30 July 2013 Some material copyright Jones and Bartlett 1 Overview/Questions What did we do last time? How can we control the computer s circuits? How