Advanced Schottky Family SDAA010

Transcription

1 Advanced Schottky Family SDAA010 1

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3 Contents Title Page Introduction Introduction to Advanced Schottky-Clamped TTL Speed-Power Slots Filled by ALS and AS TTL Additional Advantages Offered by ALS and AS Devices Concepts of Defining Series AS and ALS Compatibility With Other TTL Families Fanout Using the Schottky Barrier Diode Analysis of the Schottky Clamped Transistor Analysis of ALS and AS NAND Gates Circuit Parameters Transfer Characteristics Input Characteristics Output Characteristics Switching Speed DC Noise Margins Noise Rejection Guidelines for Series ALS/ AS TTL System Design Power Supply Regulation Supply Voltage Ripple Noise Considerations Noise Types and Control Methods Shielding Grounding and Decoupling Cross Talk Transmission-Line Driving Reflections References Acknowledgment Appendixes A Normalized Load Factors B Letter Symbols, Terms, and Definitions List of Illustrations Figure Title Page 1 Speed-Power Relationships of Digital Integrated Circuits Series 54/74 TTL Family Compatible Levels Showing DC Noise Margins Fanout Capability Baker Clamp The Schottky-Clamped Transistor Schottky Barrier-Diode Schottky Barrier-Diode Energy Diagrams iii

4 List of Illustrations (continued) Figure Title Page 8 Metal-N Diode Current-Voltage Characteristics Differences Between P-N and Schottky Barrier-Diodes Standard Process ( LS/ S) Advanced Process ( ALS/ AS) ALS00A NAND Gate Schematic AS00 NAND Gate Schematic Input Voltage vs Output Voltage of ALS/ AS Input Current vs Input Voltage for TTL Families Low-Level Input Current vs High-Level Input Voltage for TTL Families DC Equivalent Input Circuit for Series ALS Gate Equivalent Output Circuit for ALS/ AS Gates High-Level Output Voltage vs High-Level Output Current Low-Level Output Circuit for ALS/ AS Gates Low-Level Output Voltage vs Low-Level Output Current High- to Low-Level Propagation Delay vs Load Capacitance Low- to High-Level Propagation Delay vs Load Capacitance Power Dissipation per Gate vs Frequency Stray Coupling Capacitance Evaluations of Gate Response to Fast Input Pulses Theoretical Required Pulse Width vs Pulse Amplitude for AS and ALS Inputs Parameter Measurement Information Effect of Source Impedance on Input Noise Spurious Output Produced by Supply Voltage Ripple Effect of Ground Noise on Noise Margin Typical Logic Circuit With Noisy Input Diagram Representing a Gate Driving a Transmission Line Noise Generation Caused by Poor Transmission-Line Return Ideal Transmission-Line Current Handling Circuit With Effective Capacitive Loading Supply Current Transient Comparisons Transmission-Line Power Buses Capacitive Storage Supply Voltage System Commonly Used Power Distribution and Decoupling System Equivalent Circuit for Sending Line Equivalent Circuit for Cross Talk Capacitive Cross Talk Between Two Signal Lines Coupling Impedances Involved in Cross Talk Equivalent Cross-Talk Network Microstrip Line Strip Line iv

5 List of Illustrations (continued) Figure Title Page 48 Line Spacing Versus Cross-Talk Constant TTL Bergeron Diagram ALS/ AS Driving Twisted Pair AS ve Transition Bergeron Diagram AS ve Voltage/Time Plot AS +ve Transition Bergeron Diagram AS +ve Voltage/Time Plot ALS ve Transition Bergeron Diagram ALS ve Voltage/Time Plot ALS +ve Transition Bergeron Diagram ALS +ve Voltage/Time Plot Oscilloscope Photograph of AS001 ve Transition Using 50-Ohm Line Oscilloscope Photograph of AS00 +ve Transition Using 50-Ohm Line Oscilloscope Photograph of AS00 ve Transition Using 25-Ohm Line Oscilloscope Photograph of AS00 +ve Transition Using 25-Ohm Line Oscilloscope Photograph of ALS00A ve Transition Using 50-Ohm Line Oscilloscope Photograph of ALS00A +ve Transition Using 50-Ohm Line Oscilloscope Photograph of ALS00A ve Transition Using 25-Ohm Line Oscilloscope Photograph of ALS00A +ve Transition Using 25-Ohm Line List of Tables Table Title Page 1 Typical Performance Characteristics by TTL Series Worst Case Output Parameters Guidelines for Systems Design for Advanced Schottky TTL Guidelines for Printed Circuit Board Layout for Advanced Schottky TTL Guidelines for General Usage of Advanced Schottky TTL Guidelines for Gates and Flip-Flops Using Advanced Schottky TTL Typical Impedance of Microstrip Lines Typical Impedance of Strip Lines A 1 Normalized Input Currents A 2 Fanout Capability v

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