Logical Design. Design with Basic Logic Gates

Transcription

1 Logicl Design Zvi Kohvi nd Nirj K. Jh Design ith Bsic Logic Gtes Logic gtes: perform logicl opertions on input signls Positive (negtive) logic polrit: constnt () denotes high voltge nd constnt lo (high) voltge Snchronous circuits: driven clock tht produces trin of equll spced pulses Asnchronous circuits: re lmost free-running nd do not depend on clock; controlled initition nd completion signls Fnout: numer of gte inputs driven the output of single gte Fnin: ound on the numer of inputs gte cn hve Propgtion del: time to propgte signl through gte 2

2 Anlsis of Comintionl Circuits Circuit nlsis: determine the Boolen function tht descries the circuit Done trcing the output of ech gte, strting from circuit inputs nd continuing tords ech circuit output Emple: multi-level relition of full inr dder C = AB + (A + B)C = AB + AC + BC S = (A + B + C)[AB + (A + B)C] + ABC = (A + B + C)(A + B )(A + C )(B + C ) + ABC = AB C + A BC + A B C + ABC = A B C 3 Simple Design Prolems Prllel prit-it genertor: produces output vlue if nd onl if n odd numer of its inputs hve vlue P () Mp. () Implementtion. P =

3 Simple Design Prolems (Contd.) Seril-to-prllel converter: distriutes sequence of inr digits on seril input to set of different outputs, s specified eternl control signls C2 C L L2 L3 L4 5 Logic Design ith Integrted Circuits Smll scle integrtion (SSI): integrted circuit pckges contining fe gtes; e.g., AND, OR, NOT, NAND, NOR, XOR Medium scle integrtion (MSI): pckges contining up to out gtes; e.g., code converters, dders Lrge scle integrtion (LSI): pckges contining thousnds of gtes; rithmetic unit Ver lrge scle integrtion (VLSI): pckges ith millions of gtes 6 3

4 Comprtors n-it comprtor: compres the mgnitude of to numers X nd Y, nd hs three outputs f, f 2, nd f 3 f = iff X > Y f 2 = iff X = Y f 3 = iff X < Y it comprtor f f2 f3 () Block digrm () Mp for f, f2, nd f3. f f = = ( + ) f 2 = = ( ) + ( ) = ( + )( ) f 3 = = 2 2 ( + ) + 7 (c) Circuit for f. 4-it/2-it Comprtors Four-it comprtor: inputs (four for X, four for Y, nd three connected to outputs f, f 2 nd f 3 of the preceding stge) 2-it comprtor: 4 4 f f2 f3 > = < > = < Inputs from preceding stge () A 4-it comprtor f f2 f3 > = < > = < > = < > = < > = < > = < () A 2-it comprtor. 8 4

5 Dt Selectors Multipleer: electronic sitch tht connects one of n inputs to the output Dt selector: ppliction of multipleer n dt input lines, D, D,, D n- m select digit inputs s, s,, s m- output 9 Implementing Sitching Functions ith Dt Selectors Dt selectors: cn implement ritrr sitching functions Emple: implementing to-vrile functions 5

6 Implementing Sitching Functions ith Dt Selectors (Contd.) To implement n n-vrile function: dt selector ith n- select inputs nd 2 n- dt inputs Implementing three-vrile functions: = s 2 s D + s 2 s D + s 2 s D 2 + s 2 s D 3 Emple: s = A, s 2 = B, D = C, D =, D 2 =, D 3 = C = A B C + AB + ABC = AC + B C Generl cse: Assign n- vriles to the select inputs nd lst vrile nd constnts nd to the dt inputs such tht desired function results Priorit Encoders Priorit encoder: n input lines nd log 2 n output lines Input lines represent units tht m request service When inputs p i nd p j, such tht i > j, request service simultneousl, line p i hs priorit over line p j Encoder produces inr output code indicting hich of the input lines requesting service hs the highest priorit Emple: Eight-input, three-output priorit encoder p p p2 p3 p4 p5 p6 p7 Enle Priorit encoder 2 4 p Input lines Outputs p p2 p3 p4 p5 p6 p7 4 2 () Block digrm. () Truth tle. 4 = p 4 p 5 p 6 p 7 + p 5 p 6 p 7 + p 6 p 7 + p 7 = p 4 + p 5 + p 6 + p 7 2 = p 2 p 3 p 4 p 5 p 6 p 7 + p 3 p 4 p 5 p 6 p 7 + p 6 p 7 + p 7 = p 2 p 4 p 5 + p 3 p 4 p 5 + p 6 + p 7 = p p 2 p 3 p 4 p 5 p 6 p 7 + p 3 p 4 p 5 p 6 p 7 + p 5 p 6 p 7 + p 7 = p p 2 p 4 p 6 + p 3 p 4 p 6 + p 5 p 6 + p 7 2 6

7 Priorit Encoders (Contd.) p p p2 p3 p4 p5 2 p6 4 p7 Request indictor Enle (c) Logic digrm. 3 Decoders Decoders ith n inputs nd 2 n outputs: for n input comintion, onl one output is Useful for: Routing input dt to specified output line, e.g., in ddressing memor Bsic uilding locks for implementing ritrr sitching functions Code conversion Dt distriution Emple: 2-to-4- decoder f = f = f2 = f3 = 4 7

8 Decoders (Contd.) Emple: 4-to-6 decoder mde of to 2-to-4 decoders nd gtesitching mtri 5 Deciml Decoder BCD-to-deciml: 4-to-6 decoder mde of to 2-to-4 decoders nd gtesitching mtri f f f2 f3 f4 f5 f6 f7 f8 f9 Enle (c) Logic digrm. 6 8

9 Deciml Decoder (Contd.) Implementtion using prtil-gte mtri: 7 Implementing Aritrr Sitching Functions Emple: Relie distinct minterm t ech output 8 9

10 Demultipleers Demultipleers: decoder ith dt input nd n ddress inputs Directs input to n one of the 2 n outputs C2 C Emple: A 4-output demultipleer L L2 L3 L4 9 Seven-segment Displ Seven-segment displ: BCD to seven-segment decoder nd seven LEDs Seven-segment pttern nd code: A = B = C = D = E = F = G =

11 Sine Genertors Comintionl sine genertors: for fst nd repeted evlution of sine Input: ngle in rdins converted to inr Output: sine in inr Angle sin( ) () Truth tle. = = = = NAND/NOR Circuits Sitching lger: not directl pplicle to NAND/NOR logic NAND nd NOR gte smols 22

12 Anlsis of NAND/NOR Netorks Emple: circles (inversions) t oth ends of line cncel ech other A B C D E F A B C D E F 3 5 T = A + (B + C )(D + EF ) B + C 4 [(B + C )(D + EF )] 2 D + EF (EF ) () NAND-logic circuit. T = A + (B + C )(D + EF ) B + C (B + C )(D + EF ) D + EF EF () Logicll equivlent AND-OR circuit. 23 Snthesis of NAND/NOR Netorks Emple: Relie T = (+) ( ) 2 [( + )] 4 T = ( + ) + () First relition. 3 + ( ) 2 3 [( + )] 4 ( ) T = ( + ) + () Relition ith to-input gtes. 24 2

13 Design of High-speed Adders Full dder: performs inr ddition of three inr digits Inputs: rguments A nd B nd crr-in C Outputs: sum S nd crr-out C Emple: Truth tle, lock digrm nd epressions: S = A B C + A BC + AB C + ABC = A B C C = A BC + ABC + AB C + ABC = AB + AC + BC 25 Ripple-crr Adder Ripple-crr dder: Stges of full dders C f : forced crr C (n-) : overflo crr S i = A i B i C i C i = A i B i + A i C i + B i C i Time required: Time per full dder: 2 units Time for ripple-crr dder: 2n units 26 3

14 Crr-lookhed Adder Crr-lookhed dder: severl stges simultneousl emined nd their crries generted in prllel Generte signl D i = A i B i Propgte signl T i = A i B i Thus, C i = D i + T i C i To generte crries in prllel: convert recursive form to nonrecursive C i = D i + T i C i C i = C (i-) C i = D i + T i (D i- + T i- C i- ) = D i + T i D i- + T i T i- (D i-2 + T i-2 C i-2 ) = D i + T i D i- + T i T i- D i-2 + T i T i- T i-2 C i C i = D i + T i D i- + T i T i- D i T i T i- T i-2 T C f Thus, C i = if it hs een generted in the i th stge or originted in preceding stge nd propgted to ll susequent stges 27 Crr-lookhed Adder (Contd.) Implementtion of lookhed for the complete dder imprcticl: Divide the n stges into groups Full crr lookhed ithin group Ripple crr eteen groups Emple: Three-digit dder group ith full crr lookhed S2 S S A2 B2 A B A B C2 C SN2 SN SN A B A B A B Cf CN2 CN CN Cg = C2 C C () Block digrm of initil three-stge group Time tken: 4 time units for C g Onl 2 time units for C g2 nd other group crries 28 4

15 3-it Adder Emple: divide n stges into groups of three stges Time tken: 4 + 2n/3 time units 5% dditionl hrdre for threefold speedup 29 Metl-oide Semiconductor (MOS) Trnsistors nd Gtes Complementr metl-oide semiconductor (CMOS): currentl the dominnt technolog To tpes of trnsistors: nmos nd pmos () nmos trnsistor (d) pmos trnsistor (g) Complementr sitch = = () nmos opertion = = (e) pmos opertion = = (h) Complementr sitch opertion (c) nmos model (f) pmos model (i) Complementr sitch model 3 5

16 Trnsmission Function of Netork CMOS inverter nd its trnsmission functions: (Vdd) f f (Vss) 3 CMOS NAND/NOR Gtes (Vdd) f f (Vss) () CMOS NAND gte nd its trnsmission functions. (Vdd) f f (Vss) () CMOS NOR gte nd its trnsmission functions. 32 6

17 Anlsis of Series-prllel Netorks Alger of MOS netorks: isomorphic to sitching lger Emple: Find the trnsmission function of the netork nd its complementr sitch sed nd comple gte CMOS implementtions () T = [( + ) ]. c () T = ( + + ). d T (Vdd) T pmos netork nmos netork (c) Tcd = T = +. Complementr sitch sed (Vss) Comple gte 33 Anlsis of Non-series-prllel Netorks Otining the trnsmission function: Tie sets: miniml pths eteen to terminls Cut sets: miniml sets of rnches, hen open, ensure no trnsmission eteen the to terminls i v j () Tie sets. Tij = + v + v +. i v j () Cut sets. Tij = ( + )( + v + )( + v + )( + ). 34 7

18 Snthesis of MOS Netorks Snek pths in non-series-prllel netorks: undesired pths tht m chnge the trnsmission function Occur ecuse of ilterl nture of MOS trnsistors Emple: Design miniml netork ith BCD inputs tht produces henever the input is 3 or multiple of 3 () Mp for T = + +. () Series-prllel relition of T. (c) Miniml relition of T. Snek pth: OK since it hs no effect on the trnsmission function 35 Snthesis of MOS Netorks (Contd.) Emple: Design miniml netork to relie T(,,,) = (,3,3,4,5) 36 8