Introduction to CMOS VLSI Design. Circuits & Layout

Transcription

1 Introduction to MOS VLSI Design ircuits & Layout

2 Review - Manufacturing Process

3 Review Silicon Ingot

4 Modern MOS Process

5 Modern MOS Process Walk-Through p-epi p+ ase material: p+ substrate with p-epi layer p-epi p+ Si N 3 4 SiO 2 fter deposition of gate-oxide and sacrifical nitride (acts as a buffer layer) p+ fter plasma etch of insulating trenches using the inverse of the active area mask

6 Modern MOS Process Walk-Through cont d SiO 2 fter trench filling, MP planarization, and removal of sacrificial nitride n fter n-well and V Tp adjust implants p fter p-well and V Tn adjust implants

7 Modern MOS Process Walk-Through cont d poly(silicon) fter polysilicon deposition and etch n+ p+ fter n+ source/dram and p+ source/drain implants. These steps also dope the polysilicon. SiO 2 fter deposition of SiO 2 insulator and contact hole etch

8 Modern MOS Process Walk-Through cont d l fter deposition and patterning of first l layer. l SiO 2 fter deposition of SiO 2 insulator, etching of via s, deposition and patterning of second layer of l.

9 Layout Editor: max Design Frame

10 max Layer Representation Metals (five) and vias/contacts between the interconnect levels Note that m5 connects only to m4, m4 only to m3, etc., and m1 only to poly, ndif, and pdif Some technologies support stacked vias ctive active areas on/in substrate (poly gates, transistor channels (nfet, pfet), source and drain diffusions (ndif, pdif), and well contacts (nwc, pwc)) Wells (nw) and other select areas (pplus, nplus, prb)

11 MOS Inverter max Layout

12 MOS Gate Design ctivity: Sketch a 4-input MOS NND gate

13 MOS Gate Design ctivity: Sketch a 4-input MOS NOR gate D Y

14 omplementary MOS omplementary MOS logic gates nmos pull-down network pmos pull-up network a.k.a. static MOS inputs pmos pull-up network output Pull-up OFF Pull-up ON Pull-down OFF Z (float) 1 Pull-down ON 0 X (crowbar) nmos pull-down network

15 Series and Parallel nmos: 1 = ON pmos: 0 = ON Series: both must be ON Parallel: either can be ON g1 g2 (a) g1 g2 a b a b a a a a b b b b OFF OFF OFF ON a a a a b b b b (b) ON OFF OFF OFF a a a a a g1 g b b b b b (c) OFF ON ON ON a a a a a g1 g b b b b b (d) ON ON ON OFF

16 onduction omplement omplementary MOS gates always produce 0 or 1 Ex: NND gate Series nmos: Y=0 when both inputs are 1 Thus Y=1 when either input is 0 Requires parallel pmos Rule of onduction omplements Pull-up network is complement of pull-down Parallel -> series, series -> parallel Y

17 ompound Gates ompound gates can do any inverting function Ex: Y = (. +.D) D D (a) (b) (c) D (d) D D D Y D (f) Y (e)

18 Example Y = ((++).D)

19 Example Y = ((++).D) D D Y

20 omplex MOS Gate D D OUT = D + ( + )

21 onstructing a omplex Gate V DD V DD D F SN1 D F SN4 SN2 SN3 D F (a) pull-down network (b) Deriving the pull-up network hierarchically by identifying sub-nets D (c) complete gate

22 Gate Layout Layout can be very time consuming Design gates to fit together nicely uild a library of standard cells Standard cell design methodology V DD and GND should abut (standard height) djacent gates should satisfy design rules nmos at bottom and pmos at top ll gates include well and substrate contacts

23 ell Design Standard ells General purpose logic an be synthesized Same height, varying width Datapath ells For regular, structured designs (arithmetic) Includes some wiring in the cell Fixed height and width

24 Standard ell Layout Methodology 1980s Routing channel V DD signals GND

25 Standard ell Layout Methodology 1990s Mirrored ell No Routing channels V DD V DD M2 M3 GND Mirrored ell GND

26 Standard ells N Well V DD ell height 12 metal tracks Metal track is approx. 3λ + 3λ Pitch = repetitive distance between objects ell height is 12 pitch 2λ In Out ell boundary GND Rails ~10λ

27 Standard ells With minimal diffusion routing V DD With silicided diffusion V DD V DD In M 2 Out In Out In Out M 1 GND GND

28 Standard ells V DD 2-input NND gate V DD Out GND

29 Example: Inverter

30 Example: NND3 Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 V DD rail at top Metal1 GND rail at bottom 32 λ by 40 λ

31 Stick Diagrams Stick diagrams help plan layout quickly Need not be to scale Draw with color pencils or dry-erase markers

32 Example Sketch a stick diagram for Y = ((++).D)

33 Stick Diagrams ontains no dimensions Represents relative positions of transistors Inverter V DD NND2 V DD Out Out GND In GND

34 Stick Diagrams j Logic Graph X PUN X = ( + ) X i V DD i j GND PDN

35 Two Versions of ( + ) V DD V DD X X GND GND

36 onsistent Euler Path X X i V DD j GND

37 OI22 Logic Graph X PUN D D X = (+) (+D) X V DD D D GND PDN

38 Example: x = ab+cd x x b c b c x V DD x V DD a d a d GND GND (a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d} V DD x GND a b c d (c) stick diagram for ordering {a b c d}

39 Multi-Fingered Transistors One finger Two fingers (folded) Less diffusion capacitance

40 Design Rules Interface between the circuit designer and process engineer Guidelines for constructing process masks Unit dimension: minimum line width scalable design rules: lambda parameter absolute dimensions: micron rules Rules constructed to ensure that design works even when small fab errors (within some tolerance) occur complete set includes set of layers intra-layer: relations between objects in the same layer inter-layer: relations between objects on different layers

41 Why Have Design Rules? To be able to tolerate some level of fabrication errors such as 1. Mask misalignment 2. Dust 3. Process parameters (e.g., lateral diffusion) 4. Rough surfaces

42 Intra-Layer Design Rule Origins Minimum dimensions (e.g., widths) of objects on each layer to maintain that object after fab minimum line width is set by the resolution of the patterning process (photolithography) Minimum spaces between objects (that are not related) on the same layer to ensure they will not short after fab

43 Intra-Layer Design Rules

44 Inter-Layer Design Rule Origins 1. Transistor rules transistor formed by overlap of active and poly layers

45 Transistor Layout

46 Inter-Layer Design Rule Origins, on t ontact and via rules

47 Vias and ontacts 2 1 Via Metal to ctive ontact 1 Metal to Poly ontact