2-2 Chapter 2 Gates, Circuits, and Combinational Logic. 2-4 Chapter 2 Gates, Circuits, and Combinational Logic

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1 - hapter Gates, ircuits, and ombinational Logic hapter : Gates, ircuits, and ombinational Logic - hapter Gates, ircuits, and ombinational Logic nalog and Digital Systems Dr. Tim McGuire Sam Houston State University ased on notes by Miles Murdocca n analog circuit can have any value between its maximum and minimum limits digital circuit (at least in concept) has one of a fixed number of values and changes from one value to another instantaneously Digital electronic circuits use a binary system, with two values ( and ) Ideally, if a computer runs off 5, a (false, low, off) value would be represented by. and (true, high, on) by +5. This is TTL (which is common but being replaced by faster and cooler devices) We can't unfortunately, construct devices with such precision, so we assign ranges of values to represent and -3 hapter Gates, ircuits, and ombinational Logic ssignments of Logical and Logical to oltage Ranges +5 Logical +5 Logical -4 hapter Gates, ircuits, and ombinational Logic Truth Tables Developed in 854 by George oole urther developed by laude Shannon (ell Labs) Outputs are computed for all possible input combinations (how many input combinations are there? onsider a room with two light switches. How must they work?.4.4 orbidden range Logical..8 orbidden range Logical Hot Switch Light Z Switch Inputs Output Z (a) t the output of a logic gate (b) t the input to a logic gate Don't show this to your electrician, or wire your house this way. This circuit definitely violates the electric code. The practical circuit never leaves the lines to the light "hot" when the light is turned off. an you figure how? -5 hapter Gates, ircuits, and ombinational Logic Truth Tables Showing ll Possible unctions of Two inary ariables alse ND XOR OR NOR XNOR + + NND True The more frequently used functions have names: ND, XOR, OR, NOR, XNOR, and NND. (lways use upper-case spelling.) -6 hapter Gates, ircuits, and ombinational Logic Logic Gate Symbols for ND, OR, uffer, and NOT oolean functions Logic Gates and Their Symbols ND uffer = = Note the use of the inversion bubble. e careful about the nose of the gate when drawing ND vs. OR. OR NOT (Inverter) = + = Page

2 -7 hapter Gates, ircuits, and ombinational Logic Logic Gate Symbols for NND, NOR, XOR, and XNOR oolean functions -8 hapter Gates, ircuits, and ombinational Logic ariations of asic Logic Gate Symbols = = + = = + (a) (b) NND NOR = + Exclusive-OR (XOR) = Exclusive-NOR (XNOR) (c) + + (a) 3 inputs (b) negated input (c) omplementary outputs -9 hapter Gates, ircuits, and ombinational Logic The Inverter at the Transistor Level - hapter Gates, ircuits, and ombinational Logic Transistor ircuits = +5 = ase ollector Emitter R L out in out Output voltage Output voltage vs. Input voltage = 5 3. R L = 4? in Input voltage out out + (a) (b) (c) (d) Power terminals for an inverter made visible Transistor symbol transistor used as an inverter Inverter transfer function (a) two-input NND gate (b) two-input NOR gate - hapter Gates, ircuits, and ombinational Logic The asic Properties of oolean lgebra Relationship Dual Property = + = + ommutative ( + ) = + + = ( + )( + ) Distributive = + = Identity Principle of duality: The dual of a oolean function is gotten by replacing ND with OR and OR with ND, constant s by s, and s by s Postulates - hapter Gates, ircuits, and ombinational Logic DeMorgan s Theorem = + + = = + = Inverse = + = Null = + = Idempotence DeMorgan s theorem: + = + = ( ) = ( ) + ( + ) = ( + ) + ssociative = omplement = + + = DeMorgan s Theorem Theorems = + = + + = + ( + ) ( + ) ( + ) = ( + ) ( + ) onsensus Theorem Page

3 -3 hapter Gates, ircuits, and ombinational Logic The Sum-of-Products (SOP) orm Truth Table for the Majority unction Minterm Index Transform the function into a two-level ND-OR equation Implement the function with an arrangement of logic gates from the set {ND, OR, NOT} M is true when =, =, and =, or when =, =, and =, and so on for the remaining cases. Represent logic equations by using the sum-of-products (SOP) form -side -side balance tips to the left or right depending on whether there are more s or s. -4 hapter Gates, ircuits, and ombinational Logic The SOP orm of the Majority Gate The SOP form for the 3-input majority gate is: M = = m3 + m5 +m6 +m7 =??(3, 5, 6, 7) Each of the n terms are called minterms, running from to n - Note the relationship between minterm number and oolean value. Discuss: common-sense interpretation of equation. -5 hapter Gates, ircuits, and ombinational Logic Two-Level ND-OR ircuit Implements the Majority unction -6 hapter Gates, ircuits, and ombinational Logic our Notations Used at ircuit Intersections onnection No connection Discuss: what is the gate count? onnection No connection -7 hapter Gates, ircuits, and ombinational Logic Positive versus Negative Logic Positive logic: truth, or assertion is represented by logic, higher voltage; falsity, de- or unassertion, logic, is represented by lower voltage. Negative logic: truth, or assertion is represented by logic, lower voltage; falsity, de- or unassertion, logic, is represented by lower voltage Gate Logic: Positive vs. Negative Logic Normal onvention: Postive Logic/ctive High Low oltage = ; High oltage = lternative onvention sometimes used: Negative Logic/ctive Low -8 hapter Gates, ircuits, and ombinational Logic Positive and Negative Logic ssignments oltage levels low low low low high low high low low high high Physical ND gate high Positive logic levels = Negative logic levels = + oltage T ruth T able low low low low high low high low low high high high Positive Logic Negative Logic oltage levels low low high low high high high low high high high low Positive logic levels Negative logic levels ehavior in terms of Electrical Levels Two lternative Interpretations Positive Logic ND Negative Logic OR Physical NND gate = = + Dual Operations Page 3

4 hapter Gates, ircuits, and ombinational Logic Digital omponents - hapter Gates, ircuits, and ombinational Logic SN74 QUDRUPLE -INPUT POSITIE-NND GTES description These devices contain four independent schematic (eachgate) -inputnndgates. functiontable (each gate) package (topview) 4 k?.6 k? 3? High-level digital circuit designs are normally made using collections of logic gates referred to as components, rather than using individual logic gates. The majority function can be viewed as a component. Levels of integration (numbers of gates) in an integrated circuit (I) can be roughly considered as: Small-scale integration (SSI): gates. Medium-scale integration (MSI): gates. Large-scale integration (LSI):, logic gates. ery large scale integration (LSI):, upward. These levels are approximate, but the distinctions are useful in comparing the relative complexity of circuits. Let us consider several useful MSI components. Simplified Data Sheet for 74 NND gate INPUTS OUTPUT Y Y H H L L X H Y X L H absolute maximum ratings 4 4 4Y 3 3 3Y Y Supply voltage, 7 Input voltage: 5.5 k? Operating free-air temperature range: to 7 Storage temperature range 65 to 5 recommended operating conditions logic diagram (positive logic) MIN NOM MX UNIT Y Supply voltage IH High-level input voltage Y 3 IL Low-level input voltage.8 3Y 3 I OH High-level output current.4 m 4 4Y 4 I OL Low-level output current 6 m Y = T Operatingfree-air temperature 7 electrical characteristics over recommended operatingfree-air temperature range LUE OPERTING ONDITIONS MIN TYP M X UNIT OH = MIN, IL=.8, I OH=.4 m OL = MIN, IH=,I OL = 6 m..4 I IH = M X, I =.4 4? I IL = M X, I =.4.6 m I H = M X, I = 4 8 m I L = M X, I = 4.5 m switching characteristics, = 5,T = 5 PRMETER ROM (input) TO (output) TEST ONDITIONS MIN NOM MX UNIT t PLH R L = 4? ns or Y t PHL L = 5 p 7 5 ns - hapter Gates, ircuits, and ombinational Logic The Multiplexer (MUX) lock Diagram and Truth Table This is a 4-to- Multiplexer Data inputs D D ontrol inputs = D + D + + D D ND-OR ircuit Implementation D D - hapter Gates, ircuits, and ombinational Logic n 8- MUX an Implement the Majority unction M Principle: Use the 3 MUX control inputs to select (one at a time) the 8 data inputs -3 hapter Gates, ircuits, and ombinational Logic The Demultiplexer (DEMUX) lock Diagram and Truth Table -4 hapter Gates, ircuits, and ombinational Logic The Demultiplexer Is a Decoder with an Enable Input ircuit for a -4 DEMUX D D = D = D 3 = D 3 = D D 3 ompare to Decoder on next slide lock Diagram and Truth Table Enable D D Enable = D D 3 Enable = D D D = D = = = Page 4

5 -5 hapter Gates, ircuits, and ombinational Logic n ND ircuit for a -4 Decoder DEMUX D -6 hapter Gates, ircuits, and ombinational Logic 3-to-8 Decoder Used to Implement the Majority unction 3 D D M Enable -7 hapter Gates, ircuits, and ombinational Logic Tri-State uffers?? = or =??? = or =? -8 hapter Gates, ircuits, and ombinational Logic Programmable Logic rray PL is a customizable ND matrix followed by a customizable OR matrix OR matrix Tri-state buffer Tri-state buffer, inverted control There is a third state: high impedance. This means the gate output is essentially disconnected from the circuit. This state is indicated by? in the figure. uses ND matrix -9 hapter Gates, ircuits, and ombinational Logic Simplified Representation of a PL (Majority) (Unused) Page 5