Octal 3-State Noninverting D Flip-Flop High-Speed Silicon-Gate CMOS
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1 TECHNICAL DATA IN74AC374 Octal 3-State Noninverting D Flip-Flop High-Speed Silicon-Gate CMOS The IN74AC374 is identical in pinout to the LS/ALS374, HC/HCT374. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. Data meeting the setup and hold time is clocked to the outputs with the rising edge of the Clock. The Output Enable input does not affect the states of the flip-flops, but when Output Enable is high, the outputs are forced to the high-impedance state; thus, data may be stored even when the outputs are not enabled. Outputs Directly Interface to CMOS, NMOS, and TTL Operating oltage Range: to 6. Low Input Current: µa; 25 C High Noise Immunity Characteristic of CMOS Devices Outputs Source/Sink 24 ma ORDERING INFORMATION IN74AC374N Plastic IN74AC374DW SOIC T A = -4 to 85 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE PIN 2= CC PIN 1 = GND Output Enable Inputs Output Clock D Q L H H L L L L L,H, X no change H X X Z X = don t care Z = high impedance 426
2 MAXIMUM RATINGS Symbol Parameter alue CC DC Supply oltage (Referenced to GND) -.5 to +7. IN DC Input oltage (Referenced to GND) -.5 to CC +.5 OUT DC Output oltage (Referenced to GND) -.5 to CC +.5 I IN DC Input Current, per Pin ±2 ma I OUT DC Output Sink/Source Current, per Pin ±5 ma I CC DC Supply Current, CC and GND Pi ±5 ma P D Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Tstg Storage Temperature -65 to +15 C T L Lead Temperature, 1 mm from Case for 1 Seconds (Plastic DIP or SOIC Package) 75 5 Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditio. +Derating - Plastic DIP: - 1 mw/ C from 65 to 125 C SOIC Package: : - 7 mw/ C from 65 to 125 C mw 26 C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max CC DC Supply oltage (Referenced to GND) 6. IN, OUT DC Input oltage, Output oltage (Referenced to GND) CC T J Junction Temperature (PDIP) 14 C T A Operating Temperature, All Package Types C I OH Output Current - High -24 ma I OL Output Current - Low 24 ma t r, t f Input Rise and Fall Time (except Schmitt Inputs) IN from 3% to 7% CC CC = CC = CC = / This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, IN and OUT should be cotrained to the range GND ( IN or OUT ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or CC ). Unused outputs must be left open. 427
3 DC ELECTRICAL CHARACTERISTICS(oltages Referenced to GND) CC Guaranteed Limits Symbol Parameter Test Conditio 25 C -4 C to IH Minimum High-Level Input oltage IL Maximum Low - Level Input oltage OH Minimum High-Level Output oltage OUT = or CC - OUT = or CC - I OUT -5 µa IN = IH or IL I OH =-12 ma I OH =-24 ma I OH =-24 ma OL Maximum Low-Level Output oltage I OUT 5 µa I IN I OZ I OLD I OHD Maximum Input Leakage Current Maximum Three- State Leakage Current +Minimum Dynamic Output Current +Minimum Dynamic Output Current IN = IH or IL I OL =12 ma I OL =24 ma I OL =24 ma IN = CC or GND ± ± µa IN (OE)= IH or IL IN = CC or GND OUT = CC or GND ±.5 ± µa OLD =1.65 Max 75 ma OHD =3.85 Min -75 ma I CC Maximum Quiescent Supply Current (per Package) IN = CC or GND 8. 8 µa All outputs loaded; thresholds on input associated with output under test. +Maximum test duration ms, one output loaded at a time. Note: I IN and I are guaranteed to be less than or equal to the respective CC 428
4 AC ELECTRICAL CHARACTERISTICS(C L =5pF, Input t r =t f = ) CC Guaranteed Limits Symbol Parameter 25 C -4 C to f max Maximum Clock Frequency (Figure 1) t PLH Propagation Delay, Clock to Q (Figure 1) t PHL Propagation Delay, Clock to Q (Figure 1) t PZH t PZL t PHZ t PLZ Min Max Min Max C IN Maximum Input Capacitance pf MHz C, CC = C PD Power Dissipation Capacitance 8 pf oltage Range is ±.3 oltage Range is ±.5 TIMING REQUIREMENTS(C L =5pF, Input t r =t f = ) CC Guaranteed Limits Symbol Parameter 25 C -4 C to t su t h Minimum Setup Time,Data to Clock (Figure 3) Minimum Hold Time, Clock to Data (Figure 3) t w Minimum Pulse Width, Clock (Figure 1) oltage Range is ±.3 oltage Range is ±
5 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms EXPANDED LOGIC DIAGRAM 43
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Obsolete Product(s) - Obsolete Product(s)
SYNCHRONOUS PROGRAMMABLE 4-BIT BINARY COUNTER WITH ASYNCHRONOUS CLEAR INTERNAL LOOK-AHEAD FOR FAST COUNTING CARRY OUTPUT FOR CASCADING SYNCHRONOUSLY PROGRAMMABLE LOW-POWER TTL COMPATIBILITY STANDARDIZED
74AUP1G74. 1. General description. 2. Features and benefits. Low-power D-type flip-flop with set and reset; positive-edge trigger
Low-power D-type flip-flop with set and reset; positive-edge trigger Rev. 9 6 January 2014 Product data sheet 1. General description The provides a low-power, low-voltage single positive-edge triggered
74HC4002; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NOR gate
Rev. 5 26 May 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 4-input NOR gate. Inputs also include clamp diodes that enable the use of current
74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register
74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register General Description The 74F675A contai a 16-bit serial in/serial out shift register and a 16-bit parallel out storage register. Separate serial
74HC74; 74HCT74. 1. General description. 2. Features and benefits. 3. Ordering information
Rev. 5 3 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual
74HC157; 74HCT General description. 2. Features and benefits. Quad 2-input multiplexer
Rev. 8 28 December 2015 Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC standard
74ALVC164245. 16-bit dual supply translating transceiver; 3-state. This device can be used as two 8-bit transceivers or one 16-bit transceiver.
Rev. 8 15 March 2012 Product data sheet 1. General description The is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The is a 16-bit
74HC573; 74HCT573. Octal D-type transparent latch; 3-state. The 74HC573; 74HCT573 is functionally identical to:
Rev. 5 5 ugust 202 Product data sheet. General description 2. Features and benefits The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in
MM74HC74A Dual D-Type Flip-Flop with Preset and Clear
MM74HC74A Dual D-Type Flip-Flop with Preset and Clear Features Typical propagation delay: 20ns Wide power supply range: 2V 6V Low quiescent current: 40µA maximum (74HC Series) Low input current: 1µA maximum
. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54/M74HC190 M54/M74HC191 4 BIT SYNCHRONOUS UP/DOWN COUNTERS. fmax = 48 MHz (TYP.
M54/M74HC190 M54/M74HC191 4 BIT SYNCHRONOUS UP/DOWN COUNTERS. HIGH SPEED fmax = 48 MHz (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) AT T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.)
MADR-009443-0001TR. Quad Driver for GaAs FET or PIN Diode Switches and Attenuators. Functional Schematic. Features. Description. Pin Configuration 2
Features Functional Schematic High Voltage CMOS Technology Four Channel Positive Voltage Control CMOS device using TTL input levels Low Power Dissipation Low Cost 4x4 mm, 20-lead PQFN Package 100% Matte
3-input EXCLUSIVE-OR gate. The 74LVC1G386 provides a 3-input EXCLUSIVE-OR function.
Rev. 02 3 September 2007 Product data sheet 1. General description The provides a 3-input EXCLUSIVE-OR function. The input can be driven from either 3.3 or 5 V devices. This feature allows the use of these
74HC4040; 74HCT4040. 12-stage binary ripple counter
Rev. 5 3 February 2016 Product data sheet 1. General description 2. Features and benefits 3. Applications 4. Ordering information The is a with a clock input (CP), an overriding asynchronous master reset
INTEGRATED CIRCUITS DATA SHEET. 74HC08; 74HCT08 Quad 2-input AND gate. Product specification Supersedes data of 1990 Dec 01.
INTEGRTED CIRCUITS DT SHEET Supersedes data of 1990 Dec 01 2003 Jul 25 FETURES Complies with JEDEC standard no. 8-1 ESD protection: HBM EI/JESD22-114- exceeds 2000 V MM EI/JESD22-115- exceeds 200 V. Specified
CD74HC4046A, CD74HCT4046A
February 99 SEMICONDUCTOR CD7HC6A, CD7HCT6A High-Speed CMOS Logic Phase-Locked-Loop with VCO Features Operating Frequency Range - Up to MHz (Typ) at = 5V - Minimum Center Frequency of MHz at Choice of
DM74LS151 1-of-8 Line Data Selector/Multiplexer
1-of-8 Line Data Selector/Multiplexer General Description This data selector/multiplexer contains full on-chip decoding to select the desired data source. The DM74LS151 selects one-of-eight data sources.
CD4511BC BCD-to-7 Segment Latch/Decoder/Driver
CD4511BC BCD-to-7 Segment Latch/Decoder/Driver General Description The CD4511BC BCD-to-seven segment latch/decoder/ driver is cotructed with complementary MOS (CMOS) enhancement mode devices and NPN bipolar
74HC4067; 74HCT4067. 16-channel analog multiplexer/demultiplexer
Rev. 6 22 May 2015 Product data sheet 1. General description The is a single-pole 16-throw analog switch (SP16T) suitable for use in analog or digital 16:1 multiplexer/demultiplexer applications. The switch
CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset
CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset General Description These dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-