Practical ARM CPU Digital Implementation on TSMC 10nm. Yin Yan, Cadence Design Systems ARM Tech Symposia Shenzhen November 2015
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1 Practical ARM CPU Digital Implementation on TSMC 10nm Yin Yan, Cadence Design Systems ARM Tech Symposia Shenzhen November 2015
2 Outline ARM + Cadence Collaboration 10nm Design (Synthesis, Implementation, Signoff) Challenges 10nm Design Flow for High-end ARM CPU Implementation Cadence Advanced Node 10nm RTL2Signoff Flow and Unique Solutions Foundry Qualification of Cadence Tools Summary Cadence Design Systems, Inc. All rights reserved.
3 ARM and Cadence Collaboration Ongoing close collaboration on ARM CPUs, ARM Mali GPUs, system IP, embedded processors, ARM Artisan libraries, and ARM POP IP Cadence and ARM engineering relationship at all ARM design locations worldwide Engineering teams at Cambridge/Sheffield, Sophia, San Jose, Austin, Bangalore, and Hsinchu Cadence and ARM have collaborated throughout the entire development of multiple cores to drive technology leadership in the ecosystem for power, performance, and area (PPA) goals ( ) Trial implementations being run in parallel by both ARM and Cadence Regular interaction with Cadence AEs and R&D ARM uses Cadence tools and flow internally for high-performance processor and GPU development ARM + Cadence collaborative work-around reference flow development Testchips currently include ARM Cortex -A72, A57, A53, A15, A12, A9, and A7, plus POP IP and Cortex- M embedded processors such as M7 and others Cadence Design Systems, Inc. All rights reserved. 3
4 ARM and Cadence Projects History Legend: irm Testchip cmos32lp Cortex- A15 irm Implementation Reference Methodology Samsung 20nm testchip Hardened Macro cmos32lp 20nm Cortex- A15 testchip IBM 20nm testchip 28nm 28nm Cotex- A57 irm 28nm Cortex- A7 irm Cortex- A7 irm 28nm Samsung 20nm testchip GPU Mali- T604 irm 40nm POP IP Dual-core Cortex-A9 28nm 28nm Cortex-A9 Hard macro Quad-core Cortex-A15 IBM ARM 14nm FINFET testchip Samsung A7 14nm FINFET Cortex- A53 irm 28nm Mali-T678 irm 28nm ARMv8 ARM big.little + GPU Testchip Cortex- A53 Next-gen Mali Cortex-A15 R3 irm Update 16nm Cortex-A57 Cortex- A57 28nm Dual-core Cortex-A15 Cortex-A12 irm GF 28nm Cortex-A12 CCN-504 irm CCN-504 irm 16nm Cortex- A53 /A57 Next-gen System IP irm 28nm Cortex-A17 irm Cortex-A15 LP irm 28nm Mali-T720 irm Cortex-A57 irm refresh Cortex-M7 irm GF 28nm Cortex-A17 16nm Cortex- A53 /A57 PPPA Push Cortex- A72 irm 16nm 40nm 16nm Next-gen GPU Mail- T880 ARMv8 ARM big.little + GPU Testchip Next-Gen Big Core Next-gen core Foundry Adv node Cortex- A ARM and Cadence are successfully engaged in several joint projects Cadence Design Systems, Inc. All rights reserved.
5 ARM and Cadence Collaborating on 10nm A global collaborative program to develop advanced process eco-systems Ensure ARM next generation CPU IP is optimized for advanced process Ensure EDA eco-system and design flows are ready for lead partners Provide feedback on power, performance and area bottlenecks to ARM design teams Identify additional physical IP requirements for optimal PPA Educate partners and accelerate next generation process adoption Proven successful approach following on from 16nm collaboration Cadence Design Systems, Inc. All rights reserved. 5
6 Outline ARM + Cadence collaboration 10nm design (synthesis, implementation, signoff) challenges 10nm design flow for high-end ARM CPU implementation Cadence Advanced Node 10nm RTL2Signoff flow and unique solutions Foundry qualification of Cadence tools Summary Cadence Design Systems, Inc. All rights reserved.
7 Design challenges at 10nm 10nm Full coloring flow required in P&R, extraction, DRC Use of M1/M2 to be H/V impacts cell architecture and routability Significant increase of critical rules for router and placement 16nm 2 nd gen FinFET Physical 20nm 1 st gen DPT Exponential wire Res 1 st gen FinFET Fin-grid snapping Pin-access 2 nd gen DPT Coloring a Must! Color-driven Implementation Resistance increase on wire and vias (Mx and Vx). Variability (wire width, spacing) Different color tracks may have dramatic resistance difference. Length-based coupling cap handling Expect the need for more accuracy in timing and variation Route-driven Implementation Electrical Cadence Design Systems, Inc. All rights reserved.
8 Accelerating 10nm Adoption Start early so that IP, tools and process can be optimized at the same time Ensure ARM IP, process and EDA tools are co-optimized to: Provide best in class silicon implementations of ARM based systems Pipe-clean the eco-system for ARM partner designs Lower the barrier to entry for new process adoption Reduce time to market through optimized products and support Early Process Exploration Eco-system Development Library Development PPA Optimization Deployment Cadence Design Systems, Inc. All rights reserved.
9 Typical Process Design Rules SoC Design Complexity ARM CPU 10nm Challenges An evolution from 16nm FinFET 7000 Focus on efficiency Optimize performance within established mobile device power budgets Power grid integrity is crucial Meeting electromigration and IR drop targets whilst maintaining placement density Interconnect (wire) resistance continues to dominate Use of optimized physical libraries more critical Maximize the benefits of process scaling Cadence Design Systems, Inc. All rights reserved.
10 Outline ARM + Cadence collaboration 10nm design (synthesis, implementation, signoff) challenges 10nm design flow for high-end ARM CPU implementation Cadence Advanced Node 10nm RTL2Signoff flow and unique solutions Foundry qualification of Cadence tools Summary Cadence Design Systems, Inc. All rights reserved.
11 Design Flow Considerations Understand critical differences between 16nm and 10nm design flows Primary goal is to tweak the flow recipe and understand tool/ip interaction Impact of new CPU uarchitecture Feedback on tool, library, and IP interactions Optimizing floorplan, power distribution, and overall power, performance and area Traverse the entire flow from RTL to production quality sign-off All issues uncovered and validated Iterate and improve as IP, process, and libraries mature Cadence Design Systems, Inc. All rights reserved.
12 Synthesis Strategy Exploration to understand power and performance envelope Selecting the right Vt mix for design PPA targets Analyze library usage for potential bottlenecks Dominant cell type on critical paths Based on Cadence recommended flow Tuning of parameters for optimal PPA trade-offs Physical aware mapping Ensure correlation and predictability through flow Synthesis targets single Vt and channel length Based on performance and power targets Cadence Design Systems, Inc. All rights reserved.
13 The Genus Advantage Significant run time and overall QoR benefits Improved correlation through the flow Increased performance with minimal leakage impact Synthesis run time over 4x faster (~3 hours) Cadence Design Systems, Inc. All rights reserved.
14 Floorplan New process and processor combination Floorplan trials are critical Macro placement changes with process Use of placement regions based on uarchitectural feedback Macro placement needs to follow finfet grid Must align double pattern layer M2 memory pins to ensure correct coloring Cadence Design Systems, Inc. All rights reserved.
15 Power Grid Incorrect power grid construction will significantly impact routing density and performance No metal 2-standard cell power connection Potential EM and dynamic IR implications Vertical power straps need to follow FinFET grid Horizontal straps must follow even poly pitch Both runs: Cortex-A9 CPU with the same power grid pitches Good design has optimally placed M3 straps Bad design has suboptimal placement of M3 straps, blocking unnecessary routing tracks Traditional striped PG methodology used Cadence Design Systems, Inc. All rights reserved.
16 Place & Route Place and route uses single Vt/Channel length library Timing and power is optimized against dominant corners Balance of run time vs overall QoR Placement is DRC aware Respects interaction between standard cells Control of wire dominated paths is crucial Using placement bounds to constrain potential long paths Layer promotion for long nets to less resistive metal layers Waveform propagation models and AOCV essential at 10nm Cadence Design Systems, Inc. All rights reserved.
17 Sign-Off Full production quality sign-off approach TSMC recommended timing margins Signed-off for timing, power integrity & physical rules Cadence Voltus solution used for all power integrity checks Static/dynamic IR, electro-migration, in-rush current Signed-off and optimized across multiple PVT and extraction corners Leakage recovery performed using Tempus ECO functionality Power analysis early and often to ensure PG structure is correct Stage based OCV critical to avoid over-fixing Cadence Design Systems, Inc. All rights reserved.
18 Design Flow Implemented using Cadence tools Full production quality DFT solution Full scan compression Memory BIST At speed scan and memory BIST support Power domain per CPU core Full production margins for timing, power and physical sign-off Cadence Full-Flow Digital Solution Cadence Design Systems, Inc. All rights reserved.
19 Outline ARM + Cadence collaboration 10nm design (synthesis, implementation, signoff) challenges 10nm design flow for high-end ARM CPU implementation Cadence Advanced Node 10nm RTL2Signoff flow and unique solutions Foundry qualification of Cadence tools Summary Cadence Design Systems, Inc. All rights reserved.
20 Cadence Full-Flow Digital Solution vs. Previous Generation Unified Placement Engine Best-in-Class PPA Optimization Unified Timing/Power/Extract Unified CTS, Global Router Traditional Flow placer Opt timing Synthesis Cadence Full-Flow Digital Solution 10-20% Better PPA Up to 10X TAT/Capacity Gain placer router Opt CTS timing power extract Implementation CTS Full-Flow Correlation Design Convergence timing power extract Signoff Massively Parallel Unified Engines Core PPA Algorithms Early Signoff Opt Reduced iterations Cadence Design Systems, Inc. All rights reserved.
21 Innovus Technology GigaPlace next-generation placement GigaOpt power-driven optimization Advanced CCOpt and slackdriven routing H-tree Slack-driven, layer-aware, fully analytic All GigaOpt transforms made power-aware Minimizes leakage, internal and switching power FlexH Regular CTS tree Flex H-tree improves cross-corner variation Slack-driven routing reduces SI TNS Cadence Design Systems, Inc. All rights reserved.
22 Innovus: 10nm color-driven implementation Netlist GigaPlace Placer Unique correct-byconstruction approach GigaOpt CCOpt M2 Power Prevents oddcycle conflicts Nano NanoRoute Route Massively parallel for increasing rule conflicts Cadence Design Systems, Inc. All rights reserved.
23 10nm color-driven placement and routing NanoRoute via odd-cycle prevention Color-driven GigaPlace technology Actively prevents pin-access that causes odd-cycles Status of SADP-enabled Innovus System Cadence Design Systems, Inc. All rights reserved.
24 Color-driven GigaPlace technology Netlist GigaPlace Giga Placer Place GigaOpt CCOpt Fixed color placement Vertical edge constraints Placement considering power buses and power bus via Global placement for routability improvement Boundary (endcap) cell insertion Nano NanoRoute Route Cadence Design Systems, Inc. All rights reserved. Power Bus
25 Color-driven NanoRoute technology Netlist GigaPlace Giga Placer Place GigaOpt CCOpt Nano NanoRoute Route All 10nm rules. Enhance pin access to handle large same-mask cut spacing. Fat M2 pin handling: track alignment and rules. Fixed color methodology: users define color/mask in cell library M1 routing. One side spacing of NDR, mask-ndr Cadence Design Systems, Inc. All rights reserved. Power Bus
26 Production-proven Genus and Innovus speedup Genus TAT speedup Cadence Design Systems, Inc. All rights reserved.
27 Outline ARM + Cadence collaboration 10nm design (synthesis, implementation, signoff) challenges 10nm design flow for high-end ARM CPU implementation Cadence Advanced Node 10nm RTL2Signoff flow and unique solutions Foundry qualification of Cadence tools Summary Cadence Design Systems, Inc. All rights reserved.
28 10nm color-driven Cadence digital flow Innovus Implementation System PreRoute Statistical RC Extraction Statistical OCV-driven Optimization Color-Aware Track Assignment Quantus QRC 10nm extraction certification Colored aware resistance change Length based coupling cap handling. Close 10nm collaboration with IP/foundry partners Tempus, Voltus, PVS Solutions 10nm STA qualification, SOCV, SOCV-Driven MMMC Sign-Off ECO Color-aware EM /IR Color-aware Metal Fill, Fill ECO Cadence Design Systems, Inc. All rights reserved.
29 Outline ARM + Cadence collaboration 10nm design (synthesis, implementation, signoff) challenges 10nm design flow for high-end ARM CPU implementation Cadence Advanced Node 10nm RTL2Signoff flow and unique solutions Foundry qualification of Cadence tools Summary Cadence Design Systems, Inc. All rights reserved.
30 Summary Cadence and ARM continue to collaborate on advanced process nodes Our proven successful collaboration model accelerates adoption and time to market for our partners 10nm has arrived, and the eco-system is ready for your next ARM-based chip Cadence Design Systems, Inc. All rights reserved.
31 Cadence Design Systems, Inc. All rights reserved. Come visit us in Cadence Booth
32 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems. ARM and the ARM logo are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. PCI-SIG, PCI Express, and PCIe are registered trademarks and/or service marks of PCI-SIG. All other trademarks are the property of their respective owners.
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