Engineer-to-Engineer Note

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1 Engineer-to-Engineer Note EE-307 Technicl notes on using Anlog Devices DSPs, processors nd development tools Visit our Web resources nd or e-mil or for technicl support. Blckfin Processor Troubleshooting Tips Using VisulDSP++ Tools Contributed by Jorge Mngune Rev 1 December 11, 2006 Introduction This document describes debug fetures of Blckfin processors nd the VisulDSP++ development tools. By pplying the tips below, progrmmers cn nrrow down the cuse of n encountered problem before reporting it to the Anlog Devices embedded processor support tem. This will help to solve the issue quickly. Debugging Tips nd Tricks The following topics re covered: Running n ppliction vi n emultor versus booting the ppliction. Specificlly, SDRAM initiliztion considertions re ddressed. Unlocking core B for dul-core processors. The emultor does this utomticlly; however, when code is booted in, core B must be unlocked mnully. Hrdwre errors nd softwre exceptions Blckfin processor debug fetures nd tools, including: Trce buffer Brekpoints (softwre, embedded, nd hrdwre) VDK debugging (VDK Sttus window nd VDK Stte History window) Debugging issues when cche is enbled Interrupts This EE-Note does not cover issues ssocited with troubleshooting peripherls. Emultion vs. Stndlone Booting The emultor softwre uses.xml files to configure resources such s SDRAM timing on n EZ-KIT Lite evlution bord. There re defult.xml files for ll Blckfin processors for which n evlution pltform exists (i.e., the EZ- KIT Lite bords), where definitions re creted to initilize certin registers upon emultor connection. For exmple, the following is n excerpt from the ADSP-BF537-proc.xml file for the ADSP- BF537 Blckfin processor: <register-reset-definitions> <register nme="ebiu_sdrrc" resetvlue="0x03a0" core="common" /> <register nme="ebiu_sdbctl" resetvlue="0x25" core="common" /> <register nme="ebiu_sdgctl" resetvlue="0x d" core="common" /> <register nme="ebiu_amgctl" resetvlue="0xff" core="common" /> </register-reset-definitions> Thus, when developing n ppliction for the ADSP-BF537 EZ-KIT Lite bord, the SDRAM is initilized utomticlly when the emultor softwre is invoked. However, when moving to stndlone ppliction (tht is, booting the ppliction rther thn downloding it using n emultor), it is the Copyright 2006, Anlog Devices, Inc. All rights reserved. Anlog Devices ssumes no responsibility for customer product design or the use or ppliction of customers products or for ny infringements of ptents or rights of others which my result from Anlog Devices ssistnce. All trdemrks nd logos re property of their respective holders. Informtion furnished by Anlog Devices pplictions nd development tools engineers is believed to be ccurte nd relible, however no responsibility is ssumed by Anlog Devices regrding technicl ccurcy nd topiclity of the content provided in Anlog Devices Engineer-to-Engineer Notes.

2 user s responsibility to enble the SDRAM controller if SDRAM memory is used in the system. This is ccomplished by including n initiliztion file vi the Loder pge of the Project Options dilog box pge when creting loder file. See ADSP-BF533 Blckfin Booting Process (EE-240) [1]. Another difference tht cn cuse issues when moving n ppliction from n emultor session to booting stndlone is relted to ADSP-BF561 Blckfin dul-core systems. By defult, the emultor softwre unlocks core B nd llows it to run from the beginning of L1 instruction memory. When both cores re to be used, core B must be unlocked by core A by clering bit 5 of the system reset configurtion register (SICA_SYSCR). Another issue tht sometimes occurs s result of the emultor unlocking core B is with regrd to chnging operting modes or clock frequencies. Specificlly, core B must be in the idle stte (not simply t brekpoint) when mking chnges to the PLL or voltge regultor. This cn cuse trouble if, for exmple, brekpoint is set in core B nd code is run on core A tht chnges the PLL frequency. Be sure to run code tht plces core B into the idle stte prior to chnging the PLL frequency. This cn be done using supplementl interrupts or GPIO pins. Hrdwre Errors nd Softwre Exceptions Hrdwre errors nd softwre exceptions re two specific types of events tht cn occur on Blckfin processors. Ech of these events hs seprte entry in the event vector tble (EVT). Hndlers should be instlled for ech of these events so tht they cn be trpped by using ny of the brekpoint methods described lter in this document. At tht point, the stte of the processor cn be exmined to understnd wht cused the prticulr event. The sequencer sttus register (SEQSTAT) hs two fields tht cn be used to gin more insight into the offending condition. The HWERRCAUSE field is used to identify the condition tht generted hrdwre error, nd the EXCAUSE field is used to identify the condition tht generted n exception. A hrdwre error cn be generted for vriety of resons, such s when n MMR is ccessed with the wrong word size (e.g., 16-bit MMR is ccessed s 32-bit, or vice vers) or when the core or DMA controller tries to ccess reserved or uninitilized memory spce. The RETI ddress will contin n ddress within 10 loctions of the offending loction. If hrdwre errors re enbled nd the event is serviced, the condition will cler, but the hrdwre error cuse will remin with the lst error condition. For ADSP-BF561 Blckfin dul-core processors, hrdwre errors generted by specific core will only cuse n error on tht core. If the DMA controller genertes hrdwre error, the error is sent to both cores. In ech of the hndlers (hrdwre error or exception) the HWERRCAUSE nd EXCAUSE fields cn be red to identify the cuse of the event. Alterntively, when using n emultor to debug, trp instructions cn be plced in the hndlers, such s emuxcept, so tht the processor will stop running whenever hrdwre error nd/or n exception occurs. The pproprite field in the SEQSTAT register cn then be inspected to determine the cuse of the event. Now tht the cuse of the event is known, the ddress of the offending instruction should be noted to determine when the problem occurred in the progrm. For exceptions, the return from exception register (RETX) contins the ddress of the offending instruction or the ddress of the next instruction to be executed. The ddress in RETX depends on the type of exception: service (S) or error (E). The ADSP-BF53x/BF56x Blckfin Processor Progrmming Reference [2] lists the events tht cuse exceptions, s well s their type (service or error). For convenience, this tble is included in Appendix A. Blckfin Processor Troubleshooting Tips Using VisulDSP++ Tools (EE-307) Pge 2 of 11

3 For error type exceptions, RETX holds the ddress of the offending instruction; for service type exceptions, RETX holds the ddress of the next instruction fter tht of the offending instruction. At this point, the offending instruction cn be exmined for further insight into the problem. Is the instruction ccessing memory which hs no vlid CPLB definition? Is the instruction performing memory lod/store from/to misligned loction? Does the pointer or index register point to n invlid memory region? A brekpoint cn be set in the vicinity of the instruction tht cused the hrdwre error or exception, nd the code cn be single-stepped while observing the ddress registers (Ix or Px). Setting brekpoints nd/or stepping through the code prior to the instruction of interest sometimes chnges the behvior of the problem (i.e., the problem cn no longer be observed under these conditions). In cses like this, the brekpoint cn be plced pst the instruction of interest nd the stte of the processor cn be exmined when the brekpoint is encountered. Note tht the processor will hve vectored off to the event hndler, so the brekpoint is plced t the first instruction in the event hndler (exception hndler or hrdwre error hndler). Using the Trce Buffer A 16-slot trce buffer, vilble on Blckfin processors, llows the lst 16 non-contiguous chnges of flow (excluding zero-overhed hrdwre loops) to be cptured. The informtion in the trce buffer cn be instrumentl in determining the cuse of problem or, more importntly, in nrrowing down the problem such tht smll test cse cn be derived tht consistently shows the unexpected behvior. In the previous section, methods to identify the instruction which cuses prticulr event were described; however, in mny cses, tht sme instruction in isoltion would not exhibit the problem. It is wht hppens before the instruction is fetched nd executed (in some cses it does not mke it to the execution stge) tht is criticl in zeroing in on the root cuse. For exmple, consider n instruction tht performs memory lod using the P2 register. Immeditely before executing this instruction, n interrupt is tken, which, through bd progrmming prctice, does not sve nd restore the registers it uses. The ISR code modifies the pointer register P2 nd, upon returning from the interrupt service routine, the originl memory lod instruction is executed. However, P2 no longer points to the desired memory loction becuse it ws overwritten during n synchronous event, which could result in ny one of the events previously discussed. More subtly, the dt is written/red to/from the wrong memory. The ltter is typiclly hrder to detect. The trce buffer llows chnges of flow tht took plce before the problem occurred to be seen esily in window. It records the lst 16 pirs of discontinuities. The first entry in the pir is the source of the discontinuity (i.e., cll instruction), nd the second entry is the destintion, or trget, of the discontinuity (i.e., the first instruction of the clled function). In the bove P2 exmple, the first instruction of given trce pir would be return from interrupt instruction (RTI), nd the second entry in the pir would be the lod instruction or n instruction before it. Since the trce buffer lso shows the ddresses of the discontinuities, the ddress of the RTI instruction cn be inspected in the ISR to find tht P2 ws modified nd never restored before exiting the ISR. This ISR could be prt of scheduler of n RTOS tht the ppliction uses. Of course, the exmple discussed here is very simplistic. It could turn out tht the ISR did not implement workround to known issue. There will be times when nothing is pprent (i.e., with ll this nlysis, why the problem occurs still cnnot be explined). Knowing the trnsitions tht took plce before the problem ws encountered cn help crete smll test cse, which cn be very helpful to the support Blckfin Processor Troubleshooting Tips Using VisulDSP++ Tools (EE-307) Pge 3 of 11

4 tem to quickly investigte nd resolve the problem. Figure 1 shows how entries re structured in trce buffer. The leftmost column lists the cycles from 0 to 31. Cycles 0 nd 1 re the lst pir of discontinuities recorded in the trce buffer, cycles 2 nd 3 re the penultimte pir, etc. The second column from the left shows the grouping of the pirs. For exmple, cycles 0 nd 1 re the 15th pir (0xf), cycles 2 nd 3 re the 14th pir (0xe), nd cycles 0x1e nd 0x1f re the zero pir (0x0). The first instruction of the pir is the source of the discontinuity, nd the second instruction is the destintion of the discontinuity. For the 0xf pir, cycle 0 is the source ddress (the RTS instruction), nd cycle 1 is the destintion instruction (CALL Initilize 3VDKFv). Tht is, this instruction is executed first fter returning from the subroutine ending t ddress 0xff086be. execution hlts when tht line of code is hit. However, behind the scenes, the vlue of the loction where the brekpoint is plced is cched within the emultor. The emultor reds the memory t the brekpoint loction nd sves it to the emultor s internl brekpoint list. When the ppliction is run, it plces trp instruction t tht loction. When ny brekpoint is hit, or ny hlt event occurs, the trp instruction t the brekpoint loction is replced by the instruction tht ws previously cched. Clerly, this suggests tht softwre brekpoints re intrusive in nture. Thus, mny encountered problems my seem to go wy when softwre brekpoints re used to dignose the problem becuse the timing of the ppliction hs chnged due to the nture of softwre brekpoints. Figure 2 shows wht softwre brekpoint looks like in VisulDSP++ IDDE session. Figure 2. Softwre Brekpoint Exmple Figure 1. Trce Buffer Exmple Using Brekpoints This section describes differences between softwre, embedded, nd hrdwre brekpoints, nd explins when nd how to use them. Softwre Brekpoints Softwre brekpoints re convenient nd esy to use. Simply double-click on n instruction in the editor (source) window or the Disssembly window of the IDDE to set the brekpoint, nd Embedded Brekpoints An embedded brekpoint is prt of the ppliction code itself. It is similr to softwre brekpoints, except tht the debugger does not need to look up brekpoint tble list or insert hlting op-codes into the ppliction. As such, this clss of brekpoints is qusi-non-intrusive. The emuexcpt instruction cuses the processor to hlt when executed. This instruction only hs mening when n emultor is connected; otherwise, it cts s NOP. It is good prctice to use embedded brekpoints inside event hndlers becuse, other thn using code spce, they do not ffect the timing of the ppliction, thus llowing for the stte of the processor to be observed confidently soon fter the event occurred. Used in conjunction with the trce buffer informtion, Blckfin Processor Troubleshooting Tips Using VisulDSP++ Tools (EE-307) Pge 4 of 11

5 now you cn observe the stte of the processor nd cn lso observe the trnsitions tht took plce right before n event occurred. Figure 3 shows n exmple of n embedded brekpoint. Figure 3. Embedded Brekpoint Exmple Hrdwre Brekpoints On the other hnd, hrdwre brekpoints re completely non-intrusive, s they do not lter the ppliction code in ny wy. Insted, hrdwre brekpoints rely on physicl hrdwre logic on the chip, which monitors both the instruction nd dt buses. On Blckfin processors, hrdwre brekpoints re implemented by the wtchpoint register unit. There re six instruction wtchpoint registers nd two dt wtchpoint registers. Instruction hrdwre brekpoints cn be set on six specific instruction ddresses or on three instruction ddress rnges. Dt hrdwre brekpoints cn be set on two specific dt ddresses or on one dt ddress rnge. Hrdwre brekpoints cn be used in RAM or ROM types of memory. To enble hrdwre brekpoints from within the VisulDSP++ IDDE, go to Settings nd select Hrdwre Brekpoints. Figure 4 shows one of the Instruction pges of the Hrdwre Brekpoints window. Figure 4. Hrdwre Brekpoints (Instruction) The instruction ddress or ddress rnge cn then be specified to force hlts to the processor when these instructions re bout to be executed. For dt ccesses, the type of ccess must be specified (red, write, or both), to trigger n emultion hlt. Figure 5 shows the Dt pge of the Hrdwre Brekpoints window. Figure 5. Hrdwre Brekpoints (Dt) The code cn then be run, nd the processor will hlt if mtch is seen between the internl instruction/dt ddress bus nd the ddress specified in the hrdwre brekpoint registers. Blckfin Processor Troubleshooting Tips Using VisulDSP++ Tools (EE-307) Pge 5 of 11

6 Hrdwre brekpoints provide skip count feture, which cn be used to indicte how mny times to ignore ccesses to the specified region before the processor is hlted. For exmple, if skip count is set to 0xA, the processor will hlt on the 10 th occurrence of the ddress mtch. VisulDSP++ Kernel (VDK) VDK is rel-time kernel tht simplifies the mngement of projects with multiple tsks. However, it dds level of bstrction to the ppliction. Due to this, just like ny RTOS, it mkes it tht much hrder to pinpoint bugs in the system. VisulDSP++ hs kernel-wre debugger tht cn disply system performnce detils, which cn help in ppliction tuning nd in debugging n RTOS-bsed system. It llows you to visulize the vrious threds t ny given time (i.e., running, blocked, redy, etc.). Among other debug needs, this my be instrumentl in identifying why prticulr thred never gets to run. Figure 6 shows the VDK Stte History window. Ensure tht thred priorities re set ppropritely. You should know ech tsk s needs in terms of run time. The VDK Stte History window cn be instrumentl in identifying overll thred time blncing. Another useful debug window, the VDK Sttus window, displys the cuse of kernel pnic error. Figure 7 shows the VDK Sttus window. Figure 7. VDK Sttus Window The exmple in Figure 7 shows stck overflow, which cused the kernel pnic. The indicted Vlue identifies the thred (IDLE thred) whose stck size is insufficient. Cche-Relted Issues When cche problem is suspected, first consult the pproprite processor nomly list to verify whether the prticulr observed behvior hs been chrcterized there. Figure 6. VDK Stte History Window If the unexpected behvior does not pper to be relted to known issue, try to rule out the cche controller s the cuse by moving the region of interest into L1 memory. The previous sections showed how to identify this region. Run the ppliction with cche turned on, nd then run it second time with cche turned off. Observe ny differences in behvior. If the problem is still present with the cche turned off, it could indicte rce condition in the softwre ppliction. Turning cche off my chnge the timing for the rest of the ppliction, cusing the filure to stop occurring. Becuse of this, try Blckfin Processor Troubleshooting Tips Using VisulDSP++ Tools (EE-307) Pge 6 of 11

7 bringing the region of interest into L1 nd leve the cche turned on. If the problem persists nd n exception nd/or hrdwre error is generted in the region of the code tht is in L1, it is not cche integrity issue. If exceptions re present, refer to Hrdwre Errors nd Softwre Exceptions bove. Cche Coherency Blckfin processors do not mintin coherency between cche memory nd min memory. Typiclly, coherency will be n issue in systems where peripherl DMA chnnel ccesses region of externl memory defined s ccheble. The cche controller hs no knowledge of these ccesses nd, s result, my use its stle (old) dt for computtions, thus producing unexpected results. Softwre must ensure tht coherency is mintined by invlidting lines tht might hve been ccessed by DMA controller. Interrupt-Relted Issues In the ISR, ensure tht the pushing nd popping of resources is done in the correct order. Also, note the significnce of pushing nd popping RETI. When RETI is pushed onto the stck, interrupt nesting is enbled; conversely, popping RETI disbles interrupt nesting. So, if higher priority interrupts should not interrupt the interrupt service routine, do not push RETI onto the stck. If progrmming in C/C++, use the nonnested interrupt hndler: EX_INTERRUPT_HANDLER(Timer_hndler) If interrupt nesting should be enbled for prticulr ISR, use the following interrupt hndler: EX_REENTRANT_HANDLER(Timer_hndler) This reentrnt hndler pushes RETI t the beginning of the ISR nd pops it t the end, right before the RTI is executed. To prevent repeted vectoring to the sme ISR, cler the cuse of the interrupt in the ISR before exiting. For exmple, for core timer, clering the TINT (timer interrupt) bit in the core timer control register will cler the interrupt. When using nested interrupts, be sure to void problems tht my rise due to using shred resources. Minimizing n ISR s execution time llows lower-priority ISRs to lso be serviced in timely mnner. Keeping ISRs short lso reduces the number of used resources within the ISR, thus lleviting stck usge. Another type of problem tht rises with nested interrupts is stck overflow. One wy to detect stck overflow in nested interrupts (or even in deeply nested subroutines) is to red the stck pointer (SP) t the beginning of every ISR to check if the pointer is nering the end of the stck. Summry This EE-Note describes VDK tools nd Blckfin processor fetures tht re vilble to help nrrow down problems. First nd foremost, lwys check the nomly list for the silicon revision of the processor used to verify whether the problem is lredy known. If it is, implement the given workround. To get utomted softwre support for known silicon errt, ensure tht the ltest tools re being used nd tht silicon workrounds re enbled. Applictions should instll event hndlers (exception hndlers, interrupt hndlers) before running the min ppliction so you cn trp events when necessry. Verify the behvior. Wht exctly is not working properly? Are exceptions/hrdwre errors being generted? If so, wht exception nd/or hrdwre error? The tbles in Appendix A will help determine this. Are the peripherls overflowing/underflowing? Are DMA errors being generted? Find wys to increse repetbility. Although not lwys possible, incresing the frequency with which problem occurs enhnces the chnce of Blckfin Processor Troubleshooting Tips Using VisulDSP++ Tools (EE-307) Pge 7 of 11

8 fixing the problem. Incresing repetbility could men incresing or shortening loop itertions, chnging the core voltge, djusting the core nd/or system frequencies, etc. It should be noted tht only one vrible should be chnged t time. If the modified vrible hs no effect on the bug, leve the vrible s it ws before new modifiction is mde. Use softwre brekpoints to observe processor stte prior to the triggering of the fult. If the filure stops occurring when softwre brekpoints re inserted, then either use embedded or, ultimtely, hrdwre brekpoints. If hrdwre errors/exceptions re generted, find the respective cuses from the sequencer sttus register nd check the tbles in Appendix A to see wht might hve generted those events. Trp the events in the respective exception hndlers by using embedded brekpoints or hrdwre brekpoints. Use the Trce window to observe processor trnsitions prior to the occurrence of the problem. Sve ll registers for post nlysis by choosing Register->Sve Registers in VisulDSP++, s shown in Figure 8. Figure 8. Sve Registers Feture If, fter the steps described bove, the fult cnnot be corrected, hving the knowledge of the sequence of events tht triggers the unexpected behvior should llow for smll test cse to be generted. Once test cse is vilble, summrize your findings for the embedded processor support tem nd include the test cse. This will llow for rpid reproduction of the issue, which will ultimtely help get the issue resolved. Blckfin Processor Troubleshooting Tips Using VisulDSP++ Tools (EE-307) Pge 8 of 11

9 Appendix A Tble 1. Events tht Cuse Exceptions Exception Force Exception instruction EXCPT with 4-bit m field EXCAUS E [5:0] Type: Error (E) Service (S) Notes/Exmples m field S Instruction provides 4 bits of EXCAUSE. Single step 0x10 S When the processor is in single step mode, every instruction genertes n exception. Primrily used for debugging. Exception cused by trce buffer full condition 0x11 S The processor tkes this exception when the trce buffer overflows (only when enbled by the Trce Unit Control register). Undefined instruction 0x21 E My be used to emulte instructions tht re not defined for prticulr processor implementtion. Illegl instruction combintion Dt ccess CPLB protection violtion Dt ccess misligned ddress violtion 0x22 E See section for multi-issue rules in the ADSP-BF53x/BF56x Blckfin Processor Progrmming Reference. 0x23 E Attempted red or write to Supervisor resource, or illegl dt memory ccess. Supervisor resources re registers nd instructions tht re reserved for Supervisor use: Supervisor only registers, ll MMRs, nd Supervisor only instructions. (A simultneous, dul ccess to two MMRs using the dt ddress genertors genertes this type of exception.) In ddition, this entry is used to signl protection violtion cused by disllowed memory ccess, nd it is defined by the Memory Mngement Unit (MMU) cchebility protection lookside buffer (CPLB). 0x24 E Attempted misligned dt memory or dt cche ccess. Unrecoverble event 0x25 E For exmple, n exception generted while processing previous exception. Dt ccess CPLB miss Dt ccess multiple CPLB hits Exception cused by n emultion wtch-point mtch 0x26 E Used by the MMU to signl CPLB miss on dt ccess. 0x27 E More thn one CPLB entry mtches dt fetch ddress. 0x28 E There is wtchpoint mtch, nd one of the EMUSW bits in the Wtchpoint Instruction Address Control (WPIACTL) register is set. Blckfin Processor Troubleshooting Tips Using VisulDSP++ Tools (EE-307) Pge 9 of 11

10 Instruction fetch misligned ddress violtion Instruction fetch CPLB protection violtion Instruction fetch CPLB miss Instruction fetch multiple CPLB hits Illegl use of supervisor resource 0x2A E Attempted misligned instruction cche fetch. On misligned instruction fetch exception, the return ddress provided in RETX is the destintion ddress which is misligned, rther thn the ddress of the offending instruction. For exmple, if n indirect brnch to misligned ddress held in P0 is ttempted, the return ddress in RETX is equl to P0, rther thn to the ddress of the brnch instruction. (Note this exception cn never be generted from PC-reltive brnches, only from indirect brnches.) 0x2B E Illegl instruction fetch ccess (memory protection violtion). 0x2C E CPLB miss on n instruction fetch. 0x2D E More thn one CPLB entry mtches instruction fetch ddress. 0x2E E Attempted to use Supervisor register or instruction from User mode. Supervisor resources re registers nd instructions tht re reserved for Supervisor use: Supervisor only registers, ll MMRs, nd Supervisor only instructions. Tble 2. Hrdwre Conditions Cusing Hrdwre Error Interrupts Hrdwre Condition HWERRCAUS E(Hexdeciml) Notes / Exmples System MMR Error 0x02 An error cn occur if n invlid System MMR loction is ccessed, if 32-bit register is ccessed with 16-bit instruction, or if 16-bit register is ccessed with 32-bit instruction. Externl Memory Addressing Error 0x03 Performnce Monitor Overflow 0x12 RAISE 5 instruction 0x18 Softwre issued RAISE 5 instruction to invoke the Hrdwre Error Interrupt (IVHW). Reserved All other vlues. Blckfin Processor Troubleshooting Tips Using VisulDSP++ Tools (EE-307) Pge 10 of 11

11 References [1] ADSP-BF533 Blckfin Booting Process (EE-240). Rev 3. Jnury Anlog Devices, Inc. [2] ADSP-BF53x/ADSP-BF56x Progrmming Reference. Rev 1. My Anlog Devices, Inc. Document History Revision Rev 1 December 11, 2006 by J. Mngune Description Initil Relese. Blckfin Processor Troubleshooting Tips Using VisulDSP++ Tools (EE-307) Pge 11 of 11