VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur


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1 VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING QUESTION BANK SUBJECT CODE/NAME YEAR/ SEMESTER : EC6302/ DIGITAL ELECTRONICS : II / III UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES Minimization Techniques: Boolean postulates and laws DeMorgan s Theorem Principle of Duality  Boolean expression  Minimization of Boolean expressions Minterm Maxterm  Sum of Products (SOP) Product of Sums (POS) Karnaugh map Minimization Don t care conditions Quine McCluskey method of minimization. Logic Gates: AND, OR, NOT, NAND, NOR, Exclusive OR and Exclusive NOR Implementations of Logic Functions using gates, NAND NOR implementations Multilevel gate implementations Multi output gate implementations. TTL and CMOS Logic and their characteristics Tristate gates. PART A Q. No Questions BT Level Domain 1. State DeMorgan s theorem. 2. Express the function Y A BC in canonical POS. 3. Convert Y A BC + AB ABC into canonical form. 4. Enumerate the advantages of CMOS logic. 5. Simplify the following Boolean expression into one literal. W X ( Z YZ) X ( W WYZ ). 6. Describe the CMOS inverter circuit. 7. Define minterm and maxterm. 8. Draw an active high tristate Gate & write its truth table. 9. Illustrate Don t care terms. 10. State Distributive law. 11. What is meant by Prime Implicant and Essential prime implicants?
2 12. Find the minimized Boolean expression of this function F= X XY X Z XY Z. 13. Implement the given function using NAND gates only. F(X,Y,Z)= m (0,6). 14. Explain fanin & fanout of a standard TTL IC. 15. If A & B are Boolean variables and if A=1 & A B =0, determine B? Apply DeMorgan s theorem to simplify A BC. Design a 3 input CMOS NAND gate. 18. Determine the Boolean expression for the output of the system shown in figure. 19. Interpret the truth table of EXOR gate. 20. Simplify: ABC ABC. PART B 1. (i) Find the Minimized logic function using KMaps and Realize using NAND and NOR gate. F(A,B,C,D)= m ( 1,3,5,8,9,11,15) d(2,13). (8) (ii) Show that if all the gate in a twolevel ORAND gate network are replaced by NOR gate, the output function does not change. (5) 2. (i) Realize NOT, OR, AND gates using universal gates. (5) (ii) Write a brief note on the basic operation of TTL NAND gate. (8) 3. (i) Compare & contrast the features of TTL & CMOS logic families. (5) (ii)analyze the basic rules (laws) that are used in Boolean expressions with example. (8)
3 4. Evaluate the following Boolean expression using Boolean Algebra and draw the logic diagram. (i)t(x,y,z)= X Y) X Y Z XY X Z (. (7) (ii) XYZ XYZ XY (3) (iii) XYZ XZ YZ (3) 5. (i) Convert the following function into product of maxterms. F(A,B,C)= ( A B)( B C)( A C) (3) (ii) Using Quine McCluskey method, examine the given function. F(A,B,C,D)= m (1,2,3,7,8,9,1011,14,15). (10) 6. (i) Using Kmap method, Simplify the following Boolean function F= m(0,2,3,6,7) + d(8,10,11,15) and obtain (8) (a) minimal SOP and (b) minimal POS expression & realize using only NAND and NOR gates. (ii) Explain Tristate TTL inverter circuit diagram and its operation. (5) 7. (i)draw the multilevel two input NAND circuit for the following expression: F ( AB CD) E BC ( A B) (3) (ii) How would you express the Boolean function using Kmap and draw the logic diagram F(w,x,y,z)= m (0,1,2,4,5,6,8,9,12,13,14). (10) 8. (i) Simplify the following function using K map, F=ABCD+AB C D +AB C+AB & realize the SOP using only NAND gates and POS using only NOR gates. (8) (ii) Simplify the logic circuit shown in figure (5) 9. Explain the minimization of the given Boolean function using QuineMcCluskey method F= m (0,1,2,5,7,8,9,10,13,15).Realize the simplified function using logic gates. (13)
4 10. (i) Explain the implement of the following function using NAND and inverter gates F=AB+A B +B C. (5) (ii) Using Kmap method, simplify the given Boolean function and obtain minimum POS expression. X= m ( 1,3,5,7,9) d(8,11,15). (8) 11. (i) Given Y(A,B,C,D)= M (0,1,3,5,6,7,10,14,15), Draw the KMap and Obtain the simplified expression. Design the minimum expression using basic gates. (8) (ii) Construct the expression Y(A,B,C)= M (0,2,4,5,6 ) using only NORNOR logic. (5) 12. Develop the following Function using Tabulation method Y(A,B,C,D)= m(0,1,2,5,6,7,8,9,10,14) and implement using only NAND gates. (13) 13. Interpret the given Boolean function F(A,B,C,D)= m(0,1,2,5,8,9,10) into (i) Sum of products form (5) (ii) Product of sum form and implement it using basic gates. (8) 14. (i) Develop the given function using Kmap and obtain the simplified expression. Y= m (3,6,7,8,10,12,14,17,19,20,21,24,25,27,28). (7) (ii) Solve by perfect induction (6) (a) A+AB = A (b) A(A+B) = A (c) A+A B = A+B and (d) A(A +B) =AB PART C 1. Design the given function using Quine McCluskey method and Verify your result using Kmap. F= m (0,1,2,4,5,6,8,9,12,13,14) (15) 2. (i) Develop the given function Y (M,N,O,P,Q) = m (0,2,4,6,9,13,21,23,25,29,31). Draw the Kmap and Implement the simplified expression using basic gates. (8) (ii) Estimate the schematic and explain the operation of a CMOS inverter.also explain its characteristics. (7)
5 UNIT II COMBINATIONAL CIRCUITS Design procedure Half adder Full Adder Half subtractor Full subtractor Parallel binary adder, parallel binary Subtractor Fast Adder  Carry Look Ahead adder Serial Adder/Subtractor  BCD adder Binary Multiplier Binary Divider  Multiplexer/ Demultiplexer decoder  encoder parity checker parity generators code converters  Magnitude Comparator. Q.No Questions PART A BT Level Domain 1. Define Half adder and Full adder. 2. What is Priority Encoder? 3. Draw the two bit comparator circuit using logic gates. 4. Distinguish between demultiplexer and decoder 5. Construct 4bit parallel adder/subtractor using Full adders and EXOR gates. 6. Convert a twotofour line decoder with enable input to 1:4 demultiplexer. 7. Relate carry generate, carry propagate, sum and carryout of a carry look ahead adder. 8. Give examples for combinational circuit (any four). 9. Sketch the Half adder circuit using NAND gates. 10. Illustrate the logic diagram of 4:1 multiplexer. 11. Evaluate the logic circuit of a 2 bit comparator. 12. Design a Half subtractor using basic gates. 13. State the function of select inputs of a MUX. 14. Develop the following function using suitable multiplexer F= Σm(0,2,5,7). 15. How would you design the logic diagram of a 2 bit multiplier? 16. Draw the logic diagram of a serial adder.
6 17. Explain a 3 bit even parity generator. 18. Describe code converter? List their types. 19. Examine a single bit magnitude comparator to compare two words A and B. 20. Convert gray code into its binary equivalent. PART B 1. Analyze the function of Binary multiplier with neat diagram using (i) Shift method. (6) (ii) Parallel multiplier. (7) 2. (i) Design a 4bit decimal adder using 4bit binary adders. (7) (ii) Simplify the function using multiplexer F= ( 0,1,3,4,8,9,15). (6) 3. (i) Construct full subtractor using Demultiplexer. (6) (ii) Write short note on BCD adder. (7) 4. (i) Analyze the design of a 8 x 1 multiplexer using only 2 x 1 multiplexer. (6) (ii) Formulate the following Boolean function using 4 x 1 multiplexers. F ( A, B, C, D) (1,2,3,6,7,8,11,12,14). (7) 5. (i) Draw the logic diagram of a 2bit by 2bit binary multiplier and explain it s operation. (6) (ii) Realize F(w, x, y, z)= Σ (1,4,6,7,8,9,10,11,15) using 8 to 1 Multiplexer. (7) 6. (i) Realize a circuit to carryout both addition and subtraction. (6) (ii) Interpret a seven segment decoder circuit to display the numbers from 0 to 3. (7) 7. How would you design (i) Full adder using demultiplexer. (7) (ii) Serial binary adder. (6) 8. Illustrate BCD to excess 3 code converter using minimum number of NAND gates. (13)
7 9. (i) Explain the working and draw the logic diagram of Binary to Octal decoder. (6) (ii) How would you design BCD to Gray code converter. Use don t care. (7) 10. (i) Demonstrate 4bit magnitude comparator with three outputs: A>B, A=B and A<B. (7) (ii) Build a 4bit even parity generator circuit using gates. (6) 11. (i) Give a combinational circuit that converts 4 bit Gray Code to a 4 bit binary number. Implement the circuit. (8) (ii) Develop a Full adder using decoder. (5) 12. (i) How would you design a 3:8 decoder using basic gates? (7) (ii) How would you design a binary to gray code convertor? (6) 13. (i) Examine the design of a full adder using two half adders and an OR gate. (6) (ii) Analyze the design of excess 3 to BCD code converter using minimum number of NAND gates (7) 14. (7) (i) Estimate the logic diagram of BCDDecimal decoder and explain its operations. (8) (ii) Deduce the design of a 1:4 demultiplexer circuit. (5) PART C 1. Conclude that the carry look ahead adder is faster than a ripple carry Adder by using necessary equations. (15) 2. Create the design of a BCD to seven segment decoder with neat diagrams. (15)
8 UNIT III SEQUENTIAL CIRCUITS Latches, Flipflops  SR, JK, D, T, and MasterSlave Characteristic table and equation Application table Edge triggering Level Triggering Realization of one flip flop using other flip flops serial adder/subtractor Asynchronous Ripple or serial counter Asynchronous Up/Down counter  Synchronous counters Synchronous Up/Down counters Programmable counters Design of Synchronous counters: state diagram State table State minimization State assignment  Excitation table and mapscircuit implementation  Modulo n counter, Registers shift registers  Universal shift registers Shift register counters Ring counter Shift counters  Sequence generators. PART A Q. No Questions BT Domain Level 1. Show the state diagram of MOD 10 counters. 2. Define the terms: state table and state assignment. 3. Summarize the design of 3 bit ring counter and find the mod of designed counter. 4. State setup and hold time. 5. Summarize the race around condition. How do you eliminate it? 6. Analyze the differences between latch and flip flop. 7. Build a T Flipflop from a D Flipflop. 8. Illustrate the logic diagram of a clocked SR flip flop. 9. State the difference between Mealy and Moore state machines. 10. Compare the logics of synchronous counter and ripple counter. 11. Point out the condition on JK FF to work as D FF. 12. Model a NAND based logic diagram of Master Slave JK FF. 13. Build the state diagram and characteristics equation of a D FF. 14. Find minimum number of flipflops needed to design a counter of Modulus Generalize how does JK flip flop differs from SR Flip flop. 16. What is meant by programmable counter? Mention its applications.
9 17. Point out two differences between edge triggering and level triggering. 18. Distinguish and compare the asynchronous and synchronous logic. 19. How many flipflops are required to build a binary counter that counts from 0 to 1023? 20. List out the classifications of sequential circuits PART B 1. How would you design the Sequential circuit has three flip flops A, B, and C; one input X_in ; and one output Y_out. The state diagram is shown in below figure. The circuit is to be designed by treating the unused states as don t care conditions. Analyze the circuit obtain from the design to determine the effect of the unused states. Use T flip flops in the design. (13) 2. (i) Compare the diagram of a 4bit SISO SIPO, PIPO and PISO shift register and draw its waveforms. (8) (ii) Realize D flipflop using SR flipflop. (5) 3. (i) Construct and explain the working of an 4bit Up/Down ripple counter (7) (ii) Model a synchronous MOD5 counter and explain with waveforms. (6) BTL5
10 4. (i) Analyze the number of states reduction in the following state table, and tabulate the reduced state table. (7) Present Next State Output state X = 0 X =1 X =0 X=1 a f B 0 0 b d C 0 0 c f E 0 0 d g A 1 0 e d C 0 0 f f B 1 1 g g H 0 1 h g A 1 0 (ii) Examine a BCD ripple counter with timing diagram. (6) 5. Analyze state reduction if possible after designing a clocked synchronous sequential logic circuit using JK flip flops for the following state diagram. Use state reduction if possible. (13) 6. (i) Show the operation of universal shift register with neat block diagram. (7) (ii) Estimate the design a counter to count the sequence 0, 1, 2, 4, 5, 6,...using SR FF s. (6)
11 7. (i) Interpret design of a 3 bit synchronous counter using JK flipflop. (10) (ii) Differentiate between a state table, characteristic table and an excitation table. (3) 8. Explain the following design of (i) A synchronous counter with states 0, 1, 2, 3, 0, 1,... using JK flip flop. (7) (ii) A JK FF using a D FF, a 2:1 Multiplexer and an inverter. (6) 9. (i) Use T flipflop to design counter with the following repeated binary sequence 0, 4, 7, 2, 3. (8) (ii) Realize JK Flip Flop using SR Flip Flop (5) 10. (i) Illustrate with diagram an asynchronous decade counter & its operation with neat waveforms. (7) (ii) Predict the design of a synchronous 3bit counter which counts in the sequence 1, 3, 2, 6, 7, 5, 4, (repeat ) 1, 3... using T FF. (6) 11. Create the design of a clocked sequential machine using JK Flip Flops for the state diagram shown in figure. Use state reduction if possible and make proper state assignment. (13)
12 12. (i) Paraphrase the operation of master/slave Flip Flop and show how the race around condition is eliminated? (7) (ii) Deduce a clocked synchronous sequential machine using T flip flops for the following state diagram. Use state reduction if possible.also use straight binary state assignment. (6) 13. (i) Using D flipflop, Design a synchronous counter which counts in the sequence 000,001,010,011,100,101,110,111,000. (10) (ii) Discuss the working of 4 bit Johnson counter with neat diagram. (3) 14. (i) Point out a sequence detector design which detects the sequence using D flip flop. (7) (ii) Enumerate about Triggering of FlipFlop. (6) PART C 1. Design a sequence detector which detects the sequence using D flip flop? (15) 2. Explain the functions with the state diagram and characteristics equation of T FF, D FF and JK FF and compare and contrast among the FFs? (15)
13 UNIT IV MEMORY DEVICES Classification of memories ROM  ROM organization  PROM EPROM EEPROM EAPROM, RAM RAM organization Write operation Read operation Memory cycle  Timing wave forms Memory decoding memory expansion Static RAM Cell Bipolar RAM cell MOSFET RAM cell Dynamic RAM cell Programmable Logic Devices Programmable Logic Array (PLA)  Programmable Array Logic (PAL) Field Programmable Gate Arrays (FPGA)  Implementation of combinational logic circuits using ROM, PLA, PAL. PART A Q. No Questions BT Level Domain 1. Compare and contrast static RAM and dynamic RAM. 2. Describe briefly memory decoding. 3. Point out the advantages of RAM. 4. How read and write operations are done. 5. Distinguish between volatile and nonvolatile memory. 6. Define memory expansion and Mention its limit. 7. Show the implementation of Y= AB A. 8. List out the advantages of PLDs. 9. Classify the different types of programmable logic device. 10. State access time and cycle time of a memory. 11. Classify the memories. 12. What is programmable logic array? How it differs from ROM? 13. Implement the function F1= (0, 1, 2, 5, 7) and F2 = (1, 2, 4, 6) using PROM. 14. Enumerate about EPROM. 15. Generalize the implementation of 2bit multiplier using ROM. 16. Formulate the implementation of Ex OR function using PROM. 17. Explain the advantages of EEPROM over EPROM. 18. Describe various features of PROM, PAL and PLA. 19. Differentiate between PAL and PLA. 20. How the bipolar RAM cell is different from MOSFET RAM cell?
14 PART B 1. (i) Describe read cycle and write cycle timing parameter with the help of timing diagram. (7) (ii) Construct a combinational circuit is defined as the function F1 = AB C +AB C+ABC and F2 = A BC+AB C+ABC. Implement the digital circuit with a PLA having 3 inputs, 3 product terms and 2 outputs. (6) 2. (i) Classify the types of PLDs and write notes on PLDs (7) (ii) Implement the following Boolean function using PLA, F1(x, y, z) = (0, 1, 3, 5) and F2(x, y, z) = (3, 5, 7). (6) 3. (i) Demonstrate the realization of the following function using PAL F1(x, y, z) = (1, 2, 4, 5, 7). And F2(x, y, z) = (0,1,3,5,7). (7) (ii) Write a note on FPGA with neat diagram. (6) accepts a three bit number and outputs a binary number equal to 4. (i) Paraphrase the various features of RAM organization. (7) (ii) Analyze a combinational circuit using ROM. The circuit the square of the input number. (6) 5. Create the design of BCD to Excess 3 using PLA? (13) 6. (i) Demonstrate the classification of semiconductor memories (7) (ii) Manipulate the following function using PLA F1= (2, 4, 5, 10, 12, 13, 14) and F2 = (2, 9, 10, 11, 13, 14, 15). (6) 7. (i) Discuss the basic concepts and the principle of operation of Bipolar SRAM cell. (7) How can one make 64 8 ROM using 32 4 ROMs? Draw such a circuit & explain. (6) 8. How can you create the design of 32 8 ROM and give an explanation about it? (13) 9. (i) Describe the implementation of Binary to Gray code converter using PROM devices. (7) (ii) Realize the following function using PLA F (w, x, y, z) = Π (0, 3, 5, 7, 12, 15) + d (2, 9). (6) 10. (i) Explain the implementation of function F1 = A B +AC and F2= (AC +AB +BC) with a PLA circuit. (7) (ii) Write short notes on EPROM and EEPROM. (6) 11. (i) Compare types of ROMs and explain a short note on RAM, (8) (ii) Implement the following function using PLA F1= (0, 1, 2, 4) and F2 = (0, 5, 6, 7). (5)
15 12. Recognize the implementation of the following Boolean functions 13. using PAL. (13) i. W(A,B,C,D)= (0,2, 6,7,8,9,12,13) ii. X(A,B,C,D)= (0, 2, 6, 7, 8, 9, 12, 13, 14) iii. Y(A, B, C, D) = ( 2, 3, 8, 9, 10, 12, 13) iv. Z(A,B,C,D)= (1, 3, 4, 6, 9, 12, 14) (i) Examine the structure of PLA and PAL. (7) (ii) Quote how a combinational logic function is implemented in PAL and PLA. Explain with example. (6) 14. (i) Explain EAPROM and static RAM cell using MOSFET? (5) (ii) Recognize 512 X 8 ROM using eight 64x8 ROM chips with an enable input and a decoder? (8) PART C 1. Design a combinational circuit using a ROM. The circuit accepts a three bit number and outputs a binary number equal to the square of the input number. (15) 2. (i) Interpret how does Programmable logic devices differ from FPGA? (8) (ii) Formulate the implementation of the following functions with PLA having three inputs, four product terms, and two outputs. (7). F1 (A, B, C) = (3, 5, 6, 7) F2 (A, B, C) = (0, 2, 4, 7)
16 UNIT V SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS Synchronous Sequential Circuits: General Model Classification Design Use of Algorithmic State Machine Analysis of Synchronous Sequential Circuits. Asynchronous Sequential Circuits: Design of fundamental mode and pulse mode circuits Incompletely specified State Machines Problems in Asynchronous Circuits Design of Hazard Free Switching circuits. Design of Combinational and Sequential circuits using VERILOG. PART A Q. No Questions BT Level Domain 1. State flow table and primitive flow table. 2. Classify Asynchronous sequential circuits. 3. Inspect the Concept of Merger graphs. 4. Build a Verilog HDL model for half subtractor circuit. 5. Show the basic building blocks of an Algorithmic State Machine chart. 6. Distinguish between stable and unstable state. 7. Write a Verilog behavioral model of a Transparent flip flop with reset input. 8. Define the terms race and critical race. 9. Apply gate level model to write a Verilog code for 4to2 Encoder. 10. What are Hazards? How it can be avoided? 11. Compare the ASM chart with a conventional flow chart. 12. Compile fundamental mode and pulse mode asynchronous sequential circuits. 13. List out the causes of essential Hazard. 14. Construct a Verilog model of a half adder circuit. 15. Explain the analysis procedure of synchronous sequential circuits. 16. Name the problems that arise in asynchronous circuits. 17. Model a D flip flop using Verilog List the types of Hazards that exist in asynchronous sequential circuits. Interpret critical race and give the methods for criticalrace free state assignment.
17 20. What is most important consideration in making state assignment for asynchronous network? PART B 1. Design an asynchronous sequential circuit with 2 inputs T and C. The output attains a value of 1 when T=1 and C moves from 1 to 0. Otherwise the output is 0. (13) 2. (i) What are the types of hazards? Check whether the following circuit contains a hazard or not Y = x1x2 + x2 x3.if the hazard is present, demonstrate its removal. (8) (ii) Describe Moore and Mealy machines with block diagram (5) Derive the transition table, state table and state diagram for Moore sequential circuit shown in below figure. (13) (i) What is a Hazard? Give hazard free realization for the following Boolean function. F(A, B, C, D) = m(0, 2, 6, 7, 8, 10, 12). (8) (ii) Find the ASM chart for binary multiplier. (5) 5. Summarize the various problems arises in an asynchronous sequential circuits. Explain any two problems in detail. (13) 6. Construct the state table and state diagram of the sequential circuit shown in below figure. Explain the function that the circuit performs. (13)
18 7. (i) Demonstrate a sequential pattern detector that receives a stream of input bits. The circuit should recognize the pattern 010 and produce an output whenever this pattern is received. (10) (ii) When is a sequential machine set to be strongly connected? (3) Analyze the given synchronous sequential circuit shown in below figure. (13) (i) Evaluate and test Full adder and JK Flipflop with Verilog code. (7) (ii) Explain the different types of Hazards. Design Hazard free circuits for Y=X1X2+X2 Y. (6) Using Verilog model for the given logic (i) 3:8 decoder. (7) (ii) 2 bit Up/Down synchronous counter. (6) (i) Build a full adder using Two Half adders by writing Verilog program. (8) (ii) Write explanatory notes on algorithmic state machines. (5) 12. (i) For the state diagram shown in below figure, model a synchronous
19 sequential circuit using JK flip flops. (10) (ii) What is ASM? Give the basic notations. (3) Classify the methods of Race Free State assignment and explain in detail. (13) (i) What are static and dynamic hazards? Give static 0 hazard free realizations for the following Boolean function. F(A, B, C, D) = ΠM(3, 4, 5, 7, 9, 13, 14, 15). (10) (ii) Write the design procedure for Asynchronous sequential logic circuits. (3) PART C Propose a design of T flip flop using logic gates. Derive the state table, state diagram, primitive flow table, transition table and Merger graph. Draw the logic circuit. (15) Deduce the transition table, state table and state diagram for the moore sequential circuit given below. (15) 2.
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