ECE261 CMOS VLSI Design Final Project Report. Duke University. December 3, Copyright reserved. Page 1 of 30

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1 Duke University Digital Clock ECE 261 Final Project Report Fangming Ye Bhawana Singh December 3, 2009 Copyright reserved Page 1 of 30

2 Table of content 1 Introduction Project Function Performance Estimation System Power Consumption Sub- circuit Design D-flipflop JK-flipflop JK-flipflop with reset function counter counter counter with reset function segment decoder Full system design Logic implementation Layout Simulation References Page 2 of 30

3 List of Figures Figure 1-1 system block diagram... 5 Figure 1-2 System Layout Floor Plan... 6 Figure 2-1 schematic of D-flipflop... 8 Figure 2-2 layout of D-flipflop... 8 Figure 2-3 ELDO simulation of D-flipflop... 9 Figure 2-4 schematic of JK-flipflop Figure 2-5 layout of JK-flipflop Figure 2-6 ELDO simulation of JK-flipflop Figure 2-7 schematic of JK-flipflop with reset function Figure 2-8 layout of JK-flipflop with reset function Figure 2-9 ELDO simulation of JK-flipflop with reset function Figure 2-10 schematic of 0-5 counter Figure 2-11 layout of 0-5 counter Figure 2-12 ELDO simulation of 0-5 counter Figure 2-13 schematic of 0-9 counter Figure 2-14 layout of 0-9 counter Figure 2-15 ELDO simulation of 0-9 counter Figure 2-16 schematic of 0-9 counter with reset function Figure 2-17 layout of 0-9 counter with reset function Figure 2-18 ELDO simulation of 0-9 counter with reset function Figure 2-19numerical designation and display Figure segment identification Figure 2-21 schematic of 4-7 segment decoder Figure 2-22 layout of 4-7 segment decoder Figure 2-23 ModelSIM simulation of 4-7 segment decoder Figure 3-1 flow chart of full system Figure 3-2 top view schematic Figure 3-3 top view layout Figure 3-4 topview layout DRC clean Figure 3-5 topview layout LVS clean Figure 3-6 top view simulation (part I) Figure 3-7 top view simulation (part II) Figure 3-8 top view simulation (part III) Page 3 of 30

4 1 Introduction 1.1 Project Function In this project, we have built a digital clock with 12 hour count time. The clock runs from 00:00 to 11:59 and then back to 00:00. Our display has four digits, two digits for minutes and two for hour. The specialty of this clock is that it has very low power consumption and condensed layout. We have used a simple 0-9 counter for the unit s digit of minutes display and a 0-5 counter for the ten s digit of minute. For the unit s digit of hour, a resettable 0-9 counter has been used, and for the ten s digit of hour a resettable JK-flipflop has been used. Other than this, a few NAND gates and D-flipflops have been used to ensure proper functioning of the clock. There is only one input for the entire system: the clock input into the 0-9 counter used for the unit s digit of minute. The clock inputs for the other blocks are derived from the output of the previous blocks as shown in the block diagram for the system. We have a total of 12 outputs: 4 outputs for unit s digit of minute, 3 outputs for ten s digit of minute, 4 outputs for unit s digit of hour and 1 output for the ten s digit of hour. Besides, we have also designed a 4-7 segment decoder which can be used for the actual display of digits as we see on a real digital clock. We have kept the decoder separate from the top view of the schematic because it makes it difficult to view the output in binary form using the 4-7 segment display. However, if we do the actual hardware implementation, then we can use 4 such decoders, and connect the outputs of each of the four blocks (0-9 counter, 0-5 counter, resettable 0-9 counter and resettable JK-flipflop) to the inputs of the respective decoder and display time. The outputs of the decoders would be connected to LEDs and would make the LED glow for a high output and vice-versa for a low output. Every 10 minutes, we add one on the ten s digit of minute. After every 6 such cycles, we add one on the unit s digit of hour, and every 10 hours, we add one on tens digit of hour. As soon as it reaches 1 on the ten s digit of hour and 2 on unit s digit of hour, both the ten s and the unit s digit of hour are reset to 0. So, in practice, we do not see 12:00 displayed. We rather see a transition from 11:59 to 00:00. The block diagram of the system is shown in Figure 1-1 and the layout floor plan has been shown in Figure 1-2. Page 4 of 30

5 Figure 1-1 system block diagram Page 5 of 30

6 Figure 1-2 System Layout Floor Plan 1.2 Performance Estimation An estimate of the total number of transistors used in our sub-blocks and the whole system is shown in Table 1. Blocks in Top view No. of transistors in sub-block No. of sub-block needed in top-view Area of sub-block (µm 2 ) Inverter NAND D flipflop Resettable JK flipflop Counter Counter Resettable 0-9 Counter Decoder Table 1: Summary of transistor number and area Page 6 of 30

7 From this, we have calculated the total number of transistors and total area as- Total number of transistors: 1238 Total area: µm System Power Consumption Dynamic power consumption Frequency used for simulation: 1Hz Power consumption at 1Hz frequency: nw Actual clock frequency required: 1/60 Hz Scaled Power Consumption at 1/60 Hz: nw Static power consumption Usually static power consumption is one tenth of dynamic power consumption, Thus, Static power consumption: 0.02nW 2 Sub- circuit Design 2.1 D-flipflop We use D-flipflops in the main digital block connection, in order to create a delay to match the time flow. While D-flipflop is a common block in design, we briefly introduce the function of D-flipflop. The Q output always takes on the state of the D input at the moment of a rising clock edge (or falling edge if the clock input is active low). It is called the D flip-flop for this reason, since the output takes the value of the D input or Data input, and Delays it by one clock count. The D flip-flop can be interpreted as a primitive memory cell, zero-order hold, or delay line. Whenever the clock pulses, the value of Q next is D and Q prev otherwise. Clock D Q Q prev Rising edge 0 0 X Rising edge 1 1 X Non-Rising X Q prev Table 2 D-flipflop truth table The schematic and layout of D-flipflop are shown in Figure 2-1 schematic of D-flipflop and Figure 2-2, in this design, we used 5 inverters and 4 transmission gates. The ELDO analog simulation result can be seen in Figure 2-3. Page 7 of 30

8 Figure 2-1 schematic of D-flipflop[1] Figure 2-2 layout of D-flipflop Page 8 of 30

9 ECE261 CMOS VLSI Design Final Project Report Figure 2-3 ELDO simulation of D-flipflop 2.2 The schematicc and layout of JK-flipflop are shown in Figure 2-4 and Figure 2-5,, in this design, we used 1 inverter, 6 NAND2 gates and 2NAND3 gates. The ELDO analog simulation result can be seen in Figure 2-6. <Reference used for schematic was /digital/jk_nand_flip-flop. html> JK-flipflop In our design, JK-flipflop and JK-flipflop with reset function are the most importantt basic blocks used to create counters. We briefly introduce the implementation of JK-flipflop, and JK-flipflop with reset function in the next section. The JK flip-flopp augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the S = R = 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical complement of its current value. The flip-flop is negative-edge triggered (falling clock pulse) as seen in the timing diagram. The expression of JK-flipflop is shown below, Page 9 of 30

10 Figure 2-4 schematic of JK-flipflop Figure 2-5 layout of JK-flipflop Page 10 of 30

11 2.3 JK-flipflop with reset function Figure 2-6 ELDO simulation of JK-flipflop In the design of HOUR part of our digital clock, we use JK-flipflop with reset function, to reset the output to 0 when the time reaches 12, while we just use JK-flipflop without reset function in MINUTE part. The basic function of JK-flipflop with reset function is the same as JK-flipflop, except we add the clear function. But in order to implement this function, we designed another schematic. Reset input is independent from J and K and clock, so this is an asynchronous reset JK-flipflop. This JK-flipflop is substantially based on a D-flipflop, and in the input stage, we change the input for reset function. The schematic and layout of JK-flipflop with reset function are shown in Figure 2-4 and Figure 2-5, in this design, we used 7 inverter, 5 NAND2 gates and 4 transmission gates. After all, the ELDO analog simulation result can be seen in Figure 2-6. Page 11 of 30

12 Figure 2-7 schematic of JK-flipflop with reset function Figure 2-8 layout of JK-flipflop with reset function Page 12 of 30

13 counter Figure 2-9 ELDO simulation of JK-flipflop with reset function Here, a 0-5 counter acts as a digital output for ten s digit of minute. The basic idea of implementation of 0-5 counter is based on JK-flipflop to ripple the digits. Digits start from 000, when they reach 101(5 in decimal) and then return to 000. The truth table of 0-5 counter is shown below OUTPUT C B A COUNT The schematic and layout of 0-5 counter are shown in Figure 2-10and Figure 2-11, in this design, we used 3 JK flipflops, 3 inverters, and 3 NAND2 gates. In layout, in order to fit the floor plan, we designed it not in a rectangular shape. Page 13 of 30

14 Figure 2-10 schematic of 0-5 counter Figure 2-11 layout of 0-5 counter The ELDO analog simulation result can be seen in Figure We can see that the counter starts from 000 to 101 and returns to 000. Page 14 of 30

15 counter Figure 2-12 ELDO simulation of 0-5 counter 0-9 counter is a larger version of 0-5 counter. Here, 0-9 counter acts as a digital output for units of minute. The basic idea of implementation of 0-9 counter is also based on JKflipflop to ripple the digits. Digits start from 0000, when they reach 1001(9 in decimal) and then return to The truth table of 0-9 counter is shown below < Reference used for schematic was OUTPUT COUNT D C B A Page 15 of 30

16 Table counter truth table The schematic and layout of 0-9counter are shown in Figure 2-13and Figure 2-14, in this design, we used 4 JK flipflops, 1 inverter, 3 NAND2 gates and 1 NAN3 gate. Figure 2-13 schematic of 0-9 counter Page 16 of 30

17 Figure 2-14 layout of 0-9 counter ELDO analog simulation result can be seen in Figure We can see that the counter starts from 0000 to 1001 and returns to Page 17 of 30

18 counter with reset function Figure 2-15 ELDO simulation of 0-9 counter Implementation of 0-9 counter is also based on JK-flipflop with reset function to ripple the digits. Digits start from 0000, when they reach 1001(9 in decimal) and then return to 0000 normal. But it will be reset when input a reset signal, which is usually in the second round of counting and reset at The truth table of 0-9 counter with reset function is the same as the truth table of 0-9 counter. Here is a concern that the reset function is asynchrony, so we design the reset signal at the edge of 11-12, thus there is a transient spike during the process. But the delay time of this spike is in the order of nanosecond level, and this signal is trigger in HOUR level. So we can neglect this spike in the operation of our project. The schematic and layout of 0-9counter with reset function are shown in Figure 2-16Error! Reference source not found.figure 2-4 and Figure In this design, we used 4 JKflipflops with reset function, 1 inverter, 3 NAND2 gates and 1 NAN3 gate. Page 18 of 30

19 Figure 2-16 schematic of 0-9 counter with reset function Figure 2-17 layout of 0-9 counter with reset function ELDO analog simulation result can be seen in Figure We can see that the counter starts from 0000 to 1001 and returns to We gave a reset signal during the operation, all digits are set to 0 immediately. Page 19 of 30

20 Figure 2-18 ELDO simulation of 0-9 counter with reset function segment decoder Here, a 4-7 segment decoder is used for output binary digits of MUNITEs and HOURs in LEDs display. Normally, LEDs display has the function as follows, and we usually use the previous 10 output from 0 to 9. Figure 2-19numerical designation and display Figure segment identification To implement this function, we generate the truth table for a 4-7 segment decoder as below and get its corresponding 7 segment output and annotate them in decimal. Page 20 of 30

21 DECIMAL OR FUNCTION INPUTS OUTPUTS D C B A ~BI a b c d e f g 0 L L L L H 0 H H H H H H L 63 1 L L L H H 1 L H H L L L L 6 2 L L H L H 2 H H L H H H H 91 3 L L H H H 3 H H H H L L H 79 4 L H L L H 4 L H H L L H H L H L H H 5 H L H L H H H L H H L H 6 L L H H H H H L H H H H 7 H H H L L L L 7 8 H L L L H 8 H H H H H H H H L L H H 9 H H H L L H H H L H L H 10 L L L H H L H H L H H H 11 L L H H L L H H H L L H 12 L H L L L H H H H L H H 13 H L L H L H H H H H L H 14 L L L H H H H H H H H H 15 L L L L L L L 0 BI X X X X L X L L L L L L L 0 Table segment decoder truth table The schematic and layout of a 4-7 segment decoder are shown in Figure 2-20Error! Reference source not found.figure 2-4 and Figure In this design, we used 12 inverters, 14 NAND2 gates, 13 NAN3 gates and 1 NAND4 gate. Page 21 of 30

22 Figure 2-21 schematic of 4-7 segment decoder Figure 2-22 layout of 4-7 segment decoder ModelSIM digital simulation result can be seen in Figure We can see that the different input from 0000 to 1111 correspond to different output according to the truth table in Table 1, thus verifying our design. Page 22 of 30

23 Figure 2-23 ModelSIM simulation of 4-7 segment decoder 3 Full system design 3.1 Logic implementation The input to the system is the clock input into the 0-9 counter used for the unit s digit of minute. Every 10 minutes, one is added to the ten s digit of minute. After every 6 such cycles, i.e. every 60 minutes, one is added to the unit s digit of hour, and every 10 hours, one is added to the ten s digit of hour. As soon as it reaches 1 on the ten s digit of hour and 2 on unit s digit of hour, both the ten s and the unit s digit of hour are reset to 0. The flowchart for this is shown below. Page 23 of 30

24 Figure 3-1 flow chart of full system We implemented the function shown in Figure 3-1, and include all the sub-blocks we set up before, draw the top view schematic as below, and then top view layout Figure 3-3. Page 24 of 30

25 Figure 3-2 top view schematic Page 25 of 30

26 3.2 Layout Here is our DRC and LVS check result Figure 3-3 top view layout Page 26 of 30

27 Figure 3-4 topview layout DRC clean 3.3 Simulation Figure 3-5 topview layout LVS clean In the top view simulation, we can simultaneously look at all the 12 outputs. These have been shown in the three following figures. In the first figure, we can see all the four bits of Page 27 of 30

28 the unit digit of minute, and two of the three bits of ten s digit of minute. If we look at MU1, MU2, MU3 and MU4, counting starts from 0, goes up till 9, and then again goes back to 0 and so on. At every transition from 9 to 0, a clock pulse is sent to the ten s digit of minute, i.e., to the 0-5 counter. So, as soon as MU4 transitions from high to low, we can see a transition in MT1 as well. MT1, MT2 and MT3 form the three bits of the ten s digit of minute. These start counting from 0, go up till 5, and then again go back to zero. This counting from o to 5 and back to zero can be clearly seen in the second figure. Figure 3-6 top view simulation (part I) In this figure, we can clearly see the ten s digit of minute and the transition on the unit digit of hour after sixty minutes elapse. As long as both MT3 and MT1 are high, the time that is displayed on the minute part of the clock varies from 50 to 59. After this, all the bits in the minute display become zero, and a clock pulse is sent to the 0-9 counter which is used for the unit digit of hour. So, every time MT3 transitions from high to low, there is a transition in HU1. Page 28 of 30

29 Figure 3-7 top view simulation (part II) In this figure, we can see the both the unit and the ten s digit of hour. HU1, HU2, HU3 and HU4 together make up the unit digit of hour, and HT1 is for the ten s digit. HU1, HU2, HU3 and HU4 count from 0 to 9 and then go back to 0 again. As soon as the transition from 9 to 0 takes place, a clock pulse is sent to the resettable JK-flipflop used for the ten s digit display of hour. This stays high for one complete clock period on HU1, and then all the bits in HOUR display become zero (except for a spike in HU2 which is too short to be noticed in practice). A high pulse on HT1 and a simultaneous low and then high on HU1, while HU2 and HU3 stay low, implies display 10 and 11 on the hour digits. After 11, the hour display shows 00 since all of the bits, HU1, HU2, HU3 and HU4 become 0. For as long as there is a zero on HU1 or a 1 on HU1, the minutes digit would count from 00 to 59. Thus, overall the clock would display from00:00 to 11:59 and back to 00:00. Page 29 of 30

30 Figure 3-8 top view simulation (part III) 4 References [1] N. H. E. Weste and D. Harris, CMOS VLSI design : a circuits and systems perspective: Boston : Pearson/Addison-Wesley, c2005. [2] TI, system on chip: sn74ls47, BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS,1998 [3] ST, system on chip: M74HC107, DUAL J-K FLIP FLOP WITH CLEAR,2000 Page 30 of 30