Switching Circuits & Logic Design

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1 Switching ircuits & Logic esign Jie-Hong Roland Jiang 江介宏 epartment of Electrical Engineering National Taiwan University Fall 23 2 Registers and ounters rawing Hands M.. Escher,

2 Outline Registers and register transfers Shift registers esign of binary counters ounters for other sequences ounter design using S-R and J-K flipflops erivation of flip-flop input equations 3 Registers and Register Transfers Several flip-flops may be grouped together with a common clock to form a register 4

3 Registers and Register Transfers 4-Bit Flip-Flop Register Using gated clock data out lr 3 lr 2 lr lr Symbol 3 lrn Load lk With clock enable 2 data in lrn lr E 4 4 Load lrn lk 3 2 lr lr lr lr E 3 E 2 E E Load lk 5 Registers and Register Transfers ata Transfer between Registers A Tri-state bus En Register A FF Register A = FFs A and A 2 Register B = FFs B and B 2 Register = FFs and 2 If En= and Load=, =A If En= and Load=, =B Register B A 2 FF B FF B 2 FF lk Load FF E 2 FF E 2 Register 6

4 Registers and Register Transfers 8-Bit Register with Tri-State Output En En lock K ifferent from clock enable 7 Registers and Register Transfers ata Transfer Using a Tri-State Bus Bus Register G E Register H E LdG 8 lock LdH 8 lock EnA Register EnB Register En Register En A B Register If EF=, A is stored in G (or H) If EF=, B is stored in G (or H) If EF=, is stored in G (or H) If EF=, is stored in G (or H) E F ecoder 8

5 Registers and Register Transfers Parallel Adder with Accumulator Accumulator: A register of FFs that can store one number and add a second number to it, leaving the result stored in it x n x i x 2 x ' ' ' ' Accumulator Register E E E E Ad LK lrn s n x n s i x i s 2 x 2 s x c n+ Full Adder c n c i+ Full Adder c i c 3 Full Adder c 2 Full Adder c = yn yi y2 y 9 Registers and Register Transfers Parallel Adder with Accumulator (cont d) Implementation of adder cells (module-based design) E.g., using Verilog Adder cell without MU Adder cell with MU x i x i ' E K E Ad Ad LK Ld lrn s i x i s i Full Adder c i+ FA c i c i+ c i y i y i Need to clear before loading to Y No need to clear before loading

6 Shift Registers A shift register is a register where binary data can be stored and shifted to the left/right when a shift signal is applied Right-shift register cyclic shift register (end-around shift) Serial in (SI) Serial out (SO) E E E E Shift lock Shift Registers Right-Shift Register Serial in (SI) Serial out (SO) E E E E Shift lock lock SI 3 2 Initial state: 3 2 = SI sequence:,,, Register states: 2

7 Shift Registers Serial-In, Serial-Out Shift Register Serial in ata is shifted into the first flip-flop one bit at a time Serial out ata can only be read out of the last flip-flop one bit at a time 3 Shift Registers 8-Bit Serial-In, Serial-Out Shift Register Block diagram SI (Serial in) 8-bit Serial-In, Serial-Out Shift Register SO (Serial out) Logic diagram lock 7 SI S S S S S S S S SO LK R ' R ' R ' R ' R ' R ' R ' R ' Timing diagram lock SI 7 clock periods SO 7 clock periods 4

8 Shift Registers Parallel-In, Parallel-Out Shift Register Block diagram Parallel Output 3 2 SO (Serial Out) SI (Serial In) Sh (Shift En) L(LoadEn) lock 4-bit Parallel-In, Parallel-Out Shift Register 3 2 Parallel Input Application: conversion between parallel and serial data 5 Shift Registers Parallel-In, Parallel-Out Shift Register Logic diagram (implementation using FFs and MUes) 3 2 SI 3 2 Sh L LK Shift register operation Inputs Sh (Shift) L (Load) Next State SI 3 2 Action no change load right shift 3+ = Sh' L' 3 +Sh' L 3 +Sh SI 2+ = Sh' L' 2 +Sh' L 2 +Sh 3 + = Sh' L' +Sh' L +Sh 2 + = Sh' L' +Sh' L +Sh 6

9 Shift Registers Parallel-In, Parallel-Out Shift Register Timing diagram (assume 3 2 = initially and afterwards) lock L (Load) Sh (Shift) 3,, 3 2 () () t t t 2 t 3 t 4 t 5 7 Shift Registers Shift Register with Inverted Feedback A circuit that cycles through a fixed sequence of states is called a counter A shift register with inverted feedback is often called a Johnson counter Start LK 3 ' 2 ' ' Flip-flop connections State graph 8

10 esign of Binary ounters We focus on the synchronous counter, where flipflops are synchronized by a common clock pulse State table Present State B A Next State + B + A + 9 esign of Binary ounters Flip-Flop Implementation State table Present State B A Next State + B + A + Flip-Flop Inputs B A FF inputs are next-state functions in terms of A,B, 2

11 esign of Binary ounters Flip-Flop Implementation Karnaugh maps for flip-flops = AB B = A B A = A' Binary counter with flip-flops ' B' B A' A lock 2 esign of Binary ounters T Flip-Flop Implementation State table Present State B A Next State + B + A + Flip-Flop Inputs T T B T A FF inputs are next-state functions in terms of A,B, 22

12 esign of Binary ounters T Flip-Flop Implementation Karnaugh maps for flip-flops T = AB T B = A T A = Binary counter with flip-flops ' B' B A' A T T B T A lock 23 esign of Binary ounters Up-own ounter State graph and table for up-down counter U U B A + B + A + U U U U U U U U =, = count up U =, = count down 24

13 esign of Binary ounters Up-own ounter The up-down counter can be implemented using FFs and gates through the logic equations A = A + = A (U+) B = B + = B (UA+A') = + = (U+B'A') When U=, =, they reduce to binary up counter When U=, =, they reduce to A = A + = A = A' B = B + = B A' = + = B'A' 25 esign of Binary ounters Up-own ounter A = A + = A (U+) B = B + = B (UA+A') = + = (U+B'A') U lock Up-down ounter 3 ount ' B' B A' A lock lock lock U U U 26

14 esign of Binary ounters Loadable ounter with ount Enable t Ld lk 3 3 lrn lrn Ld t + B + A + B A B A Present state + (load) (no change) A + = A = (Ld' A+Ld Ain ) Ld' t B + = B = (Ld' B+Ld Bin ) Ld' t A + = = (Ld' +Ld in ) Ld' t B A Note that lrn does not appear in these equations. Why not? 27 esign of Binary ounters Loadable ounter with ount Enable A + = A = (Ld' A+Ld Ain ) Ld' t B + = B = (Ld' B+Ld Bin ) Ld' t A + = = (Ld' +Ld in ) Ld' t B A lrn ' lrn B' B lrn A' A B A lk lk lk Ld in Ld Bin Ld Ain Ld t 28

15 ounters for Other Sequences State graph State table B A + B + A + 29 ounters for Other Sequences ounter esign Using T Flip-Flops State table T FF input B A + B + A + T T B T A + T T = + 3

16 ounters for Other Sequences ounter esign Using T Flip-Flops Next-state maps = half = half + B + erivation of T inputs = half = half B= half B= half B= half A + B= half A= half A= half A= half A= half + T T = + T T B T A T ='B'+B T B ='A+B' T A =+B 3 ounters for Other Sequences ounter esign Using T Flip-Flops For T flip-flop implementation If the + map has a don t care in some square, the T map will have a don t care in the corresponding square ivide the + map into two halves corresponding to = and =, and transform each half of the map Whenever =, T= + opy the half for which = Whenever =, T=( + )' omplement the half for which = 32

17 ounters for Other Sequences ounter esign Using T Flip-Flops T flip-flop realization ' B' B A' FF K FF T K FF K T B A T A lock B 'B' B B' ' A 33 ounters for Other Sequences ounter esign Using T Flip-Flops Timing diagram Negative-edge triggered P B A T T B T A 34

18 ounters for Other Sequences ounter esign Using T Flip-Flops In the process of completing the circuit design, the transitions of the original don t care sates will be specified on t care states need to be checked to make sure they eventually lead into the main counting sequence unless a power-up reset is provided When the power in a circuit is first turned on, the initial states of the flip-flops may be unpredictable (can be in an arbitrary state) What are the transitions for states,, by the realization in Slide 33? T ='B'+B T B ='A+B' T A =+B 35 ounters for Other Sequences ounter esign Using T Flip-Flops Example (cont d) If FFs are powered up at ()=, then T =T B = and T A = leads to next state T ='B'+B T B ='A+B' T A =+B 36

19 ounters for Other Sequences ounter esign Using T Flip-Flops Example Without power-up reset, the following Johnson counter may be incorrect when powered up at states and Start LK 3 2 Flip-flop connections State graph 37 ounters for Other Sequences ounter esign Using Flip-Flops State graph Not copy this! State table B A + B + A + FF input B A + + = = + = B' B = B + = +' A = A + = A'+' = A'(+B) 38

20 ounters for Other Sequences ounter esign Using Flip-Flops = + = B' B = B + = +' A = A + = A'+' = A'(+B) ' B' B A' A K FF K FF B K FF A B' A' lock B A' B 39 ounter esign Using S-R and J-K FFs ounter esign Using S-R Flip-Flops S-R flip-flop inputs S R + + S R + S R - - inputs not allowed 4

21 ounter esign Using S-R and J-K FFs ounter esign Using S-R Flip-Flops State graph B A B A + B + A + S R S B R B S A R A + S R 4 ounter esign Using S-R and J-K FFs ounter esign Using S-R Flip-Flops Next-state maps B= half B= half A= half A= half + B + A + R R =A S-R flip-flop equations S S =B' R B S B R B ='A S B = R A R A =A S A S A =A'+' =A'(+B) 42

22 ounter esign Using S-R and J-K FFs ounter esign Using S-R Flip-Flops S-R flip-flop realization ' ' R A S B' B' B A' A ' ' R S R S LK A ' A' B (feedback lines omitted) 43 ounter esign Using S-R and J-K FFs ounter esign Using J-K Flip-Flops J-K flip-flop inputs J K + + J K + J K 44

23 ounter esign Using S-R and J-K FFs ounter esign Using J-K Flip-Flops State graph B A B A + B + A + J K J B K B J A K A + J K 45 ounter esign Using S-R and J-K FFs ounter esign Using J-K Flip-Flops Next-state maps B= half B= half A= half A= half + B + A + J K J =B' K =A J B J B = K B K B ='A J A K A J A =+B K A = J-K flip-flop equations 46

24 ounter esign Using S-R and J-K FFs ounter esign Using J-K Flip-Flops J-K flip-flop realization ' ' K A J B' B' B A' A ' ' K J K J LK ' A B (feedback lines omitted) 47 erivation of Flip-Flop Input Equations etermination of flip-flop input equations from next-state equations using Karnaugh maps = = Rules for Forming Input Map From Next-State Map* Type of Flip-Flop Input + = + = + = + = = Half of Map = Half of Map elay No change No change Trigger T No change omplement Set-Reset S No change Replace s with s** R Replace s with s** omplement J-K J No change Fill in with s K Fill in with s omplement *Always copy s from the next-state map onto the input maps first **Fill in the remaining squares with s 48

25 erivation of Flip-Flop Input Equations Flip-Flop Input Tables + + T + S R + J K Realization using J-K flip flops usually yields lower cost implementation 49 erivation of Flip-Flop Input Equations Example + ='A'B+B'+AB' T=A'B+AB'+B Next-state map input map T input map S=AB'+'A'B R=B J=A'B+AB' K=B S-R input maps J-K input maps 5

26 erivation of Flip-Flop Input Equations Example (/3) erivation of (T flip-flop) input equation using 4-variable maps B A B A = = half half + T 5 erivation of Flip-Flop Input Equations Example (2/3) erivation of 2 (S-R flip-flop) input equations using 4-variable maps 2 = half 2 = half AB 2 AB 2 AB R 2 S 2 52

27 erivation of Flip-Flop Input Equations Example (3/3) erivation of 3 (J-K flip-flop) input equations using 4-variable maps 3 AB 3 AB 3 AB 3 = half 3 = half 3 + J 3 = A+B K 3 = +AB' 53 erivation of Flip-Flop Input Equations Summary To implement a counter of N states, we need at least log 2 N flip-flops erive input equations depending on the target implementation using, T, SR, or JK flip-flops Pay attention to don t care states for power-up conditions. Sometimes reset may be needed 54

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