Final Exam review: chapter 4 and 5. Supplement 3 and 4


 Nicholas Williamson
 1 years ago
 Views:
Transcription
1 Final Exam review: chapter 4 and 5. Supplement 3 and 4 1. A new type of synchronous flipflop has the following characteristic table. Find the corresponding excitation table with don t cares used as much as possible for the new flipflop type. ANS: First expand the characteristic table as follows From Table 3, Q(t) = Q(t+1) = 0 results from X = 1 Y = 0 or 1, so X = 1, Y = x. Q(t) = 0 and Q(t+1) = 1 result from X = 0 and Y = 0 or Y = 1, so X = 0, Y = x. Q(t) = 1 and Q(t+1) = 0 result from X = 0 and Y = 1 Q(t) = 1 and Q(t+1) = 1 result from (X,Y) = 00, 10, and 11. This can be written as X 0 or 1 X.
2 Therefore, the excitation table for XY flipflop is 2. A state table is given along with an assignment of binary codes to the states. (a) In the blank Table A provided, find the state table with the states and next states represented by their binary codes. (b) In the blank Tables B provided, fill in the required D inputs to implement state variable A using a D flipflop and J and K inputs to implement state variable B using JK flipflops. Be sure to show the don t cares for J and K. (c) Find (and write in Table C) the minimum cost sumofproducts equations for the D input for flipflop A and for the J and K inputs for the flipflop B.
3 3. The clock "CLOCK" signal shown graphically below is tied in common to five different, singlebit flipflops (or latches). The "A" signal is tied to the "D", "T", "J" inputs of any D, T, or JK flipflop (or latch) respectively. The "B" signal is tied to the "K" inputs of any JK flipflop (or latch) respectively. The "Q" outputs of these different flipflops (or latches) are shown as signals W1, W2 and W3 Assume that the clock period is MUCH LONGER than the clock to output delay of the flipflops or latches. For each row in the table below, mark an "X" in the column for the waveform if that waveform is possible for the flipflop listed. If none of the waveforms fit the flipflop type, mark an "X" in the column labeled "NONE". 4. Sequence Recognizers, Moore and Mealy Models and ASM Charts.
4 (a) The State Diagram to the right recognizes an input sequence pattern. What is it? ANS: 101 (b) The sequential machine model described by the state diagram is (circle the CORRECT one): ANS: (c) In the space below, draw an ASM chart EQUIVALENT to the State Diagram above. LABLE all states, inputs, and outputs consistent with the above State Diagram.
5 5. Design a serial paritybit generator_ Assume the input x is received sequentially_ The parity bit generator will convert every third bit of the input sequence to the even parity bit of the first two bit. For example, if the inputs are 11b01b10b00b where b denotes don t cares, then the corresponding outputs are where the parity bits are in red. The state diagram has 5 states, A, B, C, D, and E, as shown below. Label on each arc the corresponding input and output. You may use b as one of the input symbol to represent don t care. ANS: 6. A toggle flipflop's characteristic table is as follows: A sequential circuit contains exactly one T flipflop. If the flipflop input equation is T(t) = AB + Q(t)B where A(t), B(t) are input variables to the sequential circuit. Find the next state equation of that sequential circuit in the minimum SOP standard format. ANS: Substitute T(t) into characteristic equation Q(t + 1) = Q(t) T(t), we have Q(t + 1) = (AB + QB)Q + (AB + QB) Q = AB Q + A B Q 7. A stateofthe art microprocessor has a clock frequency of 2GHz (2 x10 9 cycles/second) (a) What is the clock period for the microprocessor in nano (109) seconds? ANS: 0.5 ns
6 (b) Timing parameters are given for the flipflops in the Table below. What is the maximum time delay that can be tolerated for a combinational logic path from flipflop to flipflop in the microprocessor? ANS: CP = time delay + tp + tsu => time delay = CP  tp  tsu = = 0.35 ns 8. A circuit shown below will be analyzed for maximum clock rate. Assume that the circuit has been minimized. All gates and flip flops implementing the circuit have the following timing parameters:
7 (a) What is the minimum clock period for the circuit to ensure it will function properly? ANS: 4 (b) What is the minimum clock period for the circuit to ensure it will function properly? ANS: 8 + (4x7) + 4 = 40 ns 9. Construct a BCD down counter by connecting together the given components and labels:
8 10. Assuming the circuit below begins in state 0,0,0, write the sequence of states that occurs in the boxes given below the flipflops. 11. Four positive edgetriggered flipflops with asynchronous clear are shown. Connect the flipflops and additional logic to form a synchronous binary up counter (counts 0, 1, 2,,15, 0,...). This counter has an ENABLE input. With ENABLE = 1, the counter counts up. With Enable = 0, the counter holds its current value. The additional logic is to consist ONLY of AND gates with as many inputs as needed and the type of gating is to be PARALLEL (not SERIAL) to permit a high clock frequency.
9 12. A synchronous binary counter is given below along with a quad twoway multiplexer. The binary counter has a synchronous LOAD and a synchronous RESET. Q3 is the most significant bit of the counter and Q0 is the least significant bit. Add constant values to the data inputs to the multiplexer and combinational logic to the multiplexer select input S, the counter input LOAD, and the counter input RESET to generate the following sequence of counts: 0, 1, 2, 6, 7, 8, 12, 13, 14, 0,...
10 13. The block diagram of a special shift register is given below. This register is controlled by a 2bit code (S1, S0) with the operations performed listed in the table below. In the right rotate, the leftmost bits are filled with the bits falling out on the right, e.g., for a right rotates of 2 positions, become In the left shift, the vacated rightmost bits are filled with 1 s. Manually simulate the register for 8 clock cycles with the initial contents and inputs as given in the simulation table below. The results due to any given line of the table are to appear on the following line due to the positive clock edge triggering of the register.
11 14. Design a 4bit shift register that performs the following operations based on the 2bit control input SC(1:0). Neatly draw your design using the ipops given below. On the left of the page draw logic that serves all cells, if any is needed.
12 15. Using the synchronous binary counter of figure 512 and an AND gate, construct a counter that counts from 9 to 69. Add an addition input to the counter that initialized it synchronously to 9 when the signal INIT is A combinational circuit is a direct realization of the switching function: f = a c + ad + ab. The circuit is a twolevel ANDOR circuit with inverters at the input to generate a and b. All gates and inverters have a delay of 1ns. (a) Can a single input change cause a static1 hazard in this circuit? If yes, identify a single input change that causes a static1 hazard. Use a Karnaugh map to demonstrate the static1 hazard you have identified. ANS: Yes (b) Can a two input change cause a 0functional hazard in this circuit? If yes, identify 2 examples of two input change that causes a 0functional hazard Use a Karnaugh map to demonstrate the 0functional hazard you have identified. ANS: Yes
13 (c) What additional gates must be included in this circuit to eliminate all static1 hazards without changing its function (obviously). Show the additional gates on a Karnaugh map instead of drawing a logic diagram. ANS:
Lecture 8: Synchronous Digital Systems
Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered
More informationECE 223 Digital Circuits and Systems. Synchronous Logic. M. Sachdev. Dept. of Electrical & Computer Engineering University of Waterloo
ECE 223 Digital Circuits and Systems Synchronous Logic M. Sachdev Dept. of Electrical & Computer Engineering University of Waterloo Sequential Circuits Combinational circuits Output = f (present inputs)
More informationModule3 SEQUENTIAL LOGIC CIRCUITS
Module3 SEQUENTIAL LOGIC CIRCUITS Till now we studied the logic circuits whose outputs at any instant of time depend only on the input signals present at that time are known as combinational circuits.
More informationFlipFlops and Sequential Circuit Design. ECE 152A Winter 2012
FlipFlops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 FlipFlops, Registers, Counters and a Simple Processor 7.5 T FlipFlop 7.5. Configurable FlipFlops 7.6
More informationFlipFlops and Sequential Circuit Design
FlipFlops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 FlipFlops, Registers, Counters and a Simple Processor 7.5 T FlipFlop 7.5. Configurable FlipFlops 7.6
More informationLecture 8: Flipflops
Points Addressed in this Lecture Properties of synchronous and asynchronous sequential circuits Overview of flipflops and latches Lecture 8: Flipflops Professor Peter Cheung Department of EEE, Imperial
More informationSequential Logic Design
Lab #4 Sequential Logic Design Objective: To study the behavior and applications of flip flops and basic sequential circuits including shift registers and counters. Preparation: Read the following experiment.
More informationETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies
ETEC 2301 Programmable Logic Devices Chapter 10 Counters Shawnee State University Department of Industrial and Engineering Technologies Copyright 2007 by Janna B. Gallaher Asynchronous Counter Operation
More informationHaving read this workbook you should be able to: recognise the arrangement of NAND gates used to form an SR flipflop.
Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an SR flipflop. describe how such a flipflop can be SET and RESET. describe the disadvantage
More informationKarnaugh Maps. Example A B C X 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1. each 1 here gives a minterm e.g.
Karnaugh Maps Yet another way of deriving the simplest Boolean expressions from behaviour. Easier than using algebra (which can be hard if you don't know where you're going). Example A B C X 0 0 0 0 0
More informationDigital Logic Design. Basics Combinational Circuits Sequential Circuits. PuJen Cheng
Digital Logic Design Basics Combinational Circuits Sequential Circuits PuJen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction
More informationCHAPTER 11 LATCHES AND FLIPFLOPS
CHAPTER 11 LATCHES AND FLIPFLOPS This chapter in the book includes: Objectives Study Guide 11.1 Introduction 11.2 SetReset Latch 11.3 Gated D Latch 11.4 EdgeTriggered D FlipFlop 11.5 SR FlipFlop
More informationAsynchronous Counters. Asynchronous Counters
Counters and State Machine Design November 25 Asynchronous Counters ENGI 25 ELEC 24 Asynchronous Counters The term Asynchronous refers to events that do not occur at the same time With respect to counter
More informationDIGITAL SYSTEM DESIGN LAB
EXPERIMENT NO: 7 STUDY OF FLIP FLOPS USING GATES AND IC S AIM: To verify various flipflops like D, T, and JK. APPARATUS REQUIRED: Power supply, Digital Trainer kit, Connecting wires, Patch Chords, IC
More informationASYNCHRONOUS COUNTERS
LB no.. SYNCHONOUS COUNTES. Introduction Counters are sequential logic circuits that counts the pulses applied at their clock input. They usually have 4 bits, delivering at the outputs the corresponding
More informationDigital Logic Design Sequential circuits
Digital Logic Design Sequential circuits Dr. Eng. Ahmed H. Madian Email: ahmed.madian@guc.edu.eg Dr. Eng. Rania.Swief Email: rania.swief@guc.edu.eg Dr. Eng. Ahmed H. Madian Registers An nbit register
More informationTo design digital counter circuits using JKFlipFlop. To implement counter using 74LS193 IC.
8.1 Objectives To design digital counter circuits using JKFlipFlop. To implement counter using 74LS193 IC. 8.2 Introduction Circuits for counting events are frequently used in computers and other digital
More informationModule 3: Floyd, Digital Fundamental
Module 3: Lecturer : Yongsheng Gao Room : Tech  3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental
More informationUnit 4 Session  15 FlipFlops
Objectives Unit 4 Session  15 FlipFlops Usage of D flipflop IC Show the truth table for the edgetriggered D flipflop and edgetriggered JK flipflop Discuss some of the timing problems related to
More informationOutline. D Latch Example. D Latch Example: State Table. D Latch Example: Transition Table. Asynchronous Circuits (Feedback Sequential Circuits)
Outline Last time: Combinational Testability and Testpattern Generation Faults in digital circuits What is a test? : Controllability & Observability Redundancy & testability Test coverage & simple PODEM
More informationLesson 12 Sequential Circuits: FlipFlops
Lesson 12 Sequential Circuits: FlipFlops 1. Overview of a Synchronous Sequential Circuit We saw from last lesson that the level sensitive latches could cause instability in a sequential system. This instability
More informationTutorial 1: Chapter 1
Tutorial 1: hapter 1 1. Figure 1.1 shows the positive edge triggered D flip flop, determine the output of Q 0, assume output is initially LOW. Figure 1.1 2. For the positive edgetriggered JK flipflop
More informationCounters are sequential circuits which "count" through a specific state sequence.
Counters Counters are sequential circuits which "count" through a specific state sequence. They can count up, count down, or count through other fixed sequences. Two distinct types are in common usage:
More information1. Realization of gates using Universal gates
1. Realization of gates using Universal gates Aim: To realize all logic gates using NAND and NOR gates. Apparatus: S. No Description of Item Quantity 1. IC 7400 01 2. IC 7402 01 3. Digital Trainer Kit
More informationLecture 9: Flipflops
Points Addressed in this Lecture Properties of synchronous and asynchronous sequential circuits Overview of flipflops and latches Lecture 9: Flipflops Professor Peter Cheung Department of EEE, Imperial
More informationChapter  5 FLIPFLOPS AND SIMPLE FLIPFLOP APPLICATIONS
Chapter  5 FLIPFLOPS AND SIMPLE FLIPFLOP APPLICATIONS Introduction : Logic circuit is divided into two types. 1. Combinational Logic Circuit 2. Sequential Logic Circuit Definition : 1. Combinational
More informationShift registers. 1.0 Introduction
Shift registers 1.0 Introduction Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a group of flipflops connected in a chain so that the output from
More informationEdgeTriggered Dtype Flipflop
EdgeTriggered Dtype Flipflop The transparent Dtype flipflop is written during the period of time that the write control is active. However there is a demand in many circuits for a storage device (flipflop
More informationFlipFlops. Outline: 2. Timing noise
Outline: 2. Timing noise FlipFlops Signal races, glitches FPGA example ( assign bad) Synchronous circuits and memory Logic gate example 4. FlipFlop memory RSlatch example D and JK flipflops Flipflops
More informationSequential Circuits: Latches & FlipFlops
ESD I Lecture 3.b Sequential Circuits: Latches & FlipFlops 1 Outline Memory elements Latch SR latch D latch FlipFlop SR flipflop D flipflop JK flipflop T flipflop 2 Introduction A sequential circuit
More informationWEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1
WEEK 8.1 egisters and Counters ECE124 igital Circuits and Systems Page 1 Additional schematic FF symbols Active low set and reset signals. S Active high set and reset signals. S ECE124 igital Circuits
More informationSynchronous Sequential Logic. Logic and Digital System Design  CS 303 Erkay Savaş Sabanci University
Synchronous Sequential Logic Logic and Digital System Design  S 33 Erkay Savaş Sabanci University Sequential Logic Digital circuits we have learned, so far, have been combinational no memory, outputs
More informationChapter 9 Latches, FlipFlops, and Timers
ETEC 23 Programmable Logic Devices Chapter 9 Latches, FlipFlops, and Timers Shawnee State University Department of Industrial and Engineering Technologies Copyright 27 by Janna B. Gallaher Latches A temporary
More informationDIGITAL ELECTRONICS. Counters. By: Electrical Engineering Department
Counters By: Electrical Engineering Department 1 Counters Upon completion of the chapter, students should be able to:.1 Understand the basic concepts of asynchronous counter and synchronous counters, and
More informationIE1204 Digital Design F12: Asynchronous Sequential Circuits (Part 1)
IE1204 Digital Design F12: Asynchronous Sequential Circuits (Part 1) Elena Dubrova KTH / ICT / ES dubrova@kth.se BV pp. 584640 This lecture IE1204 Digital Design, HT14 2 Asynchronous Sequential Machines
More informationExperiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa
Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation
More informationClocks. Sequential Logic. A clock is a freerunning signal with a cycle time.
Clocks A clock is a freerunning signal with a cycle time. A clock may be either high or low, and alternates between the two states. The length of time the clock is high before changing states is its high
More informationDigital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill
Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Objectives: Analyze the operation of sequential logic circuits. Understand the operation of digital counters.
More informationMemory Elements. Combinational logic cannot remember
Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic
More informationCounters & Shift Registers Chapter 8 of R.P Jain
Chapter 3 Counters & Shift Registers Chapter 8 of R.P Jain Counters & Shift Registers Counters, Syllabus Design of ModuloN ripple counter, UpDown counter, design of synchronous counters with and without
More informationDigital Logic: Boolean Algebra and Gates
Digital Logic: Boolean Algebra and Gates Textbook Chapter 3 CMPE2 Summer 28 Basic Logic Gates CMPE2 Summer 28 Slides by ADB 2 Truth Table The most basic representation of a logic function Lists the output
More informationLecture 7: Sequential Networks
Lecture 7: Sequential Networks CSE 14: Components and Design Techniques for Digital Systems Fall 214 CK Cheng Dept. of Computer Science and Engineering University of California, San Diego 1 What is a sequential
More informationDigital Fundamentals
Digital Fundamentals Tenth Edition Floyd hapter 8 2009 Pearson Education, Upper 2008 Pearson Saddle River, Education NJ 07458. All Rights Reserved ounting in Binary As you know, the binary count sequence
More informationCounters and Decoders
Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4bit ripplethrough decade counter with a decimal readout display. Such a counter
More informationLatches, the D FlipFlop & Counter Design. ECE 152A Winter 2012
Latches, the D FlipFlop & Counter Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 7 FlipFlops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR
More informationMaster/Slave Flip Flops
Master/Slave Flip Flops Page 1 A Master/Slave Flip Flop ( Type) Gated latch(master) Gated latch (slave) 1 Gate Gate GATE Either: The master is loading (the master in on) or The slave is loading (the slave
More informationDesign of Digital Systems II Sequential Logic Design Principles (1)
Design of Digital Systems II Sequential Logic Design Principles (1) Moslem Amiri, Václav Přenosil Masaryk University Resource: Digital Design: Principles & Practices by John F. Wakerly Introduction Logic
More informationBasic bistable element. Chapter 6. Latches vs. flipflops. Flipflops
Basic bistable element hapter 6 It is a circuit having two stable conditions (states). It can be used to store binary symbols. FlipFlops and Simple FlipFlop Applications.. Huang, 24 igital Logic esign
More informationDigital Electronics Detailed Outline
Digital Electronics Detailed Outline Unit 1: Fundamentals of Analog and Digital Electronics (32 Total Days) Lesson 1.1: Foundations and the Board Game Counter (9 days) 1. Safety is an important concept
More informationChapter 5. Sequential Logic
Chapter 5 Sequential Logic Sequential Circuits (/2) Combinational circuits: a. contain no memory elements b. the outputs depends on the current inputs Sequential circuits: a feedback path outputs depends
More informationCS311 Lecture: Sequential Circuits
CS311 Lecture: Sequential Circuits Last revised 8/15/2007 Objectives: 1. To introduce asynchronous and synchronous flipflops (latches and pulsetriggered, plus asynchronous preset/clear) 2. To introduce
More informationEngr354: Digital Logic Circuits
Engr354: igital Circuits Chapter 7 Sequential Elements r. Curtis Nelson Sequential Elements In this chapter you will learn about: circuits that can store information; Basic cells, latches, and flipflops;
More informationENGIN 112 Intro to Electrical and Computer Engineering
ENGIN 112 Intro to Electrical and Computer Engineering Lecture 19 Sequential Circuits: Latches Overview Circuits require memory to store intermediate data Sequential circuits use a periodic signal to determine
More informationDesign Example: Counters. Design Example: Counters. 3Bit Binary Counter. 3Bit Binary Counter. Other useful counters:
Design Eample: ers er: a sequential circuit that repeats a specified sequence of output upon clock pulses. A,B,C,, Z. G, O, T, E, R, P, S,!.,,,,,,,7. 7,,,,,,,.,,,,,,,,,,,. Binary counter: follows the binary
More informationMaster/Slave Flip Flops
MSFF Master/Slave Flip Flops Page 1 A Master/Slave Flip Flop ( Type) Gated latch (master) Gated latch (slave) 1 Gate Gate GATE Either: The master is loading (the master in on) or The slave is loading (the
More informationSequential Logic Latches & Flipflops
Sequential Logic Latches & Flipflops Introduction Memory Elements PulseTriggered Latch SR Latch Gated SR Latch Gated D Latch EdgeTriggered Flipflops SR Flipflop D Flipflop JK Flipflop T Flipflop
More informationSequential Logic. (Materials taken from: Principles of Computer Hardware by Alan Clements )
Sequential Logic (Materials taken from: Principles of Computer Hardware by Alan Clements ) Sequential vs. Combinational Circuits Combinatorial circuits: their outputs are computed entirely from their present
More informationFigure 2.1(a) Bistable element circuit.
3.1 Bistable Element Let us look at the inverter. If you provide the inverter input with a 1, the inverter will output a 0. If you do not provide the inverter with an input (that is neither a 0 nor a 1),
More information7. Sequential Circuits  Combinational vs. Sequential Circuits  7. Sequential Circuits  State (2)  7. Sequential Circuits  State (1) 
Sistemas Digitais I LESI  2º ano Lesson 7  Sequential Systems Principles Prof. João Miguel Fernandes (miguel@di.uminho.pt) Dept. Informática  Combinational vs. Sequential Circuits  Logic circuits are
More informationDIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse.
DIGITAL COUNTERS http://www.tutorialspoint.com/computer_logical_organization/digital_counters.htm Copyright tutorialspoint.com Counter is a sequential circuit. A digital circuit which is used for a counting
More informationSequential Circuits: Latches & FlipFlops
Sequential Circuits: Latches & FlipFlops Sequential Circuits Combinational Logic: Output depends only on current input Able to perform useful operations (add/subtract/multiply/encode/decode/ select[mux]/etc
More informationCSE 271 Introduction to Digital Systems Supplementary Reading Some Basic Memory Elements
CE 27 Introduction to igital ystems upplementary eading ome Basic Memory Elements In this supplementary reading, we will show some some basic memory elements. In particular, we will pay attention to their
More informationBINARY CODED DECIMAL: B.C.D.
BINARY CODED DECIMAL: B.C.D. ANOTHER METHOD TO REPRESENT DECIMAL NUMBERS USEFUL BECAUSE MANY DIGITAL DEVICES PROCESS + DISPLAY NUMBERS IN TENS IN BCD EACH NUMBER IS DEFINED BY A BINARY CODE OF 4 BITS.
More informationENEE 244 (01**). Spring 2006. Homework 5. Due back in class on Friday, April 28.
ENEE 244 (01**). Spring 2006 Homework 5 Due back in class on Friday, April 28. 1. Fill up the function table (truth table) for the following latch. How is this latch related to those described in the lectures
More informationCHAPTER 3 Boolean Algebra and Digital Logic
CHAPTER 3 Boolean Algebra and Digital Logic 3.1 Introduction 121 3.2 Boolean Algebra 122 3.2.1 Boolean Expressions 123 3.2.2 Boolean Identities 124 3.2.3 Simplification of Boolean Expressions 126 3.2.4
More informationChapter 14 Sequential logic, Latches and FlipFlops
Chapter 14 Sequential logic, Latches and FlipFlops Flops Lesson 2 Sequential logic circuit, Flip Flop and Latch Introduction Ch14L2"Digital Principles and Design", Raj Kamal, Pearson Education, 2006
More informationDIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute. 2nd (Spring) term 2012/2013
DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 4. LECTURE: COUNTERS AND RELATED 2nd (Spring) term 2012/2013 1 4. LECTURE: COUNTERS AND RELATED 1. Counters,
More informationSo far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs.
equential Logic o far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs. In sequential logic the output of the
More informationSEQUENTIAL CIRCUITS. Block diagram. Flip Flop. SR Flip Flop. Block Diagram. Circuit Diagram
SEQUENTIAL CIRCUITS http://www.tutorialspoint.com/computer_logical_organization/sequential_circuits.htm Copyright tutorialspoint.com The combinational circuit does not use any memory. Hence the previous
More informationCombinational Logic Design Process
Combinational Logic Design Process Create truth table from specification Generate Kmaps & obtain logic equations Draw logic diagram (sharing common gates) Simulate circuit for design verification Debug
More informationFlipFlops, Registers, Counters, and a Simple Processor
June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 FlipFlops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number
More informationDEPARTMENT OF INFORMATION TECHNLOGY
DRONACHARYA GROUP OF INSTITUTIONS, GREATER NOIDA Affiliated to Mahamaya Technical University, Noida Approved by AICTE DEPARTMENT OF INFORMATION TECHNLOGY Lab Manual for Computer Organization Lab ECS453
More informationLatches and FlipFlops
Latches and FlipFlops Introduction to sequential logic Latches SR Latch Gated SR Latch Gated Latch FlipFlops JK Flipflop Flipflop T Flipflop JK MasterSlave Flipflop Preset and Clear functions 7474
More informationCHAPTER TEN. 10.1 New Truth Table Symbols. 10.1.1 Edges/Transitions. Memory Cells
CHAPTER TEN Memory Cells The previous chapters presented the concepts and tools behind processing binary data. This is only half of the battle though. For example, a logic circuit uses inputs to calculate
More informationChapter 3. Sequential Logic Design. Copyright 2013 Elsevier Inc. All rights reserved.
Chapter 3 Sequential Logic Design 1 Figure 3.1 Crosscoupled inverter pair 2 Figure 3.2 Bistable operation of crosscoupled inverters 3 Figure 3.3 SR latch schematic 4 Figure 3.4 Bistable states of SR
More informationOperating Manual Ver.1.1
FlipFlops Operating Manual Ver.1.1 An ISO 9001 : 2000 company 94101, Electronic Complex Pardesipura, Indore 452010, India Tel : 91731 2570301/02, 4211100 Fax: 91731 2555643 e mail : info@scientech.bz
More informationECE380 Digital Logic
ECE38 igital Logic FlipFlops, Registers and Counters: FlipFlops r.. J. Jackson Lecture 25 Flipflops The gated latch circuits presented are level sensitive and can change states more than once during
More informationET398 LAB 6. FlipFlops in VHDL
ET398 LAB 6 FlipFlops in VHDL FlipFlops March 3, 2013 Tiffany Turner OBJECTIVE The objectives of this lab are for you to begin the sequential and memory programming using flip flops in VHDL program.
More informationL4: Sequential Building Blocks (Flipflops, Latches and Registers)
L4: Sequential Building Blocks (Flipflops, Latches and Registers) Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Prof. Randy Katz (Unified
More informationSequential Circuits. Prof. MacDonald
Sequential Circuits Prof. MacDonald Sequential Element Review l Sequential elements provide memory for circuits heart of a state machine saving current state used to hold or pipe data data registers, shift
More informationLatches and FlipFlops characterestics & Clock generator circuits
Experiment # 7 Latches and FlipFlops characterestics & Clock generator circuits OBJECTIVES 1. To be familiarized with D and JK flipflop ICs and their characteristic tables. 2. Understanding the principles
More informationChapter 7. Registers & Register Transfers. J.J. Shann. J. J. Shann
Chapter 7 Registers & Register Transfers J. J. Shann J.J. Shann Chapter Overview 7 Registers and Load Enable 72 Register Transfers 73 Register Transfer Operations 74 A Note for VHDL and Verilog Users
More informationCascaded Counters. Page 1 BYU
Cascaded Counters Page 1 ModN Counters Generally we are interested in counters that count up to specific count values Not just powers of 2 A modn counter has N states Counts from 0 to N1 then rolls
More informationSequential Logic Design Principles.Latches and FlipFlops
Sequential Logic Design Principles.Latches and FlipFlops Doru Todinca Department of Computers Politehnica University of Timisoara Outline Introduction Bistable Elements Latches and FlipFlops SR Latch
More informationINTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic
More informationDigital Systems Laboratory
Digital Systems Laboratory Rev 1.2 Agust 2014 LIST OF EXPERIMENTS 1. INTRODUCTION TO LAB, USING MATERIALS 2. DIGITAL LOGIC GATES 3. INTRODUCTION TO PROTEUS 4. BINARY AND DECIMAL NUMBERS 5. CODE CONVERSION
More informationContents COUNTER. Unit III Counters
COUNTER Contents COUNTER...1 Frequency Division...2 Divideby2 Counter... 3 Toggle FlipFlop...3 Frequency Division using Toggle Flipflops...5 Truth Table for a 3bit Asynchronous Up Counter...6 Modulo
More informationDesign: a mod8 Counter
Design: a mod8 Counter A mod8 counter stores a integer value, and increments that value (say) on each clock tick, and wraps around to 0 if the previous stored value was 7. So, the stored value follows
More informationDIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute
DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 2. LECTURE: ELEMENTARY SEUENTIAL CIRCUITS: FLIPFLOPS 1st year BSc course 2nd (Spring) term 2012/2013 1
More informationDigital Logic Design Laboratory
Digital Logic Design Laboratory EE2731 Gabriel Augusto Marques Tarquinio de Souza Department of Electrical and Computer Engineering Louisiana State University and Agricultural and Mechanical College Baton
More informationDigital Electronics. 5.0 Sequential Logic. Module 5
Module 5 www.learnaboutelectronics.org Digital Electronics 5.0 Sequential Logic What you ll learn in Module 5 Section 5.0 Introduction to Sequential Logic Circuits. Section 5.1 Clock Circuits. RC Clock
More informationCDA 3200 Digital Systems. Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012
CDA 3200 Digital Systems Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012 Outline SR Latch D Latch EdgeTriggered D FlipFlop (FF) SR FlipFlop (FF) JK FlipFlop (FF) T FlipFlop
More informationAsynchronous counters, except for the first block, work independently from a system clock.
Counters Some digital circuits are designed for the purpose of counting and this is when counters become useful. Counters are made with flipflops, they can be asynchronous or synchronous and they can
More informationDigital Electronics Part I Combinational and Sequential Logic. Dr. I. J. Wassell
Digital Electronics Part I Combinational and Sequential Logic Dr. I. J. Wassell Introduction Aims To familiarise students with Combinational logic circuits Sequential logic circuits How digital logic gates
More informationUNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering. EEC180A DIGITAL SYSTEMS I Winter 2015
UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering EEC180A DIGITAL SYSTEMS I Winter 2015 LAB 7. Finite State Machine Design LED Bouncing Ball Hardware Required 2 or 3 74LS74
More informationChapter 8. Sequential Circuits for Registers and Counters
Chapter 8 Sequential Circuits for Registers and Counters Lesson 3 COUNTERS Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline Counters TFF Basic Counting element State
More informationTheory of Logic Circuits. Laboratory manual. Exercise 3
Zakład Mikroinformatyki i Teorii Automatów yfrowych Theory of Logic ircuits Laboratory manual Exercise 3 Bistable devices 2008 Krzysztof yran, Piotr zekalski (edt.) 1. lassification of bistable devices
More informationModeling Sequential Elements with Verilog. Prof. ChienNan Liu TEL: 034227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit
Modeling Sequential Elements with Verilog Prof. ChienNan Liu TEL: 034227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 41 Sequential Circuit Outputs are functions of inputs and present states of storage elements
More informationDIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 5. LECTURE: SEQUENTIAL CIRCUITS BASICS AND FLIPFLOPS
DIGITAL TECHNICS Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 5. LECTURE: SEQUENTIAL CIRCUITS BASICS AND FLIPFLOPS 1st (Autumn) term 2014/2015 5. LECTURE 1. Sequential
More informationUpon completion of unit 1.1, students will be able to
Upon completion of unit 1.1, students will be able to 1. Demonstrate safety of the individual, class, and overall environment of the classroom/laboratory, and understand that electricity, even at the nominal
More information