Synchronous (Parallel) Counters

Transcription

1 Synchronous ounter

2 Synchronous (Parallel) ounters Synchronous (parallel) counters: the flip-flops are clocked at the same time by a common clock pulse. We can design these counters using the sequential logic design process (covered in Lecture #12). Example: 2-bit synchronous binary counter (using T flip-flops, or JK flip-flops with identical J,K inputs) Present Next Flip-flop state state inputs A 1 A 0 + A 1 + A 0 TA 1 TA

3 Synchronous (Parallel) ounters Example: 2-bit synchronous binary counter (using T flip-flops, or JK flip-flops with identical J,K inputs). Present Next Flip-flop state state inputs A 1 A 0 + A 1 + A 0 TA 1 TA TA 1 = A 0 TA 0 = 1 1 J K ' A 0 J K ' A 1 LK Synchronous (Parallel) ounters 3

4 Synchronous (Parallel) ounters Example: 3-bit synchronous binary counter (using T flip-flops, or JK flip-flops with identical J, K inputs). Present Next Flip-flop state state inputs A 2 A 1 A 0 + A 2 + A 1 + A 0 TA 2 TA 1 TA A 1 A 1 A A 2 1 A A A 0 TA 2 = A 1.A 0 A 0 A 0 TA 1 = A 0 TA 0 = 1 S Synchronous (Parallel) ounters 4

5 Synchronous (Parallel) ounters Example: 3-bit synchronous binary counter (cont d). TA 2 = A 1.A 0 TA 1 = A 0 TA 0 = 1 A 2 A 1 A 0 J K J K J K P 1 Synchronous (Parallel) ounters 5

6 Synchronous (Parallel) ounters Note that in a binary counter, the n th bit (shown underlined) is always complemented whenever or Hence, X n is complemented whenever X n-1 X n-2... X 1 X 0 = As a result, if T flip-flops are used, then TX n = X n-1. X n X 1. X 0 Synchronous (Parallel) ounters 6

7 Synchronous (Parallel) ounters Example: 4-bit synchronous binary counter. TA 3 = A 2. A 1. A 0 TA 2 = A 1. A 0 TA 1 = A 0 TA 0 = 1 1 A 1.A 0 A 2.A 1.A 0 J K ' A 0 J K ' A 1 J K ' A 2 J K ' A 3 LK Synchronous (Parallel) ounters 7

8 Synchronous (Parallel) ounters Example: Synchronous decade/bd counter. lock pulse Initially (recycle) T 0 = 1 T 1 = 3 '. 0 T 2 = 1. 0 T 3 = Synchronous (Parallel) ounters 8

9 Synchronous (Parallel) ounters Example: Synchronous decade/bd counter (cont d). T 0 = 1 T 1 = 3 '. 0 T 2 = 1. 0 T 3 = T ' T ' 1 T ' 2 T 3 ' LK Synchronous (Parallel) ounters 9

10 Up/Down Synchronous ounters Up/down synchronous counter: a bidirectional counter that is capable of counting either up or down. An input (control) line Up/Down (or simply Up) specifies the direction of counting. Up/Down = 1 ount upward Up/Down = 0 ount downward Up/Down Synchronous ounters 10

11 Up/Down Synchronous ounters Example: A 3-bit up/down synchronous binary counter. lock pulse Up Down T 0 = 1 T 1 = ( 0.Up) + ( 0 '.Up' ) T 2 = ( 0. 1.Up ) + ( 0 '. 1 '. Up' ) Up counter T 0 = 1 T 1 = 0 T 2 = 0. 1 Down counter T 0 = 1 T 1 = 0 T 2 = 0. 1 S Up/Down Synchronous ounters 11

12 Up/Down Synchronous ounters Example: A 3-bit up/down synchronous binary counter (cont d). T 0 = 1 T 1 = ( 0.Up) + ( 0 '.Up' ) T 2 = ( 0. 1.Up ) + ( 0 '. 1 '. Up' ) 0 1 Up 1 T ' T ' T ' 2 LK S Up/Down Synchronous ounters 12

13 Designing Synchronous ounters overed in Lecture #12. Example: A 3-bit Gray code counter (using JK flip-flops) Present Next Flip-flop state state inputs J 2 K 2 J 1 K 1 J 0 K X 0 X 1 X X 1 X X X X 0 0 X X X 0 X X 1 0 X 0 X X 0 0 X X X 0 X 0 1 X X 0 X 1 X S Designing Synchronous ounters 13

14 Designing Synchronous ounters 3-bit Gray code counter: flip-flop inputs X X X X J 2 = 1. 0 ' X X X X J 1 = 2 ' X X X X J 0 = '. 1 ' = ( 2 1 )' X X X X 1 K 2 = 1 '. 0 ' X X X X 1 K 1 = X 1 X X 1 X K 0 = 2. 1 ' + 2 '. 1 = 2 1 S Designing Synchronous ounters 14

15 Designing Synchronous ounters 3-bit Gray code counter: logic diagram. J 2 = 1. 0 ' J 1 = 2 '. 0 J 0 = ( 2 1 )' K 2 = 1 '. 0 ' K 1 = 2. 0 K 0 = 2 1 J 0 J 1 J 2 K ' K ' 1 ' K ' 2 ' LK 0 ' S Designing Synchronous ounters 15

16 Decoding A ounter Decoding a counter involves determining which state in the sequence the counter is in. Differentiate between active-high and active-low decoding. Active-HIGH decoding: output HIGH if the counter is in the state concerned. Active-LOW decoding: output LOW if the counter is in the state concerned. S Decoding A ounter 16

17 Decoding A ounter Example: MOD-8 ripple counter (active- HIGH decoding). A' B' ' A' B' A' B ' A B lock HIGH only on count of AB = 000 HIGH only on count of AB = 001 HIGH only on count of AB = 010 HIGH only on count of AB = 111 S Decoding A ounter 17

18 Decoding A ounter Example: To detect that a MOD-8 counter is in state 0 (000) or state 1 (001). A' B' ' A' B' A' B' lock HIGH only on count of AB = 000 or AB = 001 Example: To detect that a MOD-8 counter is in the odd states (states 1, 3, 5 or 7), simply use. lock HIGH only on count of odd states S Decoding A ounter 18

19 ounters with Parallel Load ounters could be augmented with parallel load capability for the following purposes: To start at a different state To count a different sequence As more sophisticated register with increment/decrement functionality. S ounters with Parallel Load 19

20 ounters with Parallel Load Different ways of getting a MOD-6 counter: A 4 A 3 A 2 A 1 A 4 A 3 A 2 A 1 Load I 4 I 3 I 2 I 1 ount = 1 lear = 1 P lear I 4 I 3 I 2 I 1 ount = 1 Load = 0 P Inputs = 0 (a) Binary states 0,1,2,3,4,5. Inputs have no effect (b) Binary states 0,1,2,3,4,5. A 4 A 3 A 2 A 1 A 4 A 3 A 2 A 1 arry-out Load I 4 I 3 I 2 I 1 ount = 1 lear = 1 P Load I 4 I 3 I 2 I 1 ount = 1 lear = 1 P (c) Binary states 10,11,12,13,14, (d) Binary states 3,4,5,6,7,8. S ounters with Parallel Load 20

21 ounters with Parallel Load 4-bit counter with parallel load. lear P Load ount Function 0 X X X lear to 0 1 X 0 0 No change 1 1 X Load inputs Next state S ounters with Parallel Load 21

22 Introduction: Registers An n-bit register has a group of n flip-flops and some logic gates and is capable of storing n bits of information. The flip-flops store the information while the gates control when and how new information is transferred into the register. Some functions of register: retrieve data from register store/load new data into register (serial or parallel) S Introduction: Registers 22 shift the data within register (left or right)

23 Simple Registers No external gates. Example: A 4-bit register. A new 4-bit data is loaded every clock cycle. A 3 A 2 A 1 A 0 D D D D P I 3 I 2 I 1 I 0 S Simple Registers 23

24 Registers With Parallel Load Instead of loading the register at every clock pulse, we may want to control when to load. Loading a register: transfer new information into the register. Requires a load control input. Parallel loading: all bits are loaded simultaneously. S Registers With Parallel Load 24

25 Registers With Parallel Load Load I 0 Load'.A 0 + Load. I 0 D A 0 D A 1 I 1 D A 2 I 2 D A 3 I 3 LK LEAR S Registers With Parallel Load 25

26 Using Registers to implement Sequential ircuits A sequential circuit may consist of a register (memory) Next-state and value a combinational circuit. lock Register Inputs ombinational circuit Outputs The external inputs and present states of the register determine the next states of the register and the external outputs, through the combinational circuit. The combinational circuit may be implemented by any of the methods covered in MSI components and Programmable Logic Devices. S Using Registers to implement Sequential ircuits 26

27 Using Registers to implement Sequential ircuits Example 1: A 1+ = S m(4,6) = A 1.x' A 2+ = S m(1,2,5,6) = A 2.x' + A 2 '.x = A 2 x y = S m(3,7) = A 2.x Present Next state Input State Output A 1 A 2 x + A 1 + A 2 y A 1.x' A 2 x x A 1 A 2 y S Using Registers to implement Sequential ircuits 27

28 Using Registers to implement Sequential ircuits Example 2: Repeat example 1, but use a ROM. Address Outputs x A 1 A 2 8 x 3 ROM y ROM truth table S Using Registers to implement Sequential ircuits 28

29 Shift Registers Another function of a register, besides storage, is to provide for data movements. Each stage (flip-flop) in a shift register represents one bit of storage, and the shifting capability of a register permits the movement of data from stage to stage within the register, or into or out of the register upon application of clock pulses. S Shift Registers 29

30 Shift Registers Basic data movement in shift registers (four bits are used for illustration). Data in Data out Data out Data in (a) Serial in/shift right/serial out (b) Serial in/shift left/serial out Data in Data in Data in Data out (c) Parallel in/serial out Data out (d) Serial in/parallel out Data out (e) Parallel in / parallel out (f) Rotate right (g) Rotate left S Shift Registers 30

31 Serial In/Serial Out Shift Registers Accepts data serially one bit at a time and also produces output serially. Serial data input D 0 D 1 D 2 D 3 Serial data output LK S Serial In/Serial Out Shift Registers 31

32 Serial In/Serial Out Shift Registers Application: Serial transfer of data from one register to another. SI Shift register A SO SI Shift register B SO lock Shift control P lock Shift control P Wordtime T 1 T 2 T 3 T 4 S Serial In/Serial Out Shift Registers 32

33 Serial In/Serial Out Shift Registers Serial-transfer example. Timing Pulse Shift register A Shift register B Serial output of B Initial value After T After T After T After T S Serial In/Serial Out Shift Registers 33

34 Serial In/Parallel Out Shift Registers Accepts data serially. Outputs of all stages are available Data input D D D D simultaneously. LK Data input LK D SRG 4 Logic symbol S Serial In/Parallel Out Shift Registers 34

35 Parallel In/Serial Out Shift Registers Bits are entered simultaneously, but output is serial. Data input D 0 D 1 D 2 D 3 SHIFT/LOAD D Serial D D D data out LK SHIFT. 0 + SHIFT'.D 1 S Parallel In/Serial Out Shift Registers 35

36 Parallel In/Serial Out Shift Registers Bits are entered simultaneously, but output is serial. Data in D 0 D 1 D 2 D 3 SHIFT/LOAD LK SRG 4 Serial data out Logic symbol S Parallel In/Serial Out Shift Registers 36

37 Parallel In/Parallel Out Shift Registers Simultaneous input and output of all data bits. Parallel data inputs D 0 D 1 D 2 D 3 D D D D LK Parallel data outputs S Parallel In/Parallel Out Shift Registers 37

38 Bidirectional Shift Registers Data can be shifted either left or right, using a control line RIGHT/LEFT (or simply RIGHT) to indicate the direction. RIGHT/LEFT Serial data in RIGHT. 0 + RIGHT'. 2 D D 1 D 2 D 3 LK 0 S Bidirectional Shift Registers 38

39 Bidirectional Shift Registers 4-bit bidirectional shift register with parallel Parallel outputs load. A 4 A 3 A 2 A 1 lear D D D D LK s 1 4x1 s MUX x1 MUX x1 MUX x1 MUX Serial input for shift-right I 4 I 3 I 2 I 1 Serial input for shift-left Parallel inputs S Bidirectional Shift Registers 39

40 Bidirectional Shift Registers 4-bit bidirectional shift register with parallel load. Mode ontrol s 1 s 0 Register Operation 0 0 No change 0 1 Shift right 1 0 Shift left 1 1 Parallel load S Bidirectional Shift Registers 40

41 An Application Serial Addition Most operations in digital computers are done in parallel. Serial operations are slower but require less equipment. A serial adder is shown below. A A + B. Shift-right P External input SI SI Shift-register A Shift-register B SO SO x y z FA D S lear S An Application Serial Addition 41

42 An Application Serial Addition A = 0100; B = A + B = 1011 is stored in A after 4 clock pulses. Initial: A: B: : 0 Step 1: S = 1, = 0 Step 2: S = 1, = 0 Step 3: S = 0, = 1 Step 4: S = 1, = 0 A: B: x A: B: x x 0 1 A: B: x x x 0 A: B: x x x x : 0 : 0 : 1 : 0 S An Application Serial Addition 42

43 Shift Register ounters Shift register counter: a shift register with the serial output connected back to the serial input. They are classified as counters because they give a specified sequence of states. Two common types: the Johnson counter and the Ring counter. S Shift Register ounters 43

44 Ring ounters One flip-flop (stage) for each state in the sequence. The output of the last stage is connected to the D input of the first stage. An n-bit ring counter cycles through n states. No decoding gates are required, as there is an output that corresponds to every state the counter is in. S Ring ounters 44

45 Ring ounters Example: A 6-bit (MOD-6) ring counter. PRE D D D D D D LR LK lock S Ring ounters 45

46 Johnson ounters The complement of the output of the last stage is connected back to the D input of the first stage. Also called the twisted-ring counter. Require fewer flip-flops than ring counters but more flip-flops than binary counters. An n-bit Johnson counter cycles through 2n states. Require more decoding circuitry than ring S Johnson ounters 46 counter but less than binary counters.

47 Johnson ounters Example: A 4-bit (MOD-8) Johnson counter. LR LK D D D D ' 3 ' lock S Johnson ounters 47

48 Johnson ounters Decoding logic for a 4-bit Johnson counter. lock A B D Decoding A'.D' A.B' B.' D' A.D A'.B B' '.D A' D' A B' B ' D' State 0 State 1 State 2 State 3 B' State 6 A D State 4 ' D State 7 A' B State 5 S Johnson ounters 48

49 Random Access Memory (RAM) A memory unit stores binary information in groups of bits called words. The data consists of n lines (for n-bit words). Data input lines provide the information to be stored (written) into the memory, while data output lines carry the information out (read) from the memory. The address consists of k lines which specify which word (among the 2 k words available) to be selected for reading or writing. S Random Access Memory (RAM) 49 The control lines Read and Write (usually

50 Random Access Memory (RAM) Block diagram of a memory unit: n data input lines n k address lines Read/Write k Memory unit 2 k words n bits per word n n data output lines S Random Access Memory (RAM) 50

51 Random Access Memory (RAM) ontent of a 1024 x 16-bit memory: Memory address binary decimal Memory content : : : : : : S Random Access Memory (RAM) 51

52 Random Access Memory (RAM) The Write operation: Transfers the address of the desired word to the address lines Transfers the data bits (the word) to be stored in memory to the data input lines Activates the Write control line (set Read/Write to 0) The Read operation: Transfers the address of the desired word to the address lines S Random Access Memory (RAM) 52 Activates the Read control line (set Read/Write to 1)

53 Random Access Memory (RAM) The Read/Write operation: Memory Enable Read/Write Memory Operation 0 X None 1 0 Write to selected word 1 1 Read from selected word Two types of RAM: Static and dynamic. Static RAMs use flip-flops as the memory cells. Dynamic RAMs use capacitor charges to represent data. Though simpler in circuitry, they have to be constantly refreshed. S Random Access Memory (RAM) 53

54 Random Access Memory (RAM) A single memory cell of the static RAM has the following logic and block diagrams. Select R Select Input S Output Input B Output Read/Write Logic diagram Read/Write Block diagram S Random Access Memory (RAM) 54

55 Random Access Memory (RAM) Logic construction of a 4 x 3 RAM (with decoder and OR gates): S Random Access Memory (RAM) 55

56 Random Access Memory (RAM) An array of RAM chips: memory chips are combined to form larger memory. A 1K x 8-bit RAM chip: RAM 1K x 8 Input data Address hip select Read/write DATA (8) ADRS (10) S RW (8) Output data Block diagram of a 1K x 8 RAM chip S Random Access Memory (RAM) 56

57 Random Access Memory (RAM) Lines Read/write Address 2x4 decoder S 0 S 1 4K x 8 RAM. Lines Input data 8 lines DATA (8) ADRS (10) S 1K x 8 RW (8) DATA (8) (8) ADRS (10) S 1K x 8 RW DATA (8) (8) ADRS (10) S 1K x 8 RW DATA (8) (8) ADRS (10) S 1K x 8 RW Output data S Random Access Memory (RAM) 57

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