Understanding Sequential Circuit Timing


 Buck Sherman
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1 ENGIN112: Inroducion o Elecrical and Compuer Engineering Fall 2003 Prof. Russell Tessier Undersanding Sequenial Circui Timing Perhaps he wo mos disinguishing characerisics of a compuer are is processor clock speed and he size of is main memory. While i is relaively easy o undersand he concep of main memory size (he number of sorage bis in he compuer), he concep of processor clock speed is a lile more difficul o grasp. In his documen we will explain wha is mean by sequenial circui clock speed, and more imporanly, how o calculae i using he iming parameers of combinaional and sequenial circui componens. T per Figure 1: Periodic Clock Signal As we have discussed his erm, edgerigged flip flops, such as he D flip flop, are conrolled by a clock signal, such as he signal labeled in Figure 1. A clock signal is a periodic square wave which alernaes beween logic high (1) and logic low (0) values a predicable imes. The amoun of ime beween rising clock edges is called he clock period, T per, of he clock. In modern compuers he clock period is usually under 10 nanoseconds (10 ns). The inverse of he 1 clock period ( T per )isheclock frequency, f. Since he clock is used as he conrol inpu o edgeriggered flip flops, he clock frequency measures how ofen he daa is ransfered, or clocked, ino edgeriggered flip flops. A bigger clock frequency indicaes ha daa is being sored more quickly, and he sequenial circui is generaing resuls a a faser rae. Typical clock frequencies for modern compuer sysems range from 1 megaherz (MHz) o around 5 gigaherz (GHz). 1 Timing Parameers for Combinaional Logic When implemened physically, combinaional circuis, such as AND and OR gaes, exhibi cerain iming characerisics. When a binary value (0 or 1) is applied a he inpu o a combinaional circui, he change a he circui oupu is no insananeous due o elecrical consrains. Circui inpuooupu delay in combinaional circuis can be expressed wih wo parameers, pd and cd, defined as follows: Propagaion delay ( pd )  This value indicaes he amoun of ime needed for a change in a logic inpu o resul in a permanen change a an oupu. Combinaional logic is guaraneed no o show any furher oupu changes in response o an inpu change afer pd ime unis have passed. 1
2 X Y X cd cd Y pd pd Figure 2: Combinaional Propagaion and Conaminaion Delay Conaminaion delay ( cd )  This value indicaes he amoun of ime needed for a change in a logic inpu o resul in an iniial change a an oupu [1]. Combinaional logic is guaraneed no o show any oupu change in response o an inpu change before cd ime unis have passed. An example of combinaional propagaion and conaminaion delay appears in Figure 2. When inpu X changes, he change in Y is no insananeous. The inverer oupu mainains is iniial value unil ime cd has passed. Afer his ime, he Y oupu of he inverer may be a an inermediae value for a while (indicaed by he crosshached area) before he final oupu value is creaed. Afer he propagaion delay, pd, he inverer oupu is sable and is guaraneed no o change again unil anoher inpu change. Combinaional propagaion delays are addiive. I is possible o deermine he propagaion delay of a larger combinaional circui by adding he propagaion delays of he circui componens along he longes pah. For example, he propagaion delay of he combined circui in Figure 3 is 5 ns, since he longes delay from a circui inpu (w, x, y) o he oupu z is he sum of he componen propagaion delays hrough gaes A and B, 3 ns + 2 ns = 5 ns. The 4 ns propagaion delay pah hrough gaes C and B can be ignored in deermining he overall propagaion delay of he circui since i is shorer han 5 ns. In conras, he deerminaion of he conaminaion delay of he combined circui requires idenifying he shores pah of conaminaion delays from inpu o oupu. In Figure 3, he conaminaion delay of he combined circui is 2 ns, since he shores sum of conaminaion delays from an inpu (y) o an oupu (z), is cd (C) + cd (B) + 1 ns = 2ns. Noe ha his value is smaller han he conaminaion delay pah hrough gaes A and B (2 ns + 1ns = 3 ns). 2
3 cd pd = 3 ns w x A cd pd B z y C cd pd Figure 3: Combined Combinaional Circui Dealy 2 Timing Parameers for Sequenial Logic Like combinaional circuis, when sequenial circuis, such as edgeriggered flipflops, are physically implemened, hey exhibi cerain iming characerisics. Unlike combinaional circuis, hese characerisics are specified in relaion o he clock inpu. Since flipflops only change value in response o a change in he clock value, iming parameers can be specified in relaion o he rising (for posiive edgeriggered) or falling (for negaiveedge riggered) clock edge. The following parameers specify sequenial circui behavior. Unless oherwise specified, he following descripions perain o posiive edgeriggered circuis. Similar definiions can be made for negaive edgeriggered circuis. Propagaion delay ( Q )  This value indicaes he amoun of ime needed for a change in he flip flopclock inpu (e.g. rising edge) o resul in a permanen change a he flipflop oupu (Q). When he clock edge arrives, he D inpu value is ransfered o oupu Q. Noe from Figure 4, ha he oupu of he flipflop may be a an inermediae value for a while (indicaed by he crosshached area) before he final oupu value is creaed. Afer Q, he oupu is guaraneed no o change value again unil anoher clock edge rigger (e.g. rising edge) arrives. Conaminaion delay ( cd )  This value indicaes he amoun of ime needed for a change in he flipflop clock inpu o resul in he iniial change a he flipflop oupu (Q). Noe from Figure 4, ha he oupu of he flipflop mainains is iniial value unil ime cd has passed. The flipflop is guaraneed no o show any oupu change in response o an inpu change unil afer cd has passed. Seup ime ( s )  This value indicaes he amoun of ime before he clock edge ha daa inpu D mus be sable. As shown in Figure 4, D is sable s ime unis before he rising 3
4 D D Q Q s h D Q cd clk Q Figure 4: Seup and Hold Time for Sequenial Circuis clock edge. Hold ime ( h )  This value indicaes he amoun of ime afer he clock edge ha daa inpu D mus be held sable. As shown in Figure 4, he hold ime is always measured from he rising clock edge (for posiive edgeriggered) o a poin afer he edge. Seup and hold imes are resricions ha a flipflop places on combinaional or sequenial circuiry ha drives a flipflop D inpu. The circui mus be designed so ha he D flip flop inpu signal arrives a leas s ime unis before he clock edge and does no change unil a leas h ime unis afer he clock edge. If eiher of hese resricions are violaed for any of he flipflops in he circui, he circui will no operae correcly. These resricions limi he maximum clock frequency a which he circui can operae. If he rising clock edges in Figure 1 are oo close ogeher, daa will no have enough ime o propagae hrough he circui o he flipflop inpu and arrive s ime unis before he rising clock edge. 3 Deermining he Max. Clock Frequency for a Sequenial Circui Mos digial circuis conain boh combinaional componens (gaes, muxes, adders, ec.) and sequenial componens (flipflops). These componens can be combined o form sequenial circuis ha perform compuaion and sore resuls. By using combinaional and sequenial componen parameers, i is possible o deermine he maximum clock frequency a which a circui will operae and generae correc resuls. This analysis can bes be examined hrough use of an example. A sample sequenial cicui is shown in Figure 5. Before saring iming analysis, consider he flow of daa in his circui in response o a rising clock 4
5 clk Q = 10 ns D clk Q = 10 ns cd D Q X cd pd F = 5 ns Y cd s h D Q Ou A B Figure 5: An Example Sequenial Circui edge, saring a flipflop A. 1. Following he rising clock edge on, a valid oupu appears on signal X afer Q = 10 ns. 2. A valid oupu Y appears a he oupu of inverer F, pd = 5 ns afer a valid X arrives a he gae. 3. Signal Y is clocked ino flipflop B on he nex rising clock edge. This signal mus arrive a leas s = 2ns before he rising clock edge. As a resul, he minimum clock period, T min of he circui is: T min = Q (A)+ pd (F )+ s (B) =10ns +5ns +2ns =17ns (1) 1 and he maximum clock frequency of he circui is T min = 1 17ns = 58.8 MHz. Waveforms ha show he deerminaion of he minimum clock period are show in Figure 6. Since he inpu is aached o boh flipflops, boh will change value a he same ime. On each clock edge, he same hree seps saring from flip flop A are repeaed. On he nex edge, a new value is clocked ino flipflop B ha is a resul of he previous clock edge on flipflop A. In a ypical sequenial circui design here are ofen millions of flipflop o flipflop pahs ha need o be considered in calculaing he maximum clock frequency. This frequency mus be deermined by locaing he longes pah among all he flipflop pahs in he circui. For example, consider he circui shown in Figure 7. In his example, here are hree flipflop o flipflop pahs (flop A o flop 5
6 D clk Q pd s X Y Ou Figure 6: Timing Waveforms for he Circui in Fig. 5 B, flop A o flop C, flop B o flop C). Using an approach similar o Equaion 1, he delay along all hree pahs are: T AB = Q (A) + s (B) =9ns+2ns=11ns T AC = Q (A) + pd (Z) + s (C) =9ns+4ns+2ns=15ns T BC = Q (B) + pd (Z) + s (C) =10ns+4ns+2ns=16ns Since he T BC is he larges of he pah delays, he minimum clock period for he circui is T min = 16 ns and he maximum clock frequency is 1 T min = 62.5 MHz. 4 Validaing FlipFlop Hold Time Unforunaely, simply designing a circui for a specific maximum clock frequency is no enough o ensure ha he circui will work properly. As menioned earlier, he hold ime, h mus be saisfied for each flipflop inpu, indicaing ha each D inpu canno change unil h ime unis afer he clock edge. Forunaely, he conaminaion delays of combinaional circuiry and flipflops help preven flipflop inpus from changing insananeously. This observaion can be illusraed by reexamining Figure 5. The hold ime requiremen on flipflop B indicaes ha he Y inpu o flipflop B should no change unil a leas 2 ns afer he rising clock edge of. By examining he circui, i can be seen ha he earlies he signal can sar o change is equal o he sum of he conaminaion delays of flipflop A and inverer X. Therefore, if 6
7 clk Q = 9 ns cd s h A pd = 4 ns cd Comb. Logic clk Q = 9 ns cd s h C B clk Q = 10 ns cd s h Figure 7: Mulipah Sequenial Circui h (B) cd (A)+ cd (X) (2) he circui is guaraneed o work correcly. Since h, 2 ns, is less han cd (A)+ cd (B), 4 ns, he hold ime is saisifed and he circui will work correcly. A similar analysis can be performed along each flipflop o flipflop pah in Figure 7. These hree pahs lead o he following relaionships for he A o B, A o C, and B o C pahs, respecively: h (B) cd (A) [A o B pah] (3) h (C) cd (A)+ cd (Z) [A o C pah] (4) h (C) cd (B)+ cd (Z) [B o C pah] (5) plugging in he values from Figure 7 gives: 1ns 2ns [A o B pah] (6) 1ns 2ns +2ns [A o C pah] (7) 1ns 2ns +2ns [B o C pah] (8) I is apparen ha even he fases flipflop o flipflop pah (2 ns) is slower ha he required hold ime (1 ns). None of he flip flop inpu values will change unil a leas 2 ns following he clock edge due o he conaminaion delays along he pahs. For each circui in he pah, he conaminaion delay guaranees ha a change in he circui inpu will no be shown a he circui oupu unil cd ime unis. 7
8 5 Conclusion Sequenial circuis rely on a clock signal o conrol he movemen of sysem daa. Given a se of combinaional and sequenial componens and heir associaed iming parameers, i is possible o deermine he maximum clock frequency ha can be used wih he circui. This analysis includes he examinaion of every flipflop o flipflop pah in he circui. The examinaion includes boh he propagaion delays along he pahs and he daa seup ime a he desinaion flipflop. Following he calculaion of he maximum clock frequency, each flipflop o flipflop pah can be examined o ensure ha flipflop hold imes are saisfied. If he conaminaion delays along each pah are greaer han or equal o he desinaion flip flop hold ime, he circui will operae as designed. References [1] S. Ward and R. Halsead. Compuaion Srucures. McGrawHill, Boson, Ma,
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