Chapter 1 Introduction to CMOS Circuit Design

Transcription

1 Chpter 1 Introduction to CMOS Circuit Design Jin-Fu Li Advnced Relile Systems (ARES) L. Deprtment of Electricl Engineering Ntionl Centrl University Jhongli, Tiwn

2 Outline Introduction MOS Trnsistor Switches CMOS Logic Circuit nd System Representtion Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 2

3 Binry Counter Present stte Next stte A A B B A = + B = + CK CLR Source: Prof. V. D. Agrwl Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 3

4 1-it Multiplier A C B C=AxB Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 4

5 Switch: MOSFET MOSFETs re sic electronic devices used to direct nd control logic signls in IC design MOSFET: Metl-Oxide-Semiconductor Field- Effect Trnsistor N-type MOS (NMOS) nd P-type MOS (PMOS) Voltge-controlled switches A MOSFET hs four terminls: gte, source, drin, nd sustrte (ody) Complementry MOS (CMOS) Using two types of MOSFETs to crete logic networks NMOS & PMOS Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 5

6 P-N Junctions A junction etween p-type nd n-type semiconductor forms diode. Current flows only in one direction p-type n-type node cthode Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 6

7 NMOS Trnsistor Four terminls: gte, source, drin, ody Gte oxide ody stck looks like cpcitor Gte nd ody re conductors SiO 2 (oxide) is very good insultor Clled metl oxide semiconductor (MOS) cpcitor Even though gte is no longer mde of metl Source Gte Drin Polysilicon SiO 2 n+ n+ p ulk Si Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 7

8 NMOS Opertions Body is commonly tied to ground (0 V) When the gte is t low voltge: P-type ody is t low voltge Source-ody nd drin-ody diodes re OFF No current flows, trnsistor is OFF Source Gte Drin Polysilicon SiO 2 n+ p n+ ulk Si S 0 D Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 8

9 NMOS Opertions (Cont.) When the gte is t high voltge: Positive chrge on gte of MOS cpcitor Negtive chrge ttrcted to ody Inverts chnnel under gte to n-type Now current cn flow through n-type silicon from source through chnnel to drin, trnsistor is ON Source Gte Drin Polysilicon SiO 2 n+ p n+ ulk Si S 1 D Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 9

10 PMOS Opertions Similr, ut doping nd voltges reversed Body tied to high voltge (V DD ) Gte low: trnsistor ON Gte high: trnsistor OFF Bule indictes inverted ehvior Polysilicon Source Gte Drin SiO 2 p+ p+ n ulk Si Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 10

11 Threshold Voltge Every MOS trnsistor hs chrcterizing prmeter clled the threshold voltge V T The specific vlue of V T is estlished during the mnufcturing process Threshold voltge of n NMOS nd PMOS NMOS PMOS V A Gte + V GSn Drin Mn - Source V DD V Tn 0 V A V A =1 Mn On V A =0 Mn Off V A V GSp Source + V DD - Mp Gte Drin V A V DD V DD - V Tp 0 V A =1 Mp Off V A =0 Mp On Gte-source voltge Logic trnsltion Gte-source voltge Logic trnsltion Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 11

12 MOS Trnsistor is Like Tp Source: Prof. Bnerjee, ECE, UCSB Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 12

13 MOSFET & FinFET G S(D) Si-Sustrte D(S) MOSFET D(S) D(S) G G S(D) Oxide Si-Sustrte Bulk FinFET S(D) Buried Oxide Si-Sustrte SOI FinFET Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 13

14 IG & SG FinFETs According to the gte structure, FinFET cn e clssified s Independent-Gte (IG) FinFET Short-Gte (SG) FinFET D(S) D(S) G G S(D) G S(D) Oxide Oxide Si-Sustrte IG FinFET Si-Sustrte SG FinFET Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 14

15 MOS Switches NMOS symol nd chrcteristics 0v 5v 5v 0v V th 5v-V th PMOS symol nd chrcteristics 0v 5v 0v V th V th 5v Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 15

16 CMOS Switch A complementry CMOS switch Trnsmission gte -s -s Symols C s s s 0v Chrcteristics 0v 5v 5v 0v 5v Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 16

17 CMOS Logic-Inverter The NOT or INVERT function is often considered the simplest Boolen opertion F(x)=NOT(x)=x Vdd Vin Vout Vin Vout Vdd Vdd Vdd Vdd/2 Indeterminte logic level Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 17

18 Seril structure Comintionl Logic S1=0 S2=0 S1=0 S2=1 S1=1 S2=0 S1=1 S2=1 S1 S1 S2 S !=!=!= = S1=0 S2=0 S1=0 S2=1 S1=1 S2=0 S1=1 S2=1 S1 S1 S2 S =!=!=!= Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 18

19 Prllel structure Comintionl Logic S1=0 S2=0 S1=0 S2=1 S1=1 S2=0 S1=1 S2=1 S1 0 1 S1 S2 S2 0 1!= = = = S1=0 S2=0 S1=0 S2=1 S1=1 S2=0 S1=1 S2=1 S1 0 1 S1 S2 S2 0 1 = = =!= Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 19

20 NAND Gte Output A A 0 1 B B A B Output Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 20

21 NOR Gte A B Output 0 A 1 B A B Output Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 21

22 F (( AB) ( CD)) Compound Gte A B C D F A B C D F A C B D Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 22

23 Structured Logic Design CMOS logic gtes re intrinsiclly inverting The output lwys produces NOT opertion cting on the input vriles For exmple, the inverter shown elow illustrtes this property 1 V DD =1 f=0 0 Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 23

24 Structured Logic Design The inverting nture of CMOS logic circuits llows us to construct logic circuits for AOI nd OAI expressions using structured pproch AOI logic function Implements the opertions in the order AND then OR then NOT E.g., g (,, c, d ). c. d OAI logic function Implements the opertions in the order OR then AND then NOT E.g., g (,, c, d ) ( ) ( c d ) Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 24

25 Structured Logic Design Behviors of nmos nd pmos groups Prllel-connected nmos OR-NOT opertions Prllel-connected pmos AND-NOT opertions Series-connected nmos AND-NOT opertions Series-connected pmos OR-NOT opertions Consequently, wired groups of nmos nd pmos re logicl duls of nother Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 25

26 Dul Property If n NMOS group yields function of the form g ( c ) then n identiclly wired PMOS rry gives the dul function G ( c) where the AND nd OR opertions hve een interchnged This is n interesting property of NMOS-PMOS logic tht cn e exploited in some CMOS designs Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 26

27 An Exmple of Structured Design X ( c d ) Group 3 c V DD c d Group 1 Group 2 X d Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 27

28 Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 28 An Exmple of XOR Gte Boolen eqution of the two input XOR gte, this is not in AOI form But,, this is in AOI form Therefore, ) ( V DD V DD XOR Gte XNOR Gte

29 Multiplexer A B 1 0 Y A B C D Y S -S A S1 S0 A S Y B Y B C -S D S1 -S1 S0 -S0 Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 29

30 Sttic CMOS Summry In sttic circuits t every point in time (except when switching), the output is connected to either Vdd or Gnd through low resistnce pth Fn-in of n (or n inputs) requires 2n (n N-type nd n P- type) devices Non-rtioed logic: gtes operte independent of PMOS or NMOS sizes No pth ever exists etween Vdd nd Gnd: low sttic power Fully-restored logic (NMOS psses 0 only nd PMOS psses 1 only Gtes must e inverting Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 30

31 Design Flow for VLSI Chip Specifiction Function Behviorl Design Function Structurl Design Physicl Design Function Timing Power Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 31

32 Circuit nd System Representtions Behviorl representtion Functionl, high level For documenttion, simultion, verifiction Structurl representtion System level CPU, RAM, I/O Functionl level ALU, Multiplier, Adder Gte level AND, OR, XOR Circuit level Trnsistors, R, L, C For design & simultion Physicl representtion For friction Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 32

33 Behvior Representtion A one-it full dder (Verilog) module fdder(sum,cout,,,ci); output sum, cout; input,, ci; reg sum, cout; or or ci) egin sum = ^^ci; cout = (&) (&ci) (ci&); end endmodule ci fdder sum cout Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 33

34 Structure Representtion A four-it full dder (Verilog) module dder4(s,c4,,,ci); output[3:0] sum; output c4; input[3:0], ; input ci; reg[3:0] s; reg c4; wire[2:0] co; fdder 0(s[0],co[0],[0],[0],ci); fdder 1(s[1],co[1],[1],[1],co[0]); fdder 2(s[2],co[2],[2],[2],co[1]); fdder 3(s[3],c4,[3],[3],co[2]); endmodule ci [0] 0 [0] s[0] 1 [1] [1] [2] [2] [3] [3] co[0] co[1] co[2] 2 3 s[1] s[2] s3] s dder4 Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 34

35 Physicl Representtion Lyout of 4-it NAND gte Vdd Vdd in1 in2 in3 in4 in1 Out Out in2 in3 in4 Gnd in1 in2 in3 in4 Advnced Relile Systems (ARES) L. Jin-Fu Li, EE, NCU 35