Dynamic Combinational Circuits
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1 Dynamic Combinational Circuits Dynamic circuits Charge sharing, charge redistribution Domino logic np-cmos (zipper CMOS) James Morizio 1
2 Dynamic Logic Dynamic gates use a clocked pmos pullup Two modes: precharge and evaluate 2 1 2/3 4/3 1 1 Static Pseudo-nMOS Dynamic Precharge Evaluate Precharge James Morizio 2
3 The Foot What if pulldown network is ON during precharge? Use series evaluation transistor to prevent fight. precharge transistor inputs f inputs f foot footed unfooted James Morizio 3
4 Dynamic Logic M p Out In 1 In 2 In 3 PDN C L In 1 In 2 In 3 PUN Out M p C L n network Precharge 2 phase operation: Evaluation p network James Morizio 4
5 Logical Effort Inverter NND2 NOR2 unfooted 1 1 g d = 1/3 p d = 2/3 B g d = 2/3 p d = 3/3 1 1 B 1 g d = 1/3 p d = 3/3 footed B 3 2 B 2 g d = 2/3 g d = 3/3 2 p d = 3/3 3 p d = 4/3 2 g d = 2/3 p d = 5/3 James Morizio 5
6 Dynamic Logic N+2 transistors for N-input function Better than 2N transistors for complementary static CMOS Comparable to N+1 for ratio-ed logic No static power dissipation Better than ratio-ed logic Careful design, clock signal needed James Morizio 6
7 Dynamic Logic: Principles Precharge M p Out = 0, Out is precharged to by M p. is turned off, no dc current flows (regardless of input values) In 1 In 2 In 3 PDN C L Evaluation = 1, is turned on, M p is turned off. Output is pulled down to zero depending on the values on the inputs. If not, precharged value remains on C L. Important: Once Out is discharged, it cannot be charged again! Gate input can make only one transition during evaluation Minimum clock frequency must be maintained Can be eliminated? James Morizio 7
8 Example M p Out Ratioles s B C No Static Power Cons umption Nois e Margins s mall (NM L ) Requires Cloc k James Morizio 8
9 Dynamic 4 Input NND Gate James Morizio 9
10 Cascading Dynamic Gates V M p Out1 M p Out2 In In Out1 V Tn Out2 t Internal nodes can only make 0-1 transitions during evaluation period James Morizio 10
11 Monotonicity Dynamic gates require monotonically rising inputs during evaluation 0 -> 0 0 -> 1 1 -> 1 But not 1 -> 0 violates monotonicity during evaluation Precharge Evaluate Precharge Output should rise but does not James Morizio 11
12 Monotonicity Woes But dynamic gates produce monotonically falling outputs during evaluation Illegal for one dynamic gate to drive another! = 1 X Precharge Evaluate X Precharge X monotonically falls during evaluation should rise but cannot James Morizio 12
13 Reliability Problems Charge Leakage M p Out (1) (2) C L V out precharge evaluate t = 0 (a) Leakage sources (b) Effect on waveforms t (1) Leakage through reverse-biased diode of the diffusion area (2) Subthreshold current from drain to source Minimum Clock Frequency: > 1 MHz James Morizio 13
14 Leakage Dynamic node floats high during evaluation Transistors are leaky (I OFF 0) Dynamic value will leak away over time Formerly miliseconds, now nanoseconds! Use keeper to hold dynamic node Must be weak enough not to fight evaluation weak keeper 1 k 2 X H 2 James Morizio 14
15 Charge Sharing (redistribution) ssume: during precharge, and B are 0, C a is discharged During evaluation, B remains 0 and rises to 1 Charge stored on C L is now redistributed over C L and C a M p Out B = 0 M a M b X C a C L C L = C L V out (t) + C a V X V X = - V t, therefore C δv out (t) = V out (t) - = a ( -V t ) C L C b Desirable to keep the voltage drop below threshold of pmos transistor (why?) C a /C L < 0.2 James Morizio 15
16 Charge Sharing Dynamic gates suffer from charge sharing B = 0 x C x C Charge sharing noise x C V = V = V x DD Cx + C James Morizio 16
17 Charge Redistribution - Solutions M p M bl Out M p M bl Out M a M a B M b B M b (a) Static bleeder (b) Precharge of internal nodes James Morizio 17
18 Secondary Precharge Solution: add secondary precharge transistors Typically need to precharge every other node Big load capacitance C helps as well x secondary precharge transistor B James Morizio 18
19 Domino Logic M p Out1 M p M r Out2 In 1 In 2 PDN In 4 PDN Static Inverter with Level Restorer In 3 Static inverters between dynamic stages James Morizio 19
20 Domino Gates Follow dynamic stage with inverting static gate Dynamic / static pair is called domino gate Produces monotonic outputs Precharge Evaluate Precharge domino ND W W X Z X B C Z dynamic NND static inverter B W H C X H X Z = B C Z James Morizio 20
21 Domino Logic - Characteristics Only non-inverting logic Very fast - Only 1->0 transitions at input of inverter Precharging makes pull-up very fast dding level restorer reduces leakage and charge redistribution problems Optimize inverter for fan-out James Morizio 21
22 Domino Optimizations Each domino gate triggers next one, like a string of dominos toppling over Gates evaluate sequentially but precharge in parallel Thus evaluation is more critical than precharge HI-skewed static stages can perform logic S0 S1 S2 S3 D0 D1 D2 D3 H S4 S5 S6 S7 D4 D5 D6 D7 James Morizio 22
23 Dual-Rail Domino Domino only performs noninverting functions: ND, OR but not NND, NOR, or XOR Dual-rail domino solves this problem Takes true and complementary inputs Produces true and complementary outputs sig_h sig_l Meaning 0 0 Precharged _l _h inputs f f invalid James Morizio 23
24 Example: ND/NND Given _h, _l, B_h, B_l Compute _h = * B, _l = ~( * B) Pulldown networks are conduction complements _l = *B _h _h = *B _l B_l B_h James Morizio 24
25 Example: XOR/XNOR Sometimes possible to share transistors _l = xnor B _h _l _l _h _h = xor B B_l B_h James Morizio 25
26 Domino Summary Domino logic is attractive for high-speed circuits 1.5 2x faster than static CMOS But many challenges: Monotonicity Leakage Charge sharing Noise Widely used in high-performance microprocessors James Morizio 26
27 np-cmos (Zipper CMOS) M p Out1 In 1 In 2 In 3 PDN In 4 PUN Out2 M p Only 1-0 transitions allowed at inputs of PUN Used a lot in the lpha design James Morizio 27
28 np CMOS dder S 1 1 B 1 B 1 1 C i1 1 1 C i2 1 C i1 B B B 0 B 0 C i1 0 B 0 C i0 B 0 0 C i0 S 0 C i0 Carry Path James Morizio 28
29 CMOS Circuit Styles - Summary James Morizio 29
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