# Basics of Digital Logic Design

Save this PDF as:

Size: px
Start display at page:

## Transcription

1 Basics of Digital Logic Design Dr. Arjan Durresi Louisiana State University Baton Rouge, LA LSUEd These slides are available at: Louisiana State University 5- Basics of Digital Logic Design -1 Overview Gates Boolean Algebra Karnough Maps Latches and Flip-Flops Registers Louisiana State University 5- Basics of Digital Logic Design -2

2 Lets Build a Processor Almost ready to move into chapter 5 and start building a processor First, let s review Boolean Logic and build the ALU we ll need (Material from Appendix B) operation a 32 ALU result b Louisiana State University 5- Basics of Digital Logic Design -3 Review: Boolean Algebra & Gates Problem: Consider a logic function with three inputs: A, B, and C. Output D is true if at least one input is true Output E is true if exactly two inputs are true Output F is true only if all three inputs are true Show the truth table for these three functions. Show the Boolean equations for these three functions. Show an implementation consisting of inverters, AND, and OR gates. Louisiana State University 5- Basics of Digital Logic Design -4

3 Signals, Logic Operations and Gates Rather than referring to voltage levels of signals, we shall consider signals that are logically 1 or 0 (or asserted or de-asserted) Logic NOT AND OR XOR operation Gates Output is 1 if: Input is 0 Both inputs are 1s At least one Inputs are not equal are 1s input is 1 Louisiana State University 5- Basics of Digital Logic Design -5 Gates Gates are simplest digital logic circuits, and they implement basic logic operations (functions). Gates are designed using few resistors and transistors. Gates are used to build more complex circuits that implement more complex logic functions. Louisiana State University 5- Basics of Digital Logic Design -6

4 Classification of Logic Functions/Circuits Combinational logic functions (circuits): any number of inputs and outputs outputs yi depend only on current values of inputs xi Logic equations may be used to define a logic function. Example: A logic function with 4 inputs and 2 outputs * used for and, + used for or For sequential functions (circuits): outputs depend on current values of inputs and some internal states. Any logic function (circuit) can be realized using only and, or and not operations (gates). nand and nor operations (gates) are universal. Louisiana State University 5- Basics of Digital Logic Design -7 Basic Laws of Boolean Algebra Louisiana State University 5- Basics of Digital Logic Design -8

5 Simple Circuit Design: Example Given logic equations, it is easy to design a corresponding circuit Louisiana State University 5- Basics of Digital Logic Design -9 Truth Tables Another way (in addition to logic equations) to define certain functionality Problem: their sizes grow exponentially with number of inputs. Louisiana State University 5- Basics of Digital Logic Design -10

6 Logic Equations in Sum of Products Form Systematic way to obtain logic equations from a given truth table. Louisiana State University 5- Basics of Digital Logic Design -11 Programmable Logic Array - PLA PLA structured logic implementation Louisiana State University 5- Basics of Digital Logic Design -12

7 PLA Implementing a logic function Louisiana State University 5- Basics of Digital Logic Design -13 ROM Logic functions can be implemented with: Read-only memory (ROM). Programmable ROMs (PROMs) A ROM has a set of input address lines and a set of outputs. There are m input lines for 2 m addressable entries, called the height The number of bits in each addressable entry is equal to the number of output bits and is sometimes called the width of the ROM. A ROM can encode a collection of logic functions directly from the truth table. For example, if there are n functions with m inputs, we need a ROM with m address lines (and 2 m entries), with each entry being n bits wide. Louisiana State University 5- Basics of Digital Logic Design -14

8 Circuit - Logic Equation - Truth Table For the given logic circuit find its logic equation and truth table. Note that y column above is identical to y 1 column Slide 11. Thus, the given logic function may be defined with different logic equations and then designed by different circuits. Louisiana State University 5- Basics of Digital Logic Design -15 Minimization Applying Boolean Laws Consider one of previous logic equations: But if we start grouping in some other way we may not end up with the minimal equation. Louisiana State University 5- Basics of Digital Logic Design -16

9 Minimization Using Karnough Maps Provides more formal way to minimization Includes 3 steps 1. Form Karnough maps from the given truth table. There is one Karnough map for each output t variable. 2. Group all 1s into as few groups as possible with groups as large as possible. 3. each group makes one term of a minimal logic equation for the given output variable. Forming Karnough maps The key idea in the forming the map is that horizontally and vertically adjacent squares correspond to input variables that differ in one variable only. Thus, a value for the first column (row) can be arbitrary, but labeling of adjacent columns (rows) should be such that those values differ in the value of only one variable. Louisiana State University 5- Basics of Digital Logic Design -17 Minimization Using Karnough Maps Grouping (This step is critical) When two adjacent squares contain 1s, they indicate the possibility of an algebraic simplification and they may be combined in one group of two. Similarly, il l two adjacent pairs of 1s may be combined to form a group of four, then two adjacent groups of four can be combined to form a group of eight, and so on. In general, the number of squares in any valid group must be equal to 2 k. Note that one 1 can be a member of more than one group and keep in mind that you should end up with as few as possible groups which are as large as possible. Finding Product Terms The product term that corresponds to a given group is the product of variables whose values are constant in the group. If the value of input variable x i is 0 for the group, then x i is entered in the product, while if x i has value 1 for the group, then x i is entered in the product. Louisiana State University 5- Basics of Digital Logic Design -18

10 Minimization Using Karnough Maps Louisiana State University 5- Basics of Digital Logic Design -19 Minimization Using Karnough Maps Louisiana State University 5- Basics of Digital Logic Design -20

11 Don t Cares Often in implementing some combinational logic, there are situations where we do not care what the value of some output is because another output t is true or because a subset of the input combinations determines the values of the outputs. Such situations are referred to as don t cares. Don t cares are important because they make it easier to optimize the implementation of a logic function. Louisiana State University 5- Basics of Digital Logic Design -21 Don t cares The full truth table, without don t cares: The truth table written with output don t cares The truth table with the input don t cares, Louisiana State University 5- Basics of Digital Logic Design -22

12 Decoders A full decoder with n input has 2 n outputs. Let inputs be labeled In 0, In 1, In 2,..., In n-1, and let outputs be labeled Out 0, Out 1,..., Out 2n-1 A full decoder functions as follows: Only one of outputs has value 1 (it is active) while all other outputs have value 0. The only output set to 1 is one labeled with the decimal value equal to the (binary) value on input lines In general, a decoder with n inputs may have fewer than 2 n outputs. Sometime those are called partial decoders. Decoders with only one output are common. Louisiana State University 5- Basics of Digital Logic Design Input Full Decoder Louisiana State University 5- Basics of Digital Logic Design -24

13 Multiplexers A basic multiplexer has only one output line z. There are two sets of input lines: data lines and select lines. Let a number of data lines be N, labeled d 0, d 1, d 2,... d N-1. There are m select lines, labeled s 0, s 1,..., s m-1. m is such that any of data lines can be referenced (selected) by a decimal value on select lines. Thus, m has to satisfy the following inequality: 2 m-1 < N 2 m. A multiplexer functions as follows: Output z has the value of the data input line labeled by the value on select lines. Louisiana State University 5- Basics of Digital Logic Design -25 Simplest Basic Multiplexer Simplest mux is one with 2 data input lines and 1 select line. Louisiana State University 5- Basics of Digital Logic Design -26

14 3-Data Multiplexer Truth Table Louisiana State University 5- Basics of Digital Logic Design -27 Complex Multiplexer Instead N single data lines and one output line as in a basic mux, a complex mux has N sets of data lines and one set of output lines and each set has K lines. Louisiana State University 5- Basics of Digital Logic Design -28

15 Memory Elements: Flip-flops, Latches, and Registers All memory elements store state: the output from any memory element depends both on the inputs and on the value that has been stored inside the memory element. All logic blocks containing a memory element contain state and are sequential. Louisiana State University 5- Basics of Digital Logic Design -29 State Elements Unclocked vs. Clocked Clocks used in synchronous logic when should an element that contains state be updated? Falling edge Clock period cycle time Rising edge Louisiana State University 5- Basics of Digital Logic Design -30

16 Clocking Methodology In an edge-triggered methodology, either the rising edge or the falling edge of the clock is active and causes state changes to occur. To ensure that the values written into the state elements on the active clock edge are valid, the clock must have a long enough period so that all the signals in the combinational logic block stabilize, then the clock edge samples those value for storage in the state elements. Louisiana State University 5- Basics of Digital Logic Design -31 Clocking Methodology It is possible to have a state element that is used as both an input and output to the same combinational logic block Louisiana State University 5- Basics of Digital Logic Design -32

17 Latches and Flip-flops Output is equal to the stored value inside the element (don't need to ask for permission to look at the value) Change of state (value) is based on the clock Latches: whenever the inputs change, and the clock is asserted "logically true - could mean electrically low Flip-flop: state changes only on a clock edge (edge-triggered methodology) A clocking methodology defines when signals can be read and written wouldn't want to read a signal at the same time it was being written Louisiana State University 5- Basics of Digital Logic Design -33 R-S Latch (set-reset latch): Simplest Sequential Circuit R-S latch is an unclocked memory element Louisiana State University 5- Basics of Digital Logic Design -34

18 R-S Latch Characteristics R-S letch is a memory element that remembers which of two inputs has most recently had value 1: Outputs Qa =1 & Qb = 0 indicate that S is currently or was 1 last Outputs Qa =0 & Qb = 1 indicate that R is currently or was 1 last Louisiana State University 5- Basics of Digital Logic Design -35 R-S Latch Characteristics (continued) Louisiana State University 5- Basics of Digital Logic Design -36

19 R-S Latch Characteristics (continued) Louisiana State University 5- Basics of Digital Logic Design -37 Gated R-S Latch C input is write enable (not a clock) When C = 1, a gated R-S latch behaves as an ordinary R-S latch. When C = 0, changes in R and S do not influence outputs. Note that the case R =1 & S =1 is still possible, and the unstable state can be reached easily. Louisiana State University 5- Basics of Digital Logic Design -38

20 (Gated) D-Latch Two inputs: the data value to be stored (D) the write enable signal (C) indicating when to read & store D Two outputs: the value of the internal state (Q) and it's complement (often unused) Note: The case R =1 & S =1 is not possible. Louisiana State University 5- Basics of Digital Logic Design -39 D-Latch Functioning When C=1, D-latch state (and Q-output) is identical to D-input, i.e. any change in the value of D-input is immediately followed by the change of Q-output. When C=0, D-latch state is unchanged and it keeps the value it had at the time when C input changed from 1 to 0. Louisiana State University 5- Basics of Digital Logic Design -40

21 D-Latch Functioning Operation of a D latch assuming the output is initially deasserted. When the clock, C, C is asserted, the latch is open and the Q output immediately assumes the value of the D input. Louisiana State University 5- Basics of Digital Logic Design -41 D Flip-Flop Two inputs: the data value to be stored (D) the write enable signal (C) indicating when to read & store D Two outputs: the value of the internal state (Q) and it's complement (often unused) Louisiana State University 5- Basics of Digital Logic Design -42

22 D Flip-Flop Functioning When C changes its value from 1 to 0, i.e. on the falling edge, D-flip flop state (and Q output) gets the value D-input has at that moment, During all other times, D-flip flop state is unchanged and it keeps the value it had at the time of the falling edge of C- input. There is a critical period T cr around the falling edge of C during which value on D should not change. T cr is split into two parts, the setup time before the C edge, and the hold time after the C edge. Louisiana State University 5- Basics of Digital Logic Design -43 D Flip-Flop Functioning Operation of a D flip-flop with a falling-edge trigger, assuming the output is initially deasserted. When the clock input (C) changes from asserted to deasserted, the Q output stores the value of the D input. Compare this behavior to that of the clocked D latch shown in slide 41. In a clocked latch, the stored value and the output, Q, both change whenever C is high, as opposed to only when C transitions. Louisiana State University 5- Basics of Digital Logic Design -44

23 Our Implementation An edge triggered methodology Typical execution: read contents of some state elements, send values through some combinational logic write results to one or more state elements State element 1 Combinational logic State element 2 Clock cycle Louisiana State University 5- Basics of Digital Logic Design -45 Three State D-Latch Three inputs: the data value to be stored (D) the write enable signal (C) indicating when to read & store D the read enable signal (E) indicating when internal state is provided on the output One output: the value of the internal state (Q) Louisiana State University 5- Basics of Digital Logic Design -46

24 Three State D-Latch Functioning Storing (writing) is performed as in the case of the (ordinary) Dlatch) When E=1 (enable read), then the switch is closed, and Q has value (0 or 1) that has been stored (written) into the D-latch When E=0 (disable read), then the switch is open, and Q is in the high impendence state (the third possible value on the output). Louisiana State University 5- Basics of Digital Logic Design -47 Design of 32-bit Register D flip-flop as a building block Thus, 32-bit register has: 33 inputs and 32 outputs There are two operations on a register: read and Write Read operation: register content is always available on Dout0-Dout31 Write operation: provide desired values on Din0- Din31 generate falling edge on the write line Recall critical period T cr around falling edge. Louisiana State University 5- Basics of Digital Logic Design -48

25 Summary Gates Boolean Algebra Karnough Maps Latches and Flip-Flops Registers Louisiana State University 5- Basics of Digital Logic Design -49

### Digital Logic: Boolean Algebra and Gates

Digital Logic: Boolean Algebra and Gates Textbook Chapter 3 CMPE2 Summer 28 Basic Logic Gates CMPE2 Summer 28 Slides by ADB 2 Truth Table The most basic representation of a logic function Lists the output

### Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng

Digital Logic Design Basics Combinational Circuits Sequential Circuits Pu-Jen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction

### CHAPTER 3 Boolean Algebra and Digital Logic

CHAPTER 3 Boolean Algebra and Digital Logic 3.1 Introduction 121 3.2 Boolean Algebra 122 3.2.1 Boolean Expressions 123 3.2.2 Boolean Identities 124 3.2.3 Simplification of Boolean Expressions 126 3.2.4

### Module-3 SEQUENTIAL LOGIC CIRCUITS

Module-3 SEQUENTIAL LOGIC CIRCUITS Till now we studied the logic circuits whose outputs at any instant of time depend only on the input signals present at that time are known as combinational circuits.

### Clocks. Sequential Logic. A clock is a free-running signal with a cycle time.

Clocks A clock is a free-running signal with a cycle time. A clock may be either high or low, and alternates between the two states. The length of time the clock is high before changing states is its high

### Lecture 8: Synchronous Digital Systems

Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered

### The equation for the 3-input XOR gate is derived as follows

The equation for the 3-input XOR gate is derived as follows The last four product terms in the above derivation are the four 1-minterms in the 3-input XOR truth table. For 3 or more inputs, the XOR gate

### Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.

Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. describe how such a flip-flop can be SET and RESET. describe the disadvantage

### Figure 2.1(a) Bistable element circuit.

3.1 Bistable Element Let us look at the inverter. If you provide the inverter input with a 1, the inverter will output a 0. If you do not provide the inverter with an input (that is neither a 0 nor a 1),

### Gates, Circuits, and Boolean Algebra

Gates, Circuits, and Boolean Algebra Computers and Electricity A gate is a device that performs a basic operation on electrical signals Gates are combined into circuits to perform more complicated tasks

### Lecture 10. Latches and Flip-Flops

Logic Design Lecture. Latches and Flip-Flops Prof. Hyung Chul Park & Seung Eun Lee Sequential Logic Outputs of sequential logic depend on current inputs and prior input values Sequential logic might explicitly

### Chapter 14 Sequential logic, Latches and Flip-Flops

Chapter 14 Sequential logic, Latches and Flip-Flops Flops Lesson 2 Sequential logic circuit, Flip Flop and Latch Introduction Ch14L2--"Digital Principles and Design", Raj Kamal, Pearson Education, 2006

### Chapter 5: Sequential Circuits (LATCHES)

Chapter 5: Sequential Circuits (LATCHES) Latches We focuses on sequential circuits, where we add memory to the hardware that we ve already seen Our schedule will be very similar to before: We first show

### Module 4 : Propagation Delays in MOS Lecture 20 : Analyzing Delay in few Sequential Circuits

Module 4 : Propagation Delays in MOS Lecture 20 : Analyzing Delay in few Sequential Circuits Objectives In this lecture you will learn the delays in following circuits Motivation Negative D-Latch S-R Latch

### Memory Elements. Combinational logic cannot remember

Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic

### 1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1.

File: chap04, Chapter 04 1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1. 2. True or False? A gate is a device that accepts a single input signal and produces one

### Chapter 4. Gates and Circuits. Chapter Goals. Chapter Goals. Computers and Electricity. Computers and Electricity. Gates

Chapter Goals Chapter 4 Gates and Circuits Identify the basic gates and describe the behavior of each Describe how gates are implemented using transistors Combine basic gates into circuits Describe the

### ENGIN 112 Intro to Electrical and Computer Engineering

ENGIN 112 Intro to Electrical and Computer Engineering Lecture 19 Sequential Circuits: Latches Overview Circuits require memory to store intermediate data Sequential circuits use a periodic signal to determine

### Sequential Logic. (Materials taken from: Principles of Computer Hardware by Alan Clements )

Sequential Logic (Materials taken from: Principles of Computer Hardware by Alan Clements ) Sequential vs. Combinational Circuits Combinatorial circuits: their outputs are computed entirely from their present

### DIGITAL SYSTEM DESIGN LAB

EXPERIMENT NO: 7 STUDY OF FLIP FLOPS USING GATES AND IC S AIM: To verify various flip-flops like D, T, and JK. APPARATUS REQUIRED: Power supply, Digital Trainer kit, Connecting wires, Patch Chords, IC

### Synchronous Sequential Logic. Logic and Digital System Design - CS 303 Erkay Savaş Sabanci University

Synchronous Sequential Logic Logic and Digital System Design - S 33 Erkay Savaş Sabanci University Sequential Logic Digital circuits we have learned, so far, have been combinational no memory, outputs

### Programmable Logic Devices (PLDs)

Programmable Logic Devices (PLDs) Lesson Objectives: In this lesson you will be introduced to some types of Programmable Logic Devices (PLDs): PROM, PAL, PLA, CPLDs, FPGAs, etc. How to implement digital

### COMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design

PH-315 COMINATIONAL and SEUENTIAL LOGIC CIRCUITS Hardware implementation and software design A La Rosa I PURPOSE: To familiarize with combinational and sequential logic circuits Combinational circuits

### Take-Home Exercise. z y x. Erik Jonsson School of Engineering and Computer Science. The University of Texas at Dallas

Take-Home Exercise Assume you want the counter below to count mod-6 backward. That is, it would count 0-5-4-3-2-1-0, etc. Assume it is reset on startup, and design the wiring to make the counter count

### Lecture 8: Flip-flops

Points Addressed in this Lecture Properties of synchronous and asynchronous sequential circuits Overview of flip-flops and latches Lecture 8: Flip-flops Professor Peter Cheung Department of EEE, Imperial

### Chapter 2 Logic Gates and Introduction to Computer Architecture

Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are

### Lecture 9: Flip-flops

Points Addressed in this Lecture Properties of synchronous and asynchronous sequential circuits Overview of flip-flops and latches Lecture 9: Flip-flops Professor Peter Cheung Department of EEE, Imperial

### CHAPTER 11 LATCHES AND FLIP-FLOPS

CHAPTER 11 LATCHES AND FLIP-FLOPS This chapter in the book includes: Objectives Study Guide 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop

### Karnaugh Maps. Example A B C X 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1. each 1 here gives a minterm e.g.

Karnaugh Maps Yet another way of deriving the simplest Boolean expressions from behaviour. Easier than using algebra (which can be hard if you don't know where you're going). Example A B C X 0 0 0 0 0

### Contents. Chapter 6 Latches and Flip-Flops Page 1 of 27

Chapter 6 Latches and Flip-Flops Page 1 of 27 Contents Latches and Flip-Flops...2 6.1 Bistable lement...3 6.2 SR Latch...4 6.3 SR Latch with nable...6 6.4 Latch...7 6.5 Latch with nable...8 6.6 Clock...9

### Ch 5: Designing a Single Cycle Datapath

Ch 5: Designing a Single Cycle path Computer Systems Architecture CS 365 The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Control Memory path Input Output Today s

### DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 5. LECTURE: SEQUENTIAL CIRCUITS BASICS AND FLIP-FLOPS

DIGITAL TECHNICS Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 5. LECTURE: SEQUENTIAL CIRCUITS BASICS AND FLIP-FLOPS 1st (Autumn) term 2014/2015 5. LECTURE 1. Sequential

### Latches, the D Flip-Flop & Counter Design. ECE 152A Winter 2012

Latches, the D Flip-Flop & Counter Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR

### #5. Show and the AND function can be constructed from two NAND gates.

Study Questions for Digital Logic, Processors and Caches G22.0201 Fall 2009 ANSWERS Digital Logic Read: Sections 3.1 3.3 in the textbook. Handwritten digital lecture notes on the course web page. Study

### Counters and Decoders

Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4-bit ripple-through decade counter with a decimal read-out display. Such a counter

### Chapter 5 Latch and flip-flop

257 Chapter 5 Latch and flip-flop «from the ground up I-2013b --- Copyright Daniele Giacomini -- appunti2@gmail.com http://a3.informaticalibera.net 5.1 Propagation delay..................................

### Design of Digital Systems II Sequential Logic Design Principles (1)

Design of Digital Systems II Sequential Logic Design Principles (1) Moslem Amiri, Václav Přenosil Masaryk University Resource: Digital Design: Principles & Practices by John F. Wakerly Introduction Logic

### 7. Latches and Flip-Flops

Chapter 7 Latches and Flip-Flops Page 1 of 18 7. Latches and Flip-Flops Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can store one bit of information. The

### Chapter 7 Memory and Programmable Logic

NCNU_2013_DD_7_1 Chapter 7 Memory and Programmable Logic 71I 7.1 Introduction ti 7.2 Random Access Memory 7.3 Memory Decoding 7.5 Read Only Memory 7.6 Programmable Logic Array 77P 7.7 Programmable Array

### Sequential Circuits: Latches & Flip-Flops

Sequential Circuits: Latches & Flip-Flops Sequential Circuits Combinational Logic: Output depends only on current input Able to perform useful operations (add/subtract/multiply/encode/decode/ select[mux]/etc

### Let s put together a Manual Processor

Lecture 14 Let s put together a Manual Processor Hardware Lecture 14 Slide 1 The processor Inside every computer there is at least one processor which can take an instruction, some operands and produce

### ENGN3213. Digital Systems & Microprocessors. CLAB 2: Sequential Circuits, ICARUS Verilog

Department of Engineering Australian National University ENGN3213 Digital Systems & Microprocessors CLAB 2: Sequential Circuits, ICARUS Verilog V3.0 Copyright 2010 G.G. Borg ANU Engineering 1 Contents

### CDA 3200 Digital Systems. Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012

CDA 3200 Digital Systems Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012 Outline SR Latch D Latch Edge-Triggered D Flip-Flop (FF) S-R Flip-Flop (FF) J-K Flip-Flop (FF) T Flip-Flop

### Module 3: Floyd, Digital Fundamental

Module 3: Lecturer : Yongsheng Gao Room : Tech - 3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental

### Figure 3. Ball and hill analogy for metastable behavior. S' R' Q Q next Q next ' 0 0 1 1 0 1 1 0 1 0 0 1 1 1 0 0 1 1 1 1 1 0 (a)

Chapter 5 Latches and Flip-Flops Page 1 of 17 5. Latches and Flip-Flops Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can store one bit of information. The

### Sequential Circuits: Latches and Flip-Flops

Sequential Circuits: Latches and Flip-Flops Sequential circuits Output depends on current input and past sequence of input(s) How can we tell if the input is current or from the past? A clock pulse can

### 5. Sequential CMOS Logic Circuits

5. Sequential CMOS Logic Circuits In sequential logic circuits the output signals is determined by the current inputs as well as the previously applied input variables. Fig. 5.1a shows a sequential circuit

### 3.Basic Gate Combinations

3.Basic Gate Combinations 3.1 TTL NAND Gate In logic circuits transistors play the role of switches. For those in the TTL gate the conducting state (on) occurs when the baseemmiter signal is high, and

### RAM & ROM Based Digital Design. ECE 152A Winter 2012

RAM & ROM Based Digital Design ECE 152A Winter 212 Reading Assignment Brown and Vranesic 1 Digital System Design 1.1 Building Block Circuits 1.1.3 Static Random Access Memory (SRAM) 1.1.4 SRAM Blocks in

### 2011, The McGraw-Hill Companies, Inc. Chapter 4

Chapter 4 4.1 The Binary Concept Binary refers to the idea that many things can be thought of as existing in only one of two states. The binary states are 1 and 0 The 1 and 0 can represent: ON or OFF Open

### Basic bistable element. Chapter 6. Latches vs. flip-flops. Flip-flops

Basic bistable element hapter 6 It is a circuit having two stable conditions (states). It can be used to store binary symbols. Flip-Flops and Simple Flip-Flop Applications.. Huang, 24 igital Logic esign

VIDYARTHIPLUS - Anna University Students Online Community CS-6201-DIGITAL PRINCIPLE AND SYSTEM DESIGN TWO MARKS II-SEMESTER ANNA UNIVERSITY REGULATIONS 2013 UNIT I BOOLEAN ALGEBRA AND LOGIC GATES 1. Define

### CS311 Lecture: Sequential Circuits

CS311 Lecture: Sequential Circuits Last revised 8/15/2007 Objectives: 1. To introduce asynchronous and synchronous flip-flops (latches and pulsetriggered, plus asynchronous preset/clear) 2. To introduce

### Lesson 12 Sequential Circuits: Flip-Flops

Lesson 12 Sequential Circuits: Flip-Flops 1. Overview of a Synchronous Sequential Circuit We saw from last lesson that the level sensitive latches could cause instability in a sequential system. This instability

### BINARY CODED DECIMAL: B.C.D.

BINARY CODED DECIMAL: B.C.D. ANOTHER METHOD TO REPRESENT DECIMAL NUMBERS USEFUL BECAUSE MANY DIGITAL DEVICES PROCESS + DISPLAY NUMBERS IN TENS IN BCD EACH NUMBER IS DEFINED BY A BINARY CODE OF 4 BITS.

### Latches and Flip-Flops characterestics & Clock generator circuits

Experiment # 7 Latches and Flip-Flops characterestics & Clock generator circuits OBJECTIVES 1. To be familiarized with D and JK flip-flop ICs and their characteristic tables. 2. Understanding the principles

### ECE 223 Digital Circuits and Systems. Synchronous Logic. M. Sachdev. Dept. of Electrical & Computer Engineering University of Waterloo

ECE 223 Digital Circuits and Systems Synchronous Logic M. Sachdev Dept. of Electrical & Computer Engineering University of Waterloo Sequential Circuits Combinational circuits Output = f (present inputs)

### To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC.

8.1 Objectives To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC. 8.2 Introduction Circuits for counting events are frequently used in computers and other digital

### SEQUENTIAL CIRCUITS. Block diagram. Flip Flop. S-R Flip Flop. Block Diagram. Circuit Diagram

SEQUENTIAL CIRCUITS http://www.tutorialspoint.com/computer_logical_organization/sequential_circuits.htm Copyright tutorialspoint.com The combinational circuit does not use any memory. Hence the previous

### Sequential Circuits: Latches & Flip-Flops

ESD I Lecture 3.b Sequential Circuits: Latches & Flip-Flops 1 Outline Memory elements Latch SR latch D latch Flip-Flop SR flip-flop D flip-flop JK flip-flop T flip-flop 2 Introduction A sequential circuit

### CHAPTER TEN. 10.1 New Truth Table Symbols. 10.1.1 Edges/Transitions. Memory Cells

CHAPTER TEN Memory Cells The previous chapters presented the concepts and tools behind processing binary data. This is only half of the battle though. For example, a logic circuit uses inputs to calculate

### Flip-Flops. Outline: 2. Timing noise

Outline: 2. Timing noise Flip-Flops Signal races, glitches FPGA example ( assign bad) Synchronous circuits and memory Logic gate example 4. Flip-Flop memory RS-latch example D and JK flip-flops Flip-flops

### Modeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit

Modeling Sequential Elements with Verilog Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 4-1 Sequential Circuit Outputs are functions of inputs and present states of storage elements

### Unit 4 Session - 15 Flip-Flops

Objectives Unit 4 Session - 15 Flip-Flops Usage of D flip-flop IC Show the truth table for the edge-triggered D flip-flop and edge-triggered JK flip-flop Discuss some of the timing problems related to

### Problem Session 5. Overview. Part 1: An S-R Latch. Part 2: A D Latch

Problem Session 5 Overview The most basic element of binary storage is the latch, consisting of 2 cross-coupled NAND (or NOR) gates. The D latch, with a write enable input, is a rudimentary storage element.

### So far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs.

equential Logic o far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs. In sequential logic the output of the

### Revision: August 31, 2009 215 E Main Suite D Pullman, WA 99163 (509) 334 6306 Voice and Fax

Module 9: Basic Memory Circuits Revision: August 31, 2009 215 E Main Suite D Pullman, WA 99163 (509) 334 6306 Voice and Fax Overview This module introduces the concept of electronic memory. Memory circuits

### BISTABLE LATCHES AND FLIP-FLOPS

ELET 3156 DL - Laboratory #3 BISTABLE LATCHES AND FLIP-FLOPS No preliminary lab design work is required for this experiment. Introduction: This experiment will demonstrate the properties and illustrate

### l What have discussed up until now & why: l C Programming language l More low-level then Java. l Better idea about what s really going on.

CS211 Computer Architecture l Topics Digital Logic l Transistors (Design & Types) l Logic Gates l Combinational Circuits l K-Maps Class Checkpoint l What have discussed up until now & why: l C Programming

### 7. Sequential Circuits - Combinational vs. Sequential Circuits - 7. Sequential Circuits - State (2) - 7. Sequential Circuits - State (1) -

Sistemas Digitais I LESI - 2º ano Lesson 7 - Sequential Systems Principles Prof. João Miguel Fernandes (miguel@di.uminho.pt) Dept. Informática - Combinational vs. Sequential Circuits - Logic circuits are

### Chapter - 5 FLIP-FLOPS AND SIMPLE FLIP-FLOP APPLICATIONS

Chapter - 5 FLIP-FLOPS AND SIMPLE FLIP-FLOP APPLICATIONS Introduction : Logic circuit is divided into two types. 1. Combinational Logic Circuit 2. Sequential Logic Circuit Definition : 1. Combinational

### Engr354: Digital Logic Circuits

Engr354: igital Circuits Chapter 7 Sequential Elements r. Curtis Nelson Sequential Elements In this chapter you will learn about: circuits that can store information; Basic cells, latches, and flip-flops;

### Lecture 5: Gate Logic Logic Optimization

Lecture 5: Gate Logic Logic Optimization MAH, AEN EE271 Lecture 5 1 Overview Reading McCluskey, Logic Design Principles- or any text in boolean algebra Introduction We could design at the level of irsim

### 150127-Microprocessor & Assembly Language

Chapter 3 Z80 Microprocessor Architecture The Z 80 is one of the most talented 8 bit microprocessors, and many microprocessor-based systems are designed around the Z80. The Z80 microprocessor needs an

### Chapter 2 Digital Components. Section 2.1 Integrated Circuits

Chapter 2 Digital Components Section 2.1 Integrated Circuits An integrated circuit (IC) is a small silicon semiconductor crystal, called a chip, containing the electronic components for the digital gates

### Sequential Logic Design Principles.Latches and Flip-Flops

Sequential Logic Design Principles.Latches and Flip-Flops Doru Todinca Department of Computers Politehnica University of Timisoara Outline Introduction Bistable Elements Latches and Flip-Flops S-R Latch

### Practical Workbook Digital Logic Design / Logic Design & Switching Theory

Practical Workbook Digital Logic Design / Logic Design & Switching Theory Name : Year : Batch : Roll No : Department: Second edition - 2015 Dept. of Computer & Information Systems Engineering NED University

### Experiment 5. Arithmetic Logic Unit (ALU)

Experiment 5 Arithmetic Logic Unit (ALU) Objectives: To implement and test the circuits which constitute the arithmetic logic circuit (ALU). Background Information: The basic blocks of a computer are central

### Upon completion of unit 1.1, students will be able to

Upon completion of unit 1.1, students will be able to 1. Demonstrate safety of the individual, class, and overall environment of the classroom/laboratory, and understand that electricity, even at the nominal

### Simplifying Logic Circuits with Karnaugh Maps

Simplifying Logic Circuits with Karnaugh Maps The circuit at the top right is the logic equivalent of the Boolean expression: f = abc + abc + abc Now, as we have seen, this expression can be simplified

### ASYNCHRONOUS COUNTERS

LB no.. SYNCHONOUS COUNTES. Introduction Counters are sequential logic circuits that counts the pulses applied at their clock input. They usually have 4 bits, delivering at the outputs the corresponding

### 8-bit 4-to-1 Line Multiplexer

Project Part I 8-bit 4-to-1 Line Multiplexer Specification: This section of the project outlines the design of a 4-to-1 multiplexor which takes two 8-bit buses as inputs and produces a single 8-bit bus

### ANALOG & DIGITAL ELECTRONICS

ANALOG & DIGITAL ELECTRONICS Course Instructor: Course No: PH-218 3-1-0-8 Dr. A.P. Vajpeyi E-mail: apvajpeyi@iitg.ernet.in Room No: #305 Department of Physics, Indian Institute of Technology Guwahati,

### ECE380 Digital Logic

ECE38 igital Logic Flip-Flops, Registers and Counters: Flip-Flops r.. J. Jackson Lecture 25- Flip-flops The gated latch circuits presented are level sensitive and can change states more than once during

### CSE140: Components and Design Techniques for Digital Systems

CE4: Components and esign Techniques for igital ystems Tajana imunic osing ources: Where we are now What we ve covered so far (Chap -5, App. A& B) Number representations Boolean algebra OP and PO Logic

### EE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad

A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/20 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,

### Karnaugh Maps. Circuit-wise, this leads to a minimal two-level implementation

Karnaugh Maps Applications of Boolean logic to circuit design The basic Boolean operations are AND, OR and NOT These operations can be combined to form complex expressions, which can also be directly translated

### CHAPTER 11: Flip Flops

CHAPTER 11: Flip Flops In this chapter, you will be building the part of the circuit that controls the command sequencing. The required circuit must operate the counter and the memory chip. When the teach

### Understanding Logic Design

Understanding Logic Design ppendix of your Textbook does not have the needed background information. This document supplements it. When you write add DD R0, R1, R2, you imagine something like this: R1

### Flip-Flops, Registers, Counters, and a Simple Processor

June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 Flip-Flops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number

### Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa

Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation

### 4 Combinational Components

Chapter 4 Combinational Components Page of 8 4 Combinational Components In constructing large digital circuits, instead of starting with the basic gates as building blocks, we often start with larger building

### LAB MANUAL SUBJECT: DIGITAL LOGIC DESIGN AND APPLICATIONS SE (COMPUTERS) SEM III

LAB MANUAL SUBJECT: DIGITAL LOGIC DESIGN AND APPLICATIONS SE (COMPUTERS) SEM III 1 INDEX Sr. No Title of the Experiment 1 Study of BASIC Gates 3 2 Universal Gates 6 3 Study of Full & Half Adder & Subtractor

### Flip-Flops and Sequential Circuit Design. ECE 152A Winter 2012

Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6

### Flip-Flops and Sequential Circuit Design

Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6

### Electronic Troubleshooting. Chapter 10 Digital Circuits

Electronic Troubleshooting Chapter 10 Digital Circuits Digital Circuits Key Aspects Logic Gates Inverters NAND Gates Specialized Test Equipment MOS Circuits Flip-Flops and Counters Logic Gates Characteristics